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PCID and improved laziness

Andy Lutomirski linux-mm lkml 4 versions – In review

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Versions newest first · linked by author and title

  1. v4 Latest10 patches 25 repliesIn review
  2. v311 patches 64 repliesSuperseded
  3. v210 patches 20 repliesSuperseded
Earlier versions · 1
VersionPostedPatchesRepliesStatus
v1 RFC11 patches19 repliesSuperseded

Changes in v4 from the cover letter

- Lots more acks.
- Move comment deletion to the beginning.
- Misc cleanups from lots of reviewers.

Patches in v4 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/10x86/mm: Don't reenter flush_tlb_func_common()arch/x86/mm/tlb.c+15 -20 replies
2/10x86/mm: Delete a big outdated comment about TLB flushingarch/x86/mm/tlb.c+0 -360 replies
3/10x86/mm: Give each mm TLB flush generation a unique IDarch/x86/include/asm/mmu.h arch/x86/include/asm/mmu_context.h arch/x86/include/asm/tlbflush.h +1 more+51 -41 reply
4/10x86/mm: Track the TLB's tlb_gen and update the flushing algorithmarch/x86/include/asm/tlbflush.h arch/x86/mm/tlb.c+135 -100 replies
5/10x86/mm: Rework lazy TLB mode and TLB freshness trackingarch/x86/include/asm/mmu_context.h arch/x86/include/asm/tlbflush.h arch/x86/mm/init.c +2 more+124 -890 replies
6/10x86/mm: Stop calling leave_mm() in idle codearch/ia64/include/asm/acpi.h arch/x86/include/asm/acpi.h arch/x86/mm/tlb.c +2 more+7 -280 replies
7/10x86/mm: Disable PCID on 32-bit kernelsarch/x86/include/asm/disabled-features.h arch/x86/kernel/cpu/bugs.c+11 -10 replies
8/10x86/mm: Add nopcid to turn off PCIDDocumentation/admin-guide/kernel-parameters.txt arch/x86/kernel/cpu/common.c+20 -00 replies
9/10x86/mm: Enable CR4.PCIDE on supported systemsarch/x86/include/asm/tlbflush.h arch/x86/kernel/cpu/common.c arch/x86/xen/enlighten_pv.c+36 -00 replies
10/10x86/mm: Try to preserve old TLB entries using PCIDarch/x86/include/asm/mmu_context.h arch/x86/include/asm/processor-flags.h arch/x86/include/asm/tlbflush.h +2 more+88 -189 replies

Reviews trailers per patch

9 of 10 patches have a Reviewed-by or Acked-by.

PatchNadav AmitThomas GleixnerBorislav PetkovBoris Ostrovsky
1/10R-b R-b
2/10
3/10R-b R-b
4/10R-b R-b
5/10R-b R-b
6/10R-b R-b R-b
7/10R-b R-b R-b
8/10R-b R-b R-b
9/10R-b R-b R-b
10/10R-b R-b

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 4 reviewers.

Read the v4 thread

Cover letter [PATCH v4 00/10] PCID and improved laziness

*** Ingo, even if this misses 4.13, please apply the first patch before *** the merge window.

There are three performance benefits here:

1. TLB flushing is slow. (I.e. the flush itself takes a while.) This avoids many of them when switching tasks by using PCID. In a stupid little benchmark I did, it saves about 100ns on my laptop per context switch. I'll try to improve that benchmark.

2. Mms that have been used recently on a given CPU might get to keep their TLB entries alive across process switches with this patch set. TLB fills are pretty fast on modern CPUs, but they're even faster when they don't happen.

3. Lazy TLB is way better. We used to do two stupid things when we ran kernel threads: we'd send IPIs to flush user contexts on their CPUs and then we'd write to CR3 for no particular reason as an excuse to stop further IPIs. With this patch, we do neither.

This will, in general, perform suboptimally if paravirt TLB flushing is in use (currently just Xen, I think, but Hyper-V is in the works). The code is structured so we could fix it in one of two ways: we could take a spinlock when touching the percpu state so we can update it remotely after a paravirt flush, or we could be more careful about our exactly how we access the state and use cmpxchg16b to do atomic remote updates. (On SMP systems without cmpxchg16b, we'd just skip the optimization entirely.)

This is still missing a final comment-only patch to add overall documentation for the whole thing, but I didn't want to block sending the maybe-hopefully-final code on that.

This is based on tip:x86/mm. The branch is here if you want to play:
https://git.kernel.org/pub/scm/linux/kernel/git/luto/linux.git/log/?h=x86/pcid

In general, performance seems to exceed my expectations. Here are some performance numbers copy-and-pasted from the changelogs for "Rework lazy TLB mode and TLB freshness" and "Try to preserve old TLB entries using PCID":

MADV_DONTNEED; touch the page; switch CPUs using sched_setaffinity. In an unpatched kernel, MADV_DONTNEED will send an IPI to the previous CPU. This is intended to be a nearly worst-case test.

patched:         13.4Aus
unpatched:       21.6Aus

Vitaly's pthread_mmap microbenchmark with 8 threads (on four cores), nrounds = 100, 256M data

patched:         1.1 seconds or so
unpatched:       1.9 seconds or so

ping-pong between two mms on the same CPU using eventfd:
patched: 1.22Aus
patched, nopcid: 1.33Aus
unpatched: 1.34Aus

Same ping-pong, but now touch 512 pages (all zero-page to minimize cache misses) each iteration. dTLB misses are measured by dtlb_load_misses.miss_causes_a_walk:
patched: 1.8Aus 11M dTLB misses
patched, nopcid: 6.2Aus, 207M dTLB misses
unpatched: 6.1Aus, 190M dTLB misses

MADV_DONTNEED; touch the page; switch CPUs using sched_setaffinity. In an unpatched kernel, MADV_DONTNEED will send an IPI to the previous CPU. This is intended to be a nearly worst-case test.
patched: 13.4Aus
unpatched: 21.6Aus

Changes from v3:
- Lots more acks.
- Move comment deletion to the beginning.
- Misc cleanups from lots of reviewers.

Changes from v2:
- Add some Acks
- Move the reentrancy issue to the beginning.
(I also sent the same patch as a standalone fix -- it's just in here
so that this series applies to x86/mm.)
- Fix some comments.

Changes from RFC:
- flush_tlb_func_common() no longer gets reentered (Nadav)
- Fix ASID corruption on unlazying (kbuild bot)
- Move Xen init to the right place
- Misc cleanups

Andy Lutomirski (10):
x86/mm: Don't reenter flush_tlb_func_common()
x86/mm: Delete a big outdated comment about TLB flushing x86/mm: Give each mm TLB flush generation a unique ID x86/mm: Track the TLB's tlb_gen and update the flushing algorithm x86/mm: Rework lazy TLB mode and TLB freshness tracking x86/mm: Stop calling leave_mm() in idle code
x86/mm: Disable PCID on 32-bit kernels
x86/mm: Add nopcid to turn off PCID
x86/mm: Enable CR4.PCIDE on supported systems
x86/mm: Try to preserve old TLB entries using PCID

 Documentation/admin-guide/kernel-parameters.txt |   2 +
 arch/ia64/include/asm/acpi.h                    |   2 -
 arch/x86/include/asm/acpi.h                     |   2 -
 arch/x86/include/asm/disabled-features.h        |   4 +-
 arch/x86/include/asm/mmu.h                      |  25 +-
 arch/x86/include/asm/mmu_context.h              |  15 +-
 arch/x86/include/asm/processor-flags.h          |   2 +
 arch/x86/include/asm/tlbflush.h                 |  87 +++++-
 arch/x86/kernel/cpu/bugs.c                      |   8 +
 arch/x86/kernel/cpu/common.c                    |  40 +++
 arch/x86/mm/init.c                              |   2 +-
 arch/x86/mm/tlb.c                               | 382 ++++++++++++++++--------
 arch/x86/xen/enlighten_pv.c                     |   6 +
 arch/x86/xen/mmu_pv.c                           |   5 +-
 drivers/acpi/processor_idle.c                   |   2 -
 drivers/idle/intel_idle.c                       |   9 +-
 16 files changed, 446 insertions(+), 147 deletions(-)
Signature · 7 lines
2.9.4

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