target/mips: Amend R5900 support
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- v2 Latest12 patches 15 repliesIn review
- v111 patches 1 replySuperseded
Changes in v2 from the cover letter
- Drop rejected rename of ASE_MMI to ASE_TOSHIBA_MMI
- Generate R5900 DIV1 and DIVU1 in gen_div1_tx79
- Generate R5900 MFLO1, MFHI1, MTLO1 and MTHI1 in gen_HILO1_tx79
Patches in v2 No applies recorded yet
Reviews trailers per patch
7 of 12 patches have a Reviewed-by or Acked-by.
| Patch | Fredrik Noring | Richard Henderson | Aleksandar Markovic |
|---|---|---|---|
| 1/12 | |||
| 2/12 | |||
| 3/12 | |||
| 4/12 | T-b | R-b | |
| 5/12 | R-b | ||
| 6/12 | R-b | ||
| 7/12 | R-b | ||
| 8/12 | R-b | ||
| 9/12 | R-b | ||
| 10/12 | T-b | R-b | |
| 11/12 | |||
| 12/12 |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 3 reviewers.
Cover letter [Qemu-devel] [PATCH v2 00/12] target/mips: Amend R5900 support
This series amends the R5900 support with the following noncritical features:
- R5900 MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79.
- R5900 DIV1 and DIVU1 are generated in gen_div1_tx79.
- The R5900 LQ and SQ instructions are now also covered by the Toshiba MMI ASE, as per the TX79 manual[1].
- The three-operand MADD and MADDU instructions specific to the R5900 and the Toshiba TX19, TX39 and TX79 cores are now supported and tested by the R5900 TCG test suite.
- The three-operand MADD1 and MADDU1 pipeline 1 instructions specific to the R5900 and the Toshiba TX79 core are now supported and tested by the R5900 TCG test suite.
- The membership field of struct mips_opcode is now uint64_t instead of unsigned long, that is too small in 32-bit builds.
- R5900 disassembly constants are defined.
- The R5900 instructions DIV1, DIVU1, MFLO, MTLO, MFHI, MTHI, MULT1 and MULTU1 are now disassembled. Unfortunately, the opcodes for MADD1 and MADDU1 clash with the opcodes for CLZ and CLO, resulting in incorrect disassembly. MADD1 and MADDU1 are therefore left undefined.
This series has been successfully built with the 8 different build configurations
{gcc,clang} x -m64 x mips{,64}el-{linux-user,softmmu}in addition successfully completing the R5900 test suite
cd tests/tcg/mips/mipsr5900 && make check
Reference:
[1] "Toshiba TX System RISC TX79 Core Architecture", Toshiba Corporation,
section B.3.2, p. B-4, <https://wiki.qemu.org/File:C790.pdf>.
Changes in v2:
- Drop rejected rename of ASE_MMI to ASE_TOSHIBA_MMI
- Generate R5900 DIV1 and DIVU1 in gen_div1_tx79
- Generate R5900 MFLO1, MFHI1, MTLO1 and MTHI1 in gen_HILO1_tx79
Fredrik Noring (10):
target/mips: Generate R5900 MFLO1, MFHI1, MTLO1 and MTHI1 in gen_HILO1_tx79 target/mips: Generate R5900 DIV1 and DIVU1 in gen_div1_tx79 target/mips: R5900 LQ and SQ also belong to the Toshiba MMI ASE target/mips: Support R5900 three-operand MADD1 and MADDU1 tests/tcg/mips: Test R5900 three-operand MADD
tests/tcg/mips: Test R5900 three-operand MADD1
tests/tcg/mips: Test R5900 three-operand MADDU
tests/tcg/mips: Test R5900 three-operand MADDU1
disas/mips: Define R5900 disassembly constants
disas/mips: Disassemble R5900 DIV[U]1, M{F,T}{LO,HI}1 and MULT[U]1
Philippe Mathieu-Daudé (2):
target/mips: Support Toshiba specific three-operand MADD and MADDU disas/mips: Increase 'member of ISAs' flag holder size
disas/mips.c | 22 +++- target/mips/translate.c | 206 ++++++++++++++++++++++++++---- tests/tcg/mips/mipsr5900/Makefile | 2 + tests/tcg/mips/mipsr5900/madd.c | 78 +++++++++++ tests/tcg/mips/mipsr5900/maddu.c | 70 ++++++++++ 5 files changed, 351 insertions(+), 27 deletions(-) create mode 100644 tests/tcg/mips/mipsr5900/madd.c create mode 100644 tests/tcg/mips/mipsr5900/maddu.c
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