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Fix decoding mechanisms of the R5900

Fredrik Noring qemu-devel 2 versions – In review

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  1. v2 Latest6 patches 16 repliesIn review
  2. v12 patches 11 repliesSuperseded

Changes in v2 from the cover letter

- Fix HI and LO 32-bit truncation with the MIPS64 DSP ASE
- Decode special R5900 opcodes in decode_opc_special_tx79
- Guard check_insn_opc_user_only with INSN_R5900 check
- Guard check_insn with INSN_R5900 check

Patches in v2 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/6target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1target/mips/translate.c+40 -111 reply
2/6target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1target/mips/translate.c+59 -60 replies
3/6target/mips: Fix HI[ac] and LO[ac] 32-bit truncation with MIPS64 DSP ASEtarget/mips/translate.c+4 -321 reply
4/6target/mips: Fix decoding mechanism of special R5900 opcodestarget/mips/translate.c+50 -412 replies
5/6target/mips: Guard check_insn_opc_user_only with INSN_R5900 checktarget/mips/translate.c+12 -41 reply
6/6target/mips: Guard check_insn with INSN_R5900 checktarget/mips/translate.c+5 -21 reply

Reviews trailers per patch

5 of 6 patches have a Reviewed-by or Acked-by.

PatchPhilippe Mathieu-DaudéAleksandar Markovic
1/6R-b
2/6R-b
3/6
4/6R-b
5/6R-b
6/6R-b

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.

Read the v2 thread

Cover letter [Qemu-devel] [PATCH v2 0/6] Fix decoding mechanisms of the R5900

This series amends the R5900 support with the following changes:

- MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of the generic gen_HILO.

- DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic gen_muldiv.

- MOVN, MOVZ, MFHI, MFLO, MTHI, MTLO, MULT, MULTU, DIV, DIVU, DMULT, DMULTU, DDIV, DDIVU and JR are decoded in decode_opc_special_tx79 instead of the generic decode_opc_special_legacy.

- Guard check_insn_opc_user_only with INSN_R5900 check.

- Guard check_insn with INSN_R5900 check.

- Fix HI[ac] and LO[ac] 32-bit truncation with the MIPS64 DSP ASE.

This series has been successfully built with the 8 different build configurations

    {gcc,clang} x -m64 x mips{,64}el-{linux-user,softmmu}

in addition successfully completing the R5900 test suite

    cd tests/tcg/mips/mipsr5900 && make check

Changes in v2:
- Fix HI and LO 32-bit truncation with the MIPS64 DSP ASE
- Decode special R5900 opcodes in decode_opc_special_tx79
- Guard check_insn_opc_user_only with INSN_R5900 check
- Guard check_insn with INSN_R5900 check

Fredrik Noring (6):
target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1 target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1 target/mips: Fix HI[ac] and LO[ac] 32-bit truncation with MIPS64 DSP ASE target/mips: Fix decoding mechanism of special R5900 opcodes target/mips: Guard check_insn_opc_user_only with INSN_R5900 check target/mips: Guard check_insn with INSN_R5900 check

 target/mips/translate.c | 229 +++++++++++++++++++++++++++++-----------
 1 file changed, 170 insertions(+), 59 deletions(-)
Signature · 1 line
2.18.1