V8 more sampling fun 0

mark gross historical-speck 1 version Apr 16, 2020 Applied

Status from this message: I've merged the V8 series with the polishing done by Borislav into the

Get series with b4

b4 am [email protected]

Versions newest first

v1 Latest Apr 16, 20204 patches 28 repliesApplied

Patches in v1 Applied

#	Subject and files	Size	Replies
1/4	V8 more sampling fun 1`arch/x86/include/asm/cpu_device_id.h` `arch/x86/kernel/cpu/match.c` `include/linux/mod_devicetable.h`	+32 -4	0 replies
2/4	V8 more sampling fun 2`arch/x86/kernel/cpu/common.c`	+14 ~~-11~~	0 replies
3/4	V8 more sampling fun 3`Documentation/ABI/testing/sysfs-devices-system-cpu` `Documentation/admin-guide/kernel-parameters.txt` `arch/x86/include/asm/cpufeatures.h` +5 more	+198 -0	0 replies
4/4	V8 more sampling fun 4`Documentation/admin-guide/hw-vuln/index.rst` `Documentation/admin-guide/hw-vuln/special-register-buffer-data-sampling.rst`	+148 -0	0 replies

Reviews trailers per patch

3 of 4 patches have a Reviewed-by or Acked-by of their own; the series has one for all of them.

Patch	Tony Luck	Pawan Gupta	Neelima Krishnan	Josh Poimboeuf
Series	R-b	R-b	T-b	R-b
1/4	R-b
2/4
3/4	R-b	R-b	T-b
4/4	R-b

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 4 reviewers.

Read the v1 thread

Cover letter [MODERATED] [PATCH 0/4] V8 more sampling fun 0

From: mark gross <[email protected]>
Subject: [PATCH 0/4] V8 more sampling fun

This version implement cleanups for readability and alignment with the finalizing Intel white paper on the SRBDS topic. I thank all who've been giving me valuable feedback through this process.

I've included a branch diff between the previous patch set and this one.

---

Special Register Buffer Data Sampling is a sampling type of vulnerability that leaks data across cores sharing the HW-RNG for vulnerable processors.

This leak is fixed by a microcode update and is enabled by default.

This new microcode serializes processor access during execution of RDRAND or RDSEED. It ensures that the shared buffer is overwritten before it is released for reuse.

The mitigation impacts the throughput of the RDRAND and RDSEED instructions and latency of RT processing running on the socket while executing RDRAND or RDSEED. The micro benchmarks calling RDRAND many times show a slowdown.

This patch set enables kernel command line control of this mitigation and exports vulnerability and mitigation status.
This patch set includes 3 patches:
* The first patch adds steppings to x86_cpu_id structure and related macros
* The second patch enables the command line control of the mitigation as well as the sysfs export of vulnerability status.
* The third patch has the Documentation/admin-guide/hw-vuln documentation for this issue and the control over the mitigation.

mark gross (4):
x86/cpu: Add stepping field to x86_cpu_id structure x86/cpu: clean up cpu_matches
x86/speculation: Special Register Buffer Data Sampling (SRBDS)
mitigation control.
x86/speculation: SRBDS vulnerability and mitigation documentation

 .../ABI/testing/sysfs-devices-system-cpu      |   1 +
 Documentation/admin-guide/hw-vuln/index.rst   |   1 +
 .../special-register-buffer-data-sampling.rst | 147 ++++++++++++++++++
 .../admin-guide/kernel-parameters.txt         |  20 +++
 arch/x86/include/asm/cpu_device_id.h          |  27 +++-
 arch/x86/include/asm/cpufeatures.h            |   2 +
 arch/x86/include/asm/msr-index.h              |   4 +
 arch/x86/kernel/cpu/bugs.c                    | 105 +++++++++++++
 arch/x86/kernel/cpu/common.c                  |  81 ++++++++--
 arch/x86/kernel/cpu/cpu.h                     |   2 +
 arch/x86/kernel/cpu/match.c                   |   7 +-
 drivers/base/cpu.c                            |   8 +
 include/linux/mod_devicetable.h               |   2 +
 13 files changed, 392 insertions(+), 15 deletions(-)
 create mode 100644 Documentation/admin-guide/hw-vuln/special-register-buffer-data-sampling.rst

Signature · 1 line

2.17.1

Documentation/admin-guide/hw-vuln/special-register-buffer-data-sampling.rst +14 ~~-15~~

index 9f1ee4064fcd..b3cb73668b08 100644
@@ -14,16 +14,19 @@ core through the special register mechanism that is susceptible to MDS attacks.
 
 Affected processors
 --------------------
-Core models (desktop, mobile, Xeon-E3) that implement RDRAND and/or RDSEED and
-are vulnerable to MFBDS (Micro architectural Fill Buffer Data Sampling) variant
-of MDS (Micro architectural Data Sampling) or to the TAA (TSX Asynchronous
-Abort) when TSX is enabled,
+Core models (desktop, mobile, Xeon-E3) that implement RDRAND and/or RDSEED may
+be affected.
+
+A processor is affected by SRBDS if its Family_Model and stepping is in the
+following list, with the exception of the listed processors exporting MDS_NO
+while Intel TSX is available yet not enabled.  The latter class of processors
+are only affected when Intel TSX is enabled by software using TSX_CTRL_MSR
+otherwise they are not affected.
 
-  =============  ============  ==========================
-  common name    Family_Model  Stepping
-  =============  ============  ==========================
-  Ivybridge      06_3AH        All
 
+  =============  ============  ========
+  common name    Family_Model  Stepping
+  =============  ============  ========
   Haswell        06_3CH        All
   Haswell_L      06_45H        All
   Haswell_G      06_46H        All

@@ -34,14 +37,10 @@ Abort) when TSX is enabled,
   Skylake_L      06_4EH        All
   Skylake        06_5EH        All
 
-  Kabylake_L     06_8EH        <=A
-  Kabylake_L     06_8EH        0xB only if TSX is enabled
-  Kabylake_L     06_8EH        0xC only if TSX is enabled
+  Kabylake_L     06_8EH        <=0xC
 
-  Kabylake       06_9EH        <=B
-  Kabylake       06_9EH        0xC only if TSX is enabled
-  Kabylake       06_9EH        0xD only if TSX is enabled
-  =============  ============  ==========================
+  Kabylake       06_9EH        <=0xD
+  =============  ============  ========
 
 Related CVEs
 ------------

arch/x86/include/asm/cpu_device_id.h +5 -5

index 4f0df2e46c95..10426cd56dca 100644
@@ -22,7 +22,7 @@
 
 #define X86_STEPPINGS(mins, maxs)    GENMASK(maxs, mins)
 /**
- * X86_MATCH_VENDOR_FAM_MODEL_STEPPING_FEATURE - Base macro for CPU matching
+ * X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE - Base macro for CPU matching
  * @_vendor:	The vendor name, e.g. INTEL, AMD, HYGON, ..., ANY
  *		The name is expanded to X86_VENDOR_@_vendor
  * @_family:	The family number or X86_FAMILY_ANY

@@ -39,7 +39,7 @@
  * into another macro at the usage site for good reasons, then please
  * start this local macro with X86_MATCH to allow easy grepping.
  */
-#define X86_MATCH_VENDOR_FAM_MODEL_STEPPING_FEATURE(_vendor, _family, _model, \
+#define X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(_vendor, _family, _model, \
 						    _steppings, _feature, _data) { \
 	.vendor		= X86_VENDOR_##_vendor,				\
 	.family		= _family,					\

@@ -50,7 +50,7 @@
 }
 
 /**
- * X86_MATCH_VENDOR_FAM_MODEL_FEATURE - Base macro for CPU matching
+ * X86_MATCH_VENDOR_FAM_MODEL_FEATURE - Macro for CPU matching
  * @_vendor:	The vendor name, e.g. INTEL, AMD, HYGON, ..., ANY
  *		The name is expanded to X86_VENDOR_@_vendor
  * @_family:	The family number or X86_FAMILY_ANY

@@ -60,11 +60,11 @@
  *		format is unsigned long. The supplied value, pointer
  *		etc. is casted to unsigned long internally.
  *
- * The steppings arguments of X86_MATCH_VENDOR_FAM_MODEL_STEPPING_FEATURE() is
+ * The steppings arguments of X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE() is
  * set to wildcards.
  */
 #define X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, feature, data) \
-	X86_MATCH_VENDOR_FAM_MODEL_STEPPING_FEATURE(vendor, family, model, \
+	X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(vendor, family, model, \
 						X86_STEPPING_ANY, feature, data)
 
 /**

arch/x86/kernel/cpu/bugs.c +13 ~~-24~~

index addef92109fe..f345c24f85d1 100644
@@ -406,17 +406,17 @@ enum srbds_mitigations {
 	SRBDS_MITIGATION_OFF,
 	SRBDS_MITIGATION_UCODE_NEEDED,
 	SRBDS_MITIGATION_FULL,
-	SRBDS_MITIGATION_NOT_AFFECTED_TSX_OFF,
+	SRBDS_MITIGATION_TSX_OFF,
 	SRBDS_MITIGATION_HYPERVISOR,
 };
 
 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
 static const char * const srbds_strings[] = {
-	[SRBDS_MITIGATION_OFF]			= "Vulnerable",
-	[SRBDS_MITIGATION_UCODE_NEEDED]		= "Vulnerable: No microcode",
-	[SRBDS_MITIGATION_FULL]			= "Mitigated: Microcode",
-	[SRBDS_MITIGATION_NOT_AFFECTED_TSX_OFF]	= "Not affected (TSX disabled)",
-	[SRBDS_MITIGATION_HYPERVISOR]		= "Unknown: Dependent on hypervisor status",
+	[SRBDS_MITIGATION_OFF]		= "Vulnerable",
+	[SRBDS_MITIGATION_UCODE_NEEDED]	= "Vulnerable: No microcode",
+	[SRBDS_MITIGATION_FULL]		= "Mitigated: Microcode",
+	[SRBDS_MITIGATION_TSX_OFF]	= "Mitigated: TSX disabled",
+	[SRBDS_MITIGATION_HYPERVISOR]	= "Unknown: Dependent on hypervisor status",
 };
 
 static bool srbds_off;

@@ -438,7 +438,7 @@ void update_srbds_msr(void)
 
 	switch (srbds_mitigation) {
 	case SRBDS_MITIGATION_OFF:
-	case SRBDS_MITIGATION_NOT_AFFECTED_TSX_OFF:
+	case SRBDS_MITIGATION_TSX_OFF:
 		mcu_ctrl |= RNGDS_MITG_DIS;
 		break;
 	case SRBDS_MITIGATION_FULL:

@@ -462,26 +462,15 @@ static void __init srbds_select_mitigation(void)
 	 * TSX that are only exposed to SRBDS when TSX is enabled.
 	 */
 	ia32_cap = x86_read_arch_cap_msr();
-	if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM)) {
-		srbds_mitigation = SRBDS_MITIGATION_NOT_AFFECTED_TSX_OFF;
-		goto out;
-	}
-
-	if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
+	if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM))
+		srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
+	else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
 		srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
-		goto out;
-	}
-
-	if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL)) {
+	else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
 		srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
-		goto out;
-	}
+	else if (cpu_mitigations_off() || srbds_off)
+		srbds_mitigation = SRBDS_MITIGATION_OFF;
 
-	if (cpu_mitigations_off() || srbds_off) {
-		if (srbds_mitigation != SRBDS_MITIGATION_NOT_AFFECTED_TSX_OFF)
-			srbds_mitigation = SRBDS_MITIGATION_OFF;
-	}
-out:
 	update_srbds_msr();
 	pr_info("%s\n", srbds_strings[srbds_mitigation]);
 }

arch/x86/kernel/cpu/common.c +35 ~~-32~~

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Read the cover letter in its thread