Add PCIe support to Sophgo SG2042 SoC
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- v1 Latest5 patches 11 repliesIn review
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/5 | dt-bindings: pci: Add Sophgo SG2042 PCIe hostDocumentation/ | +66 | 3 replies | |
| 2/5 | PCI: cadence: Fix NULL pointer error for opsdrivers/ drivers/ drivers/ | +6 | 2 replies | |
| 3/5 | PCI: sg2042: Add Sophgo SG2042 PCIe driverdrivers/ drivers/ drivers/ | +147 | 6 replies | |
| 4/5 | riscv: sophgo: dts: add pcie controllers for SG2042arch/ | +66 | 0 replies | |
| 5/5 | riscv: sophgo: dts: enable pcie for PioneerBoxarch/ | +12 | 0 replies |
Reviews trailers per patch
1 of 5 patches has a Reviewed-by or Acked-by.
| Patch | Rob Herring (Arm) |
|---|---|
| 1/5 | R-b |
| 2/5 | |
| 3/5 | |
| 4/5 | |
| 5/5 |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [PATCH 0/5] Add PCIe support to Sophgo SG2042 SoC
From: Chen Wang <[email protected]>
Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode.
This is a completely rewritten PCIe driver for SG2042. It inherits some previously submitted patch codes (not merged into the upstream mainline), but the biggest difference is that the support for compatibility with old 32-bit PCIe devices has been removed in this new version. This is because after discussing with community users, we felt that there was not much demand for support for old devices, so we made a new design based on the simplified design and practical needs. If someone really needs to play with old devices, we can provide them with some necessary hack patches in the downstream repository.
Since the new design is quite different from the old code, I will release it as a new patch series. The old patch series can be found in here [old-series].
Note, regarding [2/5] of this patchset, this fix is introduced because the pcie->ops pointer is not filled in SG2042 PCIe driver. This is not a must-have parameter, if we use it w/o checking will cause a null pointer access error during runtime.
This patchset is based on v6.17-rc1.
Thanks,
Chen
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Chen Wang (5):
dt-bindings: pci: Add Sophgo SG2042 PCIe host
PCI: cadence: Fix NULL pointer error for ops
PCI: sg2042: Add Sophgo SG2042 PCIe driver
riscv: sophgo: dts: add pcie controllers for SG2042
riscv: sophgo: dts: enable pcie for PioneerBox
.../bindings/pci/sophgo,sg2042-pcie-host.yaml | 66 +++++++++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 66 +++++++++ drivers/pci/controller/cadence/Kconfig | 12 ++ drivers/pci/controller/cadence/Makefile | 1 + .../controller/cadence/pcie-cadence-host.c | 2 +- drivers/pci/controller/cadence/pcie-cadence.c | 4 +- drivers/pci/controller/cadence/pcie-cadence.h | 6 +- drivers/pci/controller/cadence/pcie-sg2042.c | 134 ++++++++++++++++++ 9 files changed, 297 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c
base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
Signature · 1 line
2.34.1