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Add Altera Agilex5 DWC3 support

[email protected] linux-devicetree linux-usb lkml 2 versions – In review

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  1. v2 Latest4 patches 3 repliesIn review
  2. v14 patches 6 repliesSuperseded

Changes in v2 from the cover letter

* Update new binding name to match compatible.
* Update binding to use single node instead of parent child node structure.
* Update binding according to comments from maintainer.
* Split USB3 and USB2 changes in dts into separate commits.
* Update to use flattened model and use dwc3-generic-plat driver instead of dwc3-of-simple driver.
* Add dma_addressable_bits as a dwc3 property which is set by the glue driver which is used to configure the dma mask in the core driver.

Patches in v2 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/4dt-bindings: usb: dwc3: Add support for Altera Agilex5 DWC3Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml+96 -01 reply
2/4arm64: dts: intel: agilex5: Add USB3.1 support for Agilex5 SoCDKarch/arm64/boot/dts/intel/socfpga_agilex5.dtsi arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts+23 -00 replies
3/4arm64: dts: intel: agilex5: Remove usb0 in Agilex5 SoCDKarch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts+0 -50 replies
4/4usb: dwc3: Add support for Agilex5 in dwc3-generic-platform driverdrivers/usb/dwc3/core.c drivers/usb/dwc3/core.h drivers/usb/dwc3/dwc3-generic-plat.c+29 -22 replies

Reviews trailers per patch

No Reviewed-by, Acked-by or Tested-by trailers for v2 yet.

Read the v2 thread

Cover letter [PATCH v2 0/4] Add Altera Agilex5 DWC3 support

From: Adrian Ng Ho Yin <[email protected]>

Agilex5 integrates a Synopsys DesignWare USB3 controller via a SoC-specific wrapper that requires dedicated clock, reset, PHY, and optional SMMU integration. In addition, the Agilex5 has a 40-bit DMA address bus limitation. When SMMU is enabled, using the default 64-bit DMA mask can result in address truncation and subsequent translation faults. This series addresses that limitation by allowing the glue driver to constrain the DMA mask appropriately.

This series adds a device tree binding for the Agilex5 DWC3 wrapper and introduces the corresponding USB3.1 controller node in the Agilex5 SoC and SoCDK device trees. As the SoCDK only exposes the USB3.1 interface, the unused USB0 node is removed. The series also extends the dwc3 generic platform driver with Agilex5-specific configuration support, including limiting the DMA addressable width to 40 bits to avoid DMA faults when SMMU is enabled.

---
changelog:
v1->v2:
* Update new binding name to match compatible.
* Update binding to use single node instead of parent child node structure.
* Update binding according to comments from maintainer.
* Split USB3 and USB2 changes in dts into separate commits.
* Update to use flattened model and use dwc3-generic-plat driver instead of dwc3-of-simple driver.
* Add dma_addressable_bits as a dwc3 property which is set by the glue driver which is used to configure the dma mask in the core driver.

v1 patch link:
https://lore.kernel.org/all/[email protected]/
---

Adrian Ng Ho Yin (4):
dt-bindings: usb: dwc3: Add support for Altera Agilex5 DWC3
arm64: dts: intel: agilex5: Add USB3.1 support for Agilex5 SoCDK
arm64: dts: intel: agilex5: Remove usb0 in Agilex5 SoCDK
usb: dwc3: Add support for Agilex5 in dwc3-generic-platform driver

 .../bindings/usb/altr,agilex5-dwc3.yaml       | 96 +++++++++++++++++++
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 18 ++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  4 +-
 drivers/usb/dwc3/core.c                       |  6 +-
 drivers/usb/dwc3/core.h                       |  5 +
 drivers/usb/dwc3/dwc3-generic-plat.c          | 20 +++-
 6 files changed, 145 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
Signature · 1 line
2.49.GIT