clock: versal-clk: Fix Versal NET clock binding and switch to CCF

This series fixes the Versal NET clock controller DT binding validation and switches the platform to use the firmware-based CCF clock interface.

One patch extracts zynqmp to own DT binding file.

Another restructures the if/then conditions in the versal-clk binding schema so that xlnx,versal-net-clk is matched first before falling back to xlnx,versal-clk. This fixes false "too long" validation errors caused by both conditions matching simultaneously when the fallback compatible is present. A dedicated example for the Versal NET 3-clock configuration is added and all examples are split into separate blocks for independent validation.

The last patch switches Versal NET from static fixed-clock definitions to the firmware-based clock interface, enabling proper clock management through platform firmware. DT macro headers for clocks, power domains and resets are added.

Thanks,
Michal

Changes in v5:
- update commit message s/zynqmp-clk/versal-clk/
- Also update firmware node to match xlnx,versal-firmware enforced by schema (change taken from next patch)
- Update commit message
- Move change done in v4 to previous patch where issue started.

Changes in v4:
- simplify expression to [0-6][0-9] from 0[0-9||[1-6][0-9]
- Update regex from previous patch
- Also update firmware node to match xlnx,versal-firmware enforced by schema

Changes in v3:
- new patch in series
- New patch in series
- Cover change in zynqmp-firmware.yaml
- Move clock-cells to be the last in the example
- Remove comment around (Optional clock) which is obvious from schema itself
- Move clock-cells to be the last property in the example
- use 2 spaces for indentation in example to follow the same style which is already used
- Add fixed tag
- Remove interrupt from zynqmp-power - Versal NET is using event framework instead. No interrupt is required.
- Remove unused GEM{0,1}_REF_{R,T}X macros
- Update commit message
- s/zynqmp/versal-net/ in subject
- Update copyrights
- Make all macro values lower case
- Fix guarding macro names

Changes in v2:
- New patch in series
- Split zynqmp-clk from versal-clk
- Update logic without ZynqMP part in this file and have if/else only around min/maxItems
- use clock-<HZ> node name for fixed clocks
- Reuse existing versal-net-clk.dtsi file

Michal Simek (5):
dt-bindings: firmware: xilinx: Add missing example for ZynqMP
dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names
pattern
dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema
dt-bindings: clock: versal-clk: Fix Versal NET clock validation
arm64: versal-net: Switch Versal NET to firmware clock interface

 .../bindings/clock/xlnx,versal-clk.yaml       |  93 ++---
 .../bindings/clock/xlnx,zynqmp-clk.yaml       |  68 ++++
 .../firmware/xilinx/xlnx,zynqmp-firmware.yaml |  15 +-
 .../arm64/boot/dts/xilinx/versal-net-clk.dtsi | 345 +++++++++++++-----
 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h  | 123 +++++++
 .../boot/dts/xilinx/xlnx-versal-net-clk.h     |  74 ++++
 .../boot/dts/xilinx/xlnx-versal-net-power.h   |  38 ++
 .../boot/dts/xilinx/xlnx-versal-net-resets.h  |  53 +++
 .../arm64/boot/dts/xilinx/xlnx-versal-power.h |  55 +++
 .../boot/dts/xilinx/xlnx-versal-resets.h      | 106 ++++++
 10 files changed, 797 insertions(+), 173 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-clk.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-clk.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-power.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-net-resets.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-power.h
 create mode 100644 arch/arm64/boot/dts/xilinx/xlnx-versal-resets.h

---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
branch: xnext/versal-net

2.43.0