counter: add GPIO-based counter driver

This series adds a counter subsystem driver that does quadrature encoder position tracking with plain GPIO pins and edge interrupts. Compared to interrupt-cnt.c (pulse-only) it provides full A/B/Index decoding and exposes the counter sysfs ABI. Target hardware is low- to medium-speed rotary encoders on SoCs without a free eQEP / FTM / etc. Benchmark rig: github.com/wafgo/qenc-bench.

v7 addresses Williams review comments on v6 [1]. Main change is the reworked index GPIO handling, rest is smaller stuff.

Tested in quadrature x4 mode (both directions) on a AM642 board with a real encoder on GPIOs.

== Changes in v7 ==

Driver:
- check the enabled state in the ISRs before reading the GPIOs. This also moves the reads under the spinlock, so concurrent A/B ISRs cant evaluate the state out of order anymore.
- dropped the spinlock from the simple single-field read callbacks
- smaller cleanups from the review (b_irq_users increment split from the zero check, current_state variable gone, ternary in index_pulse, GPIO_COUNTER_NUM_COUNTS_MAX rename, GPIO_COUNTER_MAX_INDEX removed)
- index GPIOs now live per Count (idx_gpio/idx_irq/has_index in gpio_counter_count_priv), the n_idx based arrays are gone
- enable_write: dont resample prev_a/prev_b when Count 2 gets enabled, that would corrupt the quadrature state of an already running Count 1. Also sync the direction from the current B level on enable in pulse-direction mode, otherwise the counter steps in the wrong direction until the next B edge if B moved while disabled (both reported by the Sashiko review on v6).

Regarding the IRQ enable ordering question from the review: I kept setting cp->enabled = true before enable_irq(). The prev sampling and the enabled flag are done atomic under the lock, so the first edge after enable_irq() sees consistent state. With the other order there is a window where an edge fires and gets droped.

Binding:
- index-gpios (array, position selects the Count) is replaced by two seperate properties index1-gpios and index2-gpios, matching the signal-a-gpios/signal-b-gpios naming. So Count 2 can have an index line without a dummy entry for Count 1.
- dropped Conors Ack [2] because of the binding change, a fresh one would be appreciated

The 2D synapse array preparation for a future pulse-direction mode on Count 2 is not part of this revision, that was flagged as follow-up material.

[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/20260629-trekker-estranged-754e9bfada16@spud/

Wadim Mueller (3):
dt-bindings: counter: add gpio-counter binding
counter: add GPIO-based counter driver
MAINTAINERS: add entry for GPIO counter driver

 .../bindings/counter/gpio-counter.yaml        |   60 +
 MAINTAINERS                                   |    7 +
 drivers/counter/Kconfig                       |   17 +
 drivers/counter/Makefile                      |    1 +
 drivers/counter/gpio-counter.c                | 1011 +++++++++++++++++
 5 files changed, 1096 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/counter/gpio-counter.yaml
 create mode 100644 drivers/counter/gpio-counter.c

base-commit: 3cd8b194bf3428dfa53120fee47e827a7c495815

2.43.0