clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes
Get series with b4
b4 am [email protected]Versions newest first
- v1 Latest2 of 3 patches 0 repliesNew
2 of 3 patches are in this archive. The cover letter announces 3.
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/3 | clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks | +0 | 0 replies | |
| 3/3 | clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk | +0 | 0 replies |
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v1 yet.
Cover letter [PATCH 0/3] clk: sunxi-ng: sun6i-a31: Register offset and clk flag fixes
Quoted 11 lines · Maxime Ripard
Hi,
Quoted 8 lines · Chen-Yu Tsai
Hi,
Here are 3 fixes for the new sunxi-ng clk driver for sun6i-a31 recently introduced for 4.9. The issues were noticed while working on the display pipeline for the A31/A31s. The second patch follows what Maxime has done for the A33 CCU driver. The third issue was noticed while doing the first patch.
Quoted 7 lines
Quoted 2 lines
I hope we can get this into 4.9 as well, either right in -rc1, or in a later -rc.
Acked-by Maxime Ripard <[email protected]>Stephen, could you apply those patches directly on top of my previous PR, or do you want me to send another one?
I can apply directly to clk-next.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project