tegra: Add display driver and LCD support for Seaboard
Get series with b4
b4 am '[email protected]'Versions newest first
- v1 Latest0 of 17 patches 0 repliesNew
Patches in v1 No applies recorded yet
None of the 17 patches the cover letter announces are in this archive.
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v1 yet.
Cover letter [U-Boot] [PATCH 0/17] tegra: Add display driver and LCD support for Seaboard
Am 18.07.2012 08:51, schrieb Simon Glass:
Quoted 124 lines
+Tom, Stephen
Quoted 111 lines · Thierry Reding
Quoted 101 lines · Simon Glass
Hi Christian,
Quoted 88 lines · Christian Kroehnert
Quoted 69 lines · Simon Glass
This series adds support for the Tegra2x's display peripheral. This supports the LCD display on Seaboard and we use this to enable console output in U-Boot on the LCD.
Configuration is via the device tree. Proposed bindings are included in this series.
To improve performance two optimisations are offered:
1. The LCD frame buffer is cached, with the cache being flushed after each call
puts(). This dramatically increases performance (around 10x). This requires a few additions to the ARM cache support.2. The console supports scrolling in steps of more than 1 line. This speeds up scrolling output considerably, particularly commands like 'printenv' which display a lot of output. This requires a new CONFIG and a change to the
console_scrollup()function.Mayuresh Kulkarni (1):
tegra: Enable display/lcd support on SeaboardSimon Glass (15):
fdt: Add function to look up a phandle's register address
fdt: Add header guard tofdtdec.h
fdt: Correct GPIO name access in fdtdec
tegra: Add display support to funcmux
tegra: fdt: Add LCD definitions for Tegra
tegra: Add support for PWFM
tegra: Add LCD driver
tegra: Add LCD support to Nvidia boards
arm: Add control over cachability of memory regions
lcd: AddCONFIG_ALIGN_LCD_TO_SECTIONto align lcd for MMU
lcd: Add support for flushing LCD fb from dcache after update
tegra: Align LCD frame buffer to section boundary
tegra: Support control of cache settings for LCD
tegra: fdt: Add LCD definitions for Seaboard
lcd: AddCONSOLE_SCROLL_LINESoption to speed consoleWei Ni (1):
tegra: Add SOC support for display/lcdREADME | 16 + arch/arm/cpu/armv7/cache_v7.c | 11 + arch/arm/cpu/armv7/tegra2/Makefile | 1 + arch/arm/cpu/armv7/tegra2/display.c | 271 +++++++++++ arch/arm/cpu/armv7/tegra2/funcmux.c | 39 ++ arch/arm/cpu/armv7/tegra2/pwfm.c | 40 ++ arch/arm/dts/tegra20.dtsi | 25 + arch/arm/include/asm/arch-tegra2/dc.h | 544 +++++++++++++++++++++++ arch/arm/include/asm/arch-tegra2/display.h | 133 ++++++ arch/arm/include/asm/arch-tegra2/pwfm.h | 54 +++ arch/arm/include/asm/system.h | 30 ++ arch/arm/lib/cache-cp15.c | 62 +++- board/nvidia/common/board.c | 21 +- board/nvidia/dts/tegra2-seaboard.dts | 21 + common/cmd_echo.c | 3 +- common/lcd.c | 85 +++- doc/device-tree-bindings/video/nvidia-video.txt | 92 ++++ drivers/video/Makefile | 1 + drivers/video/tegra.c | 388 ++++++++++++++++ include/configs/seaboard.h | 12 +- include/configs/tegra2-common.h | 1 + include/fdtdec.h | 17 + include/lcd.h | 11 + lib/fdtdec.c | 15 +- 24 files changed, 1862 insertions(+), 31 deletions(-)Quoted 8 lines
create mode 100644
arch/arm/cpu/armv7/tegra2/display.ccreate mode 100644arch/arm/cpu/armv7/tegra2/pwfm.ccreate mode 100644arch/arm/include/asm/arch-tegra2/dc.hcreate mode 100644arch/arm/include/asm/arch-tegra2/display.hcreate mode 100644arch/arm/include/asm/arch-tegra2/pwfm.hcreate mode 100644doc/device-tree-bindings/video/nvidia-video.txtcreate mode 100644drivers/video/tegra.cHi Simon,
I have added your patch sources manually into the "Prepare v2012.04-rc1 release", because I got errors at apply. Also I added a device tree source file for Harmony.
I tested the device tree source file for Harmony and your patch sources on our Harmony hardware and generated a new patch file:
Quoted 6 lines
I hope it's all okay, this my first patch release.
In the
display.csource file I implemented a bug fix, because I get garbled images on the LCD without this fix.I see this code:
Quoted 8 lines
u32 m_value; m_value = readl(0x54202e04); m_value &= ~0x2; writel(m_value, 0x54202e04);What register are you actually writing here? I can't find it in my manual, but maybe I just haven't seen that address.
Quoted 8 lines
At the time I did look for that register as well but couldn't find anything. But I believe that we saw the garbled display issue that has been mentioned in another thread. If I remember correctly this particular register write was the fix for it.
But I wasn't very much involved at the time, so maybe Christian can clarify. However I was going to test your newest version of the LCD patch series on our hardware and see if the issue is still there.
Quoted 9 lines
Does anyone know what this register is for? I am reluctant to add this code to the patch without at least a comment.
Quoted 2 lines
Thierry
Regards,
Simon
Also in our manual this register is not documented. The garbed images emerged when the tempature of ARM processor was high (after 2min standby and then a reboot) or if I cool it down with ice spay before the boot up. So when I didn't cleared this register, I got garbled images. I don't have the device here, on which I have tested, so I can reproduce it. Thierry have tested it on a other device with the newest version of the LCD patch and he can't reproduce the garbed images.
Best regards
Christian