mpc8245 timer

The following code appears in u-boot-0.3.0/cpu/mpc824x/cpu.c

/*
* Get timebase clock frequency (like cpu_clk in Hz)
* This is the sys_logic_clk (memory bus) divided by 4 */
unsigned long get_tbclk (void)

{
	return ((get_bus_freq (0) + 2L) / 4L);
}

However, in Table 11-11 of the _MPC8245 Integrated Processor User's Manual_, there is the statement "The timers operate at 1/8 the speed of the SDRAM_CLK signal."

Should the divisor in get_tbclk( ) be 8L for the MPC8245?

(I know there are several '8245 and '8241 boards using PPCBoot and/or U-Boot, so my guess is that the manual is wrong, but I didn't see anything in the errata about this.)

This was designed for MPC8240 systems; where the timebase registers are incremented once for every for sys_logic_clk cycles. And all systems I've seen so far used sys_logic_clk = 2 x PCI bus frequency.

You can easily try it out: how long does "sleep 10" sleep on your system?

Best regards,

Wolfgang Denk

Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd at denx.de
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