add bcm5752 support plus some cleanup to tg3

PATCH Applied John W. Linville 6 participants 45 messages Apr 13, 2005 – May 27, 2005

Subsystems (3)

Networking Network drivers PCI

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John W. Linville

author

2005-04-13 23:38 UTC #0 lore raw

cover add bcm5752 support plus some cleanup to tg3

Add support to tg3 for bcm5752 hardware. Also clean-up a lot of multi-way if statements and replace them with checks of flags representing classes of tg3 hardware.

Patches to follow...

John W. Linville

author

2005-04-13 23:38 UTC #1 lore raw

PATCH 1/10 tg3: add basic bcm5752 support

Track-down all references to ASIC_REV_5750 and mirror them with references to the newly defined ASIC_REV_5752.

Signed-off-by John W. Linville <[email protected]>

---

 drivers/net/tg3.c |   63 ++++++++++++++++++++++++++++++++++++------------------
 1 files changed, 42 insertions(+), 21 deletions(-)

drivers/net/tg3.c renamed from drivers/net/tg3.c.orig +42 ~~-21~~

@@ -86,7 +86,8 @@
 #define TG3_MIN_MTU			60
 #define TG3_MAX_MTU(tp)	\
 	((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && \
-	  GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) ? 9000 : 1500)
+	  GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 && \
+	  GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) ? 9000 : 1500)
 
 /* These numbers seem to be hard coded in the NIC firmware somehow.
  * You can't change the ring sizes, but you can change where you place

@@ -861,7 +862,8 @@ out:
 		/* Cannot do read-modify-write on 5401 */
 		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
 	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
-		   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+		   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
+		   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
 		u32 phy_reg;
 
 		/* Set bit 14 with read-modify-write to preserve other bits */

@@ -874,7 +876,8 @@ out:
 	 * jumbo frames transmission.
 	 */
 	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
-	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
+	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
 		u32 phy_reg;
 
 		if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))

@@ -1068,7 +1071,8 @@ static int tg3_set_power_state(struct tg
 			mac_mode = MAC_MODE_PORT_MODE_TBI;
 		}
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750)
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
+		    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
 			tw32(MAC_LED_CTRL, tp->led_ctrl);
 
 		if (((power_caps & PCI_PM_CAP_PME_D3cold) &&

@@ -3967,7 +3971,8 @@ static int tg3_chip_reset(struct tg3 *tp
 		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
 		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
 			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
-			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
 				tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
 		}
 	}

@@ -5041,7 +5046,8 @@ static int tg3_reset_hw(struct tg3 *tp)
 	tw32(GRC_MISC_CFG, val);
 
 	/* Initialize MBUF/DESC pool. */
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
 		/* Do nothing.  */
 	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
 		tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);

@@ -5240,7 +5246,8 @@ static int tg3_reset_hw(struct tg3 *tp)
 		rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
 	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
-	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
+	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
 		if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
 		    (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
 		     tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {

@@ -5355,7 +5362,8 @@ static int tg3_reset_hw(struct tg3 *tp)
 
 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
 	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
 		if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
 		    (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
 		     tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {

@@ -7028,7 +7036,8 @@ static void __devinit tg3_get_nvram_info
 		tw32(NVRAM_CFG1, nvcfg1);
 	}
 
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
 		switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
 			case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
 				tp->nvram_jedecnum = JEDEC_ATMEL;

@@ -7093,7 +7102,8 @@ static void __devinit tg3_nvram_init(str
 	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
 		tp->tg3_flags |= TG3_FLAG_NVRAM;
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
 			u32 nvaccess = tr32(NVRAM_ACCESS);
 
 			tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);

@@ -7102,7 +7112,8 @@ static void __devinit tg3_nvram_init(str
 		tg3_get_nvram_info(tp);
 		tg3_get_nvram_size(tp);
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
 			u32 nvaccess = tr32(NVRAM_ACCESS);
 
 			tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);

@@ -7195,7 +7206,8 @@ static int tg3_nvram_read(struct tg3 *tp
 
 	tg3_nvram_lock(tp);
 
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
 		u32 nvaccess = tr32(NVRAM_ACCESS);
 
 		tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);

@@ -7210,7 +7222,8 @@ static int tg3_nvram_read(struct tg3 *tp
 
 	tg3_nvram_unlock(tp);
 
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
 		u32 nvaccess = tr32(NVRAM_ACCESS);
 
 		tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);

@@ -7438,7 +7451,8 @@ static int tg3_nvram_write_block(struct 
 
 		tg3_nvram_lock(tp);
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
 			u32 nvaccess = tr32(NVRAM_ACCESS);
 
 			tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);

@@ -7463,7 +7477,8 @@ static int tg3_nvram_write_block(struct 
 		grc_mode = tr32(GRC_MODE);
 		tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
 			u32 nvaccess = tr32(NVRAM_ACCESS);
 
 			tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);

@@ -7581,7 +7596,8 @@ static int __devinit tg3_phy_probe(struc
 		} else
 			eeprom_phy_id = 0;
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
 			led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
 				    SHASTA_EXT_LED_MODE_MASK);
 		} else

@@ -7634,7 +7650,8 @@ static int __devinit tg3_phy_probe(struc
 
 		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
 			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
-			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
 				tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
 		}
 		if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)

@@ -7932,10 +7949,12 @@ static int __devinit tg3_get_invariants(
 	tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
 
 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
-	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
+	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
+	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752))
 		tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
 
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
 		tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
 
 	if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)

@@ -8066,7 +8085,8 @@ static int __devinit tg3_get_invariants(
 		tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
 
 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
 		tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
 
 	/* Only 5701 and later support tagged irq status mode.

@@ -8462,7 +8482,8 @@ static int __devinit tg3_test_dma(struct
 		tp->dma_rwctrl |= 0x00180000;
 	} else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
 		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
-		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
 			tp->dma_rwctrl |= 0x003f0000;
 		else
 			tp->dma_rwctrl |= 0x003f000f;

John W. Linville

author

2005-04-13 23:38 UTC #2 lore raw

PATCH 2/10 tg3: add bcm5752 to tg3_pci_tbl

Add hard-coded definition of bcm5752 PCI ID to tg3_pci_tbl.

Signed-off-by John W. Linville <[email protected]>

---
Next patch will change entry to use pci_ids.h-based definition.

 drivers/net/tg3.c |    2 ++
 1 files changed, 2 insertions(+)

drivers/net/tg3.c renamed from drivers/net/tg3.c.orig +2 -0

@@ -206,6 +206,8 @@ static struct pci_device_id tg3_pci_tbl[
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+	{ PCI_VENDOR_ID_BROADCOM, 0x1600, /* TIGON3_5752 */
+	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,

John W. Linville

author

2005-04-13 23:38 UTC #3 lore raw

PATCH 3/10 tg3: add bcm5752 entry to pci_ids.h

Add proper entry for bcm5752 PCI ID to pci_ids.h, and use it in tg3.

Signed-off-by John W. Linville <[email protected]>

---
I did this separately in case patches like this (i.e. new PCI IDs) need to come from more "official" sources.

 drivers/net/tg3.c       |    2 +-
 include/linux/pci_ids.h |    1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

drivers/net/tg3.c renamed from drivers/net/tg3.c.orig +1 -1

@@ -206,7 +206,7 @@ static struct pci_device_id tg3_pci_tbl[
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
-	{ PCI_VENDOR_ID_BROADCOM, 0x1600, /* TIGON3_5752 */
+	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

include/linux/pci_ids.h renamed from include/linux/pci_ids.h.orig +1 -0

@@ -2065,6 +2065,7 @@
 #define PCI_DEVICE_ID_AFAVLAB_P030	0x2182
 
 #define PCI_VENDOR_ID_BROADCOM		0x14e4
+#define PCI_DEVICE_ID_TIGON3_5752	0x1600
 #define PCI_DEVICE_ID_TIGON3_5700	0x1644
 #define PCI_DEVICE_ID_TIGON3_5701	0x1645
 #define PCI_DEVICE_ID_TIGON3_5702	0x1646

John W. Linville

author

2005-04-13 23:38 UTC #4 lore raw

PATCH 4/10 tg3: use TG3_FLG2_5705_PLUS instead of multi-way if's

Replace a number of three-way if statements checking for 5705, 5750, and 5752 to reference the equivalent TG3_FLG2_5705_PLUS flag instead.

Signed-off-by John W. Linville <[email protected]>

---

 drivers/net/tg3.c |   16 ++++------------
 1 files changed, 4 insertions(+), 12 deletions(-)

drivers/net/tg3.c renamed from drivers/net/tg3.c.orig +4 ~~-12~~

@@ -85,9 +85,7 @@
 /* hardware minimum and maximum for a single frame's data payload */
 #define TG3_MIN_MTU			60
 #define TG3_MAX_MTU(tp)	\
-	((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && \
-	  GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 && \
-	  GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) ? 9000 : 1500)
+	(!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
 
 /* These numbers seem to be hard coded in the NIC firmware somehow.
  * You can't change the ring sizes, but you can change where you place

@@ -863,9 +861,7 @@ out:
 	if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
 		/* Cannot do read-modify-write on 5401 */
 		tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
-	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
-		   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
-		   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
+	} else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
 		u32 phy_reg;
 
 		/* Set bit 14 with read-modify-write to preserve other bits */

@@ -877,9 +873,7 @@ out:
 	/* Set phy register 0x10 bit 0 to high fifo elasticity to support
 	 * jumbo frames transmission.
 	 */
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
-	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
-	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
+	if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
 		u32 phy_reg;
 
 		if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))

@@ -8483,9 +8477,7 @@ static int __devinit tg3_test_dma(struct
 		/* DMA read watermark not used on PCIE */
 		tp->dma_rwctrl |= 0x00180000;
 	} else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
-		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+		if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
 			tp->dma_rwctrl |= 0x003f0000;
 		else
 			tp->dma_rwctrl |= 0x003f000f;

John W. Linville

author

2005-04-13 23:38 UTC #5 lore raw

PATCH 5/10 tg3: define TG3_FLG2_5750_PLUS flag

Define TG3_FLG2_5750_PLUS flag and set it in tg3_get_invariants for ASIC_REV_5750 or ASIC_REV_5752.

Signed-off-by John W. Linville <[email protected]>

---

 drivers/net/tg3.c |    4 ++++
 drivers/net/tg3.h |    1 +
 2 files changed, 5 insertions(+)

drivers/net/tg3.c renamed from drivers/net/tg3.c.orig +4 -0

@@ -7951,6 +7951,10 @@ static int __devinit tg3_get_invariants(
 
 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
+
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
 		tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
 
 	if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)

drivers/net/tg3.h renamed from drivers/net/tg3.h.orig +1 -0

@@ -2101,6 +2101,7 @@ struct tg3 {
 #define TG3_FLG2_HW_TSO			0x00010000
 #define TG3_FLG2_SERDES_PREEMPHASIS	0x00020000
 #define TG3_FLG2_5705_PLUS		0x00040000
+#define TG3_FLG2_5750_PLUS		0x00080000
 
 	u32				split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ		3

John W. Linville

author

2005-04-13 23:38 UTC #6 lore raw

PATCH 6/10 tg3: use new TG3_FLG2_5750_PLUS flag

Replace a number of two-way if statements checking for 5750, and/or 5752 to reference the newly-defined TG3_FLG2_5750_PLUS flag instead.

Signed-off-by John W. Linville <[email protected]>

---

 drivers/net/tg3.c |   38 +++++++++++++-------------------------
 1 files changed, 13 insertions(+), 25 deletions(-)

drivers/net/tg3.c renamed from drivers/net/tg3.c.orig +13 ~~-25~~

@@ -1067,8 +1067,7 @@ static int tg3_set_power_state(struct tg
 			mac_mode = MAC_MODE_PORT_MODE_TBI;
 		}
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
-		    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
+		if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
 			tw32(MAC_LED_CTRL, tp->led_ctrl);
 
 		if (((power_caps & PCI_PM_CAP_PME_D3cold) &&

@@ -3967,8 +3966,7 @@ static int tg3_chip_reset(struct tg3 *tp
 		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
 		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
 			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
-			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+			if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
 				tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
 		}
 	}

@@ -5042,8 +5040,7 @@ static int tg3_reset_hw(struct tg3 *tp)
 	tw32(GRC_MISC_CFG, val);
 
 	/* Initialize MBUF/DESC pool. */
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
 		/* Do nothing.  */
 	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
 		tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);

@@ -7032,8 +7029,7 @@ static void __devinit tg3_get_nvram_info
 		tw32(NVRAM_CFG1, nvcfg1);
 	}
 
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
 		switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
 			case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
 				tp->nvram_jedecnum = JEDEC_ATMEL;

@@ -7098,8 +7094,7 @@ static void __devinit tg3_nvram_init(str
 	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
 		tp->tg3_flags |= TG3_FLAG_NVRAM;
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
 			u32 nvaccess = tr32(NVRAM_ACCESS);
 
 			tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);

@@ -7108,8 +7103,7 @@ static void __devinit tg3_nvram_init(str
 		tg3_get_nvram_info(tp);
 		tg3_get_nvram_size(tp);
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
 			u32 nvaccess = tr32(NVRAM_ACCESS);
 
 			tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);

@@ -7202,8 +7196,7 @@ static int tg3_nvram_read(struct tg3 *tp
 
 	tg3_nvram_lock(tp);
 
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
 		u32 nvaccess = tr32(NVRAM_ACCESS);
 
 		tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);

@@ -7218,8 +7211,7 @@ static int tg3_nvram_read(struct tg3 *tp
 
 	tg3_nvram_unlock(tp);
 
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
 		u32 nvaccess = tr32(NVRAM_ACCESS);
 
 		tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);

@@ -7447,8 +7439,7 @@ static int tg3_nvram_write_block(struct 
 
 		tg3_nvram_lock(tp);
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
 			u32 nvaccess = tr32(NVRAM_ACCESS);
 
 			tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);

@@ -7473,8 +7464,7 @@ static int tg3_nvram_write_block(struct 
 		grc_mode = tr32(GRC_MODE);
 		tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
 			u32 nvaccess = tr32(NVRAM_ACCESS);
 
 			tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);

@@ -7592,11 +7582,10 @@ static int __devinit tg3_phy_probe(struc
 		} else
 			eeprom_phy_id = 0;
 
-		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
 			led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
 				    SHASTA_EXT_LED_MODE_MASK);
-		} else
+		else
 			led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
 
 		switch (led_cfg) {

@@ -7646,8 +7635,7 @@ static int __devinit tg3_phy_probe(struc
 
 		if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
 			tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
-			if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-			    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+			if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
 				tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
 		}
 		if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)

John W. Linville

author

2005-04-13 23:38 UTC #7 lore raw

PATCH 7/10 tg3: more use of TG3_FLG2_5705_PLUS flag

Rewrite of a couple of troublesome multi-way if statements to use TG3_FLG2_5705_PLUS flag.

Signed-off-by John W. Linville <[email protected]>

---

 drivers/net/tg3.c |   12 ++++--------
 1 files changed, 4 insertions(+), 8 deletions(-)

drivers/net/tg3.c renamed from drivers/net/tg3.c.orig +4 -8

@@ -5237,10 +5237,8 @@ static int tg3_reset_hw(struct tg3 *tp)
 		      RDMAC_MODE_LNGREAD_ENAB);
 	if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
 		rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
-	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
-	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
-	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
+	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
+	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
 		if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
 		    (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
 		     tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {

@@ -5353,10 +5351,8 @@ static int tg3_reset_hw(struct tg3 *tp)
 	       WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
 	       WDMAC_MODE_LNGREAD_ENAB);
 
-	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
-	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
-	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-	     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
+	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
+	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
 		if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
 		    (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
 		     tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {

John W. Linville

author

2005-04-13 23:38 UTC #8 lore raw

PATCH 8/10 tg3: use TG3_FLG2_57{05,50}_PLUS flags in tg3_get_invariants

Rewrite checks in tg3_get_invariants to use TG3_FLG2_5705_PLUS and TG3_FLG2_5750_PLUS flags.

Signed-off-by John W. Linville <[email protected]>

---

 drivers/net/tg3.c |    7 ++-----
 1 files changed, 2 insertions(+), 5 deletions(-)

drivers/net/tg3.c renamed from drivers/net/tg3.c.orig +2 -5

@@ -7937,8 +7937,7 @@ static int __devinit tg3_get_invariants(
 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
 		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
 
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
 		tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
 
 	if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)

@@ -8068,9 +8067,7 @@ static int __devinit tg3_get_invariants(
 	if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
 		tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
 
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
 		tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
 
 	/* Only 5701 and later support tagged irq status mode.

John W. Linville

author

2005-04-13 23:38 UTC #9 lore raw

PATCH 9/10 tg3: check TG3_FLG2_5750_PLUS flag to set TG3_FLG2_5705_PLUS flag

Use check of TG3_FLG2_5750_PLUS in tg3_get_invariants to set TG3_FLG2_5705_PLUS flag.

Signed-off-by John W. Linville <[email protected]>

---

 drivers/net/tg3.c |    9 ++++-----
 1 files changed, 4 insertions(+), 5 deletions(-)

drivers/net/tg3.c renamed from drivers/net/tg3.c.orig +4 -5

@@ -7928,15 +7928,14 @@ static int __devinit tg3_get_invariants(
 	tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
 	tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
 
-	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
-	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
-	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752))
-		tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
-
 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
 	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
 		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
 
+	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
+	    (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
+		tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
+
 	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
 		tp->tg3_flags2 |= TG3_FLG2_HW_TSO;

John W. Linville

author

2005-04-13 23:38 UTC #10 lore raw

PATCH 10/10 tg3: add support for bcm5752 rev a1

Replace existing ASIC_REV_5752 definition with ASIC_REV_5752_A0, and add definition for ASIC_REV_5752_A1. Then, add ASIC_REV_5752_A1 to check for setting TG3_FLG2_5750_PLUS in tg3_get_invariants.

Signed-off-by John W. Linville <[email protected]>

---

 drivers/net/tg3.c |    3 ++-
 drivers/net/tg3.h |    5 ++++-
 2 files changed, 6 insertions(+), 2 deletions(-)

drivers/net/tg3.c renamed from drivers/net/tg3.c.orig +2 -1

@@ -7929,7 +7929,8 @@ static int __devinit tg3_get_invariants(
 	tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
 
 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752_A0 ||
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752_A1)
 		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
 
 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||

drivers/net/tg3.h renamed from drivers/net/tg3.h.orig +4 -1

@@ -125,6 +125,8 @@
 #define  CHIPREV_ID_5750_A0		 0x4000
 #define  CHIPREV_ID_5750_A1		 0x4001
 #define  CHIPREV_ID_5750_A3		 0x4003
+#define  CHIPREV_ID_5752_A0		 0x5000
+#define  CHIPREV_ID_5752_A1		 0x6001
 #define  GET_ASIC_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700			 0x07
 #define   ASIC_REV_5701			 0x00

@@ -132,7 +134,8 @@
 #define   ASIC_REV_5704			 0x02
 #define   ASIC_REV_5705			 0x03
 #define   ASIC_REV_5750			 0x04
-#define   ASIC_REV_5752			 0x05
+#define   ASIC_REV_5752_A0		 0x05
+#define   ASIC_REV_5752_A1		 0x06
 #define  GET_CHIP_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX		 0x70
 #define   CHIPREV_5700_BX		 0x71

Michael Chan

2005-04-18 06:42 UTC #32 lore raw

cover tg3: Add complete support for 5752

In reply to John W. Linville

These patches should be applied on top of John Linville's patches posted a few days ago.

The last 2 patches are MSI patches for 5751 C0 and 5752. They are very similar to the MSI patches posted a few weeks ago. I've modified the MSI test patch to display a warning message to ask the user to report the failure if the MSI test fails. If Jeff still objects to this, then just skip patch 11 but apply patch 10 which enables MSI on the latest chips.

Michael Chan

2005-04-18 06:50 UTC #33 lore raw

PATCH 1/11 tg3: Minor 5752 fixes

Some minor 5752 fixes mostly for correctness and add 5752 PHY ID.

Signed-off-by Michael Chan <[email protected]>

drivers/net/tg3.c +17 -7

diff -Nru 100/drivers/net/tg3.c 101/drivers/net/tg3.c
@@ -1094,7 +1094,7 @@
 		     CLOCK_CTRL_ALTCLK |
 		     CLOCK_CTRL_PWRDOWN_PLL133);
 		udelay(40);
-	} else if (!((GET_ASIC_REV(tp->pci_chip_rev_id) == 5750) &&
+	} else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
 		     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
 		u32 newbits1, newbits2;

@@ -5237,8 +5237,11 @@
 		      RDMAC_MODE_LNGREAD_ENAB);
 	if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
 		rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
-	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
-	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
+
+	/* If statement applies to 5705 and 5750 PCI devices only */
+	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
+	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
+	    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
 		if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
 		    (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
 		     tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {

@@ -5249,6 +5252,9 @@
 		}
 	}
 
+	if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
+		rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
+
 #if TG3_TSO_SUPPORT != 0
 	if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
 		rdmac_mode |= (1 << 27);

@@ -5351,8 +5357,10 @@
 	       WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
 	       WDMAC_MODE_LNGREAD_ENAB);
 
-	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
-	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
+	/* If statement applies to 5705 and 5750 PCI devices only */
+	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
+	     tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
 		if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
 		    (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
 		     tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {

@@ -7025,7 +7033,7 @@
 		tw32(NVRAM_CFG1, nvcfg1);
 	}
 
-	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
 		switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
 			case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
 				tp->nvram_jedecnum = JEDEC_ATMEL;

@@ -8462,7 +8470,8 @@
 		/* DMA read watermark not used on PCIE */
 		tp->dma_rwctrl |= 0x00180000;
 	} else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
-		if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
+		    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
 			tp->dma_rwctrl |= 0x003f0000;
 		else
 			tp->dma_rwctrl |= 0x003f000f;

@@ -8628,6 +8637,7 @@
 	case PHY_ID_BCM5704:	return "5704";
 	case PHY_ID_BCM5705:	return "5705";
 	case PHY_ID_BCM5750:	return "5750";
+	case PHY_ID_BCM5752:	return "5752";
 	case PHY_ID_BCM8002:	return "8002/serdes";
 	case 0:			return "serdes";
 	default:		return "unknown";

drivers/net/tg3.h +1 -0

diff -Nru 100/drivers/net/tg3.h 101/drivers/net/tg3.h
@@ -2150,6 +2150,7 @@
 #define PHY_ID_BCM5704			0x60008190
 #define PHY_ID_BCM5705			0x600081a0
 #define PHY_ID_BCM5750			0x60008180
+#define PHY_ID_BCM5752			0x60008100
 #define PHY_ID_BCM8002			0x60010140
 #define PHY_ID_INVALID			0xffffffff
 #define PHY_ID_REV_MASK			0x0000000f

Michael Chan

2005-04-18 07:08 UTC #34 lore raw

PATCH 2/11 tg3: Split tg3_phy_probe into 2 functions

Split the 1st half of tg3_phy_probe() into tg3_get_eeprom_hw_cfg() so that the TG3_FLAG_EEPROM_WRITE_PROT can be determined before calling tg3_set_power_state() in tg3_get_invariants(). This will allow tg3_set_power_state() to drive the GPIOs correctly based on the config. information in eeprom.

On the 5752, there are no pull-up resistors on the GPIO pins and it is necessary to drive the unused GPIOs as output.

Signed-off-by Michael Chan <[email protected]>

drivers/net/tg3.c +39 ~~-17~~

diff -Nru 101/drivers/net/tg3.c 102/drivers/net/tg3.c
@@ -7542,21 +7542,27 @@
 	return NULL;
 }
 
-static int __devinit tg3_phy_probe(struct tg3 *tp)
+/* Since this function may be called in D3-hot power state during
+ * tg3_init_one(), only config cycles are allowed.
+ */
+static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
 {
-	u32 eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
-	u32 hw_phy_id, hw_phy_id_masked;
 	u32 val;
-	int eeprom_signature_found, eeprom_phy_serdes, err;
+
+	/* Make sure register accesses (indirect or otherwise)
+	 * will function correctly.
+	 */
+	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
+			       tp->misc_host_ctrl);
 
 	tp->phy_id = PHY_ID_INVALID;
-	eeprom_phy_id = PHY_ID_INVALID;
-	eeprom_phy_serdes = 0;
-	eeprom_signature_found = 0;
+	tp->led_ctrl = LED_CTRL_MODE_PHY_1;
+
 	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
 	if (val == NIC_SRAM_DATA_SIG_MAGIC) {
 		u32 nic_cfg, led_cfg;
-		u32 nic_phy_id, ver, cfg2 = 0;
+		u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
+		int eeprom_phy_serdes = 0;
 
 		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
 		tp->nic_sram_data_cfg = nic_cfg;

@@ -7569,8 +7575,6 @@
 		    (ver > 0) && (ver < 0x100))
 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
 
-		eeprom_signature_found = 1;
-
 		if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
 		    NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
 			eeprom_phy_serdes = 1;

@@ -7586,6 +7590,10 @@
 		} else
 			eeprom_phy_id = 0;
 
+		tp->phy_id = eeprom_phy_id;
+		if (eeprom_phy_serdes)
+			tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
+
 		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
 			led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
 				    SHASTA_EXT_LED_MODE_MASK);

@@ -7653,6 +7661,13 @@
 		if (cfg2 & (1 << 18))
 			tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
 	}
+}
+
+static int __devinit tg3_phy_probe(struct tg3 *tp)
+{
+	u32 hw_phy_id_1, hw_phy_id_2;
+	u32 hw_phy_id, hw_phy_id_masked;
+	int err;
 
 	/* Reading the PHY ID register can conflict with ASF
 	 * firwmare access to the PHY hardware.

@@ -7681,10 +7696,10 @@
 		if (hw_phy_id_masked == PHY_ID_BCM8002)
 			tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
 	} else {
-		if (eeprom_signature_found) {
-			tp->phy_id = eeprom_phy_id;
-			if (eeprom_phy_serdes)
-				tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
+		if (tp->phy_id != PHY_ID_INVALID) {
+			/* Do nothing, phy ID already set up in
+			 * tg3_get_eeprom_hw_cfg().
+			 */
 		} else {
 			struct subsys_tbl_ent *p;

@@ -7755,9 +7770,6 @@
 		err = tg3_init_5401phy_dsp(tp);
 	}
 
-	if (!eeprom_signature_found)
-		tp->led_ctrl = LED_CTRL_MODE_PHY_1;
-
 	if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
 		tp->link_config.advertising =
 			(ADVERTISED_1000baseT_Half |

@@ -8023,6 +8035,16 @@
 		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
 	}
 
+	/* Get eeprom hw config before calling tg3_set_power_state().
+	 * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
+	 * determined before calling tg3_set_power_state() so that
+	 * we know whether or not to switch out of Vaux power.
+	 * When the flag is set, it means that GPIO1 is used for eeprom
+	 * write protect and also implies that it is a LOM where GPIOs
+	 * are not used to switch power.
+	 */ 
+	tg3_get_eeprom_hw_cfg(tp);
+
 	/* Force the chip into D0. */
 	err = tg3_set_power_state(tp, 0);
 	if (err) {

Michael Chan

2005-04-18 07:22 UTC #35 lore raw

PATCH 3/11 tg3: Setup proper GPIO settings

In reply to Michael Chan

Setup proper GPIO settings in tp->grc_local_ctrl before calling tg3_set_power() state in tg3_get_invariants() and after chip reset.

Signed-off-by Michael Chan <[email protected]>

drivers/net/tg3.c +28 -6

diff -Nru 102/drivers/net/tg3.c 103/drivers/net/tg3.c
@@ -5336,10 +5336,23 @@
 	tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
 	udelay(40);
 
-	tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
-	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
+	/* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
+	 * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
+	 * register to preserve the GPIO settings for LOMs. The GPIOs,
+	 * whether used as inputs or outputs, are set by boot code after
+	 * reset.
+	 */
+	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
+		u32 gpio_mask;
+
+		gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
+			    GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
+		tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
+
+		/* GPIO1 must be driven high for eeprom write protect */
 		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
 				       GRC_LCLCTRL_GPIO_OUTPUT1);
+	}
 	tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
 	udelay(100);

@@ -7430,8 +7443,8 @@
 	}
 
 	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
-		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-		       GRC_LCLCTRL_GPIO_OE1);
+		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
+		       ~GRC_LCLCTRL_GPIO_OUTPUT1);
 		udelay(40);
 	}

@@ -7477,8 +7490,7 @@
 	}
 
 	if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
-		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
-		       GRC_LCLCTRL_GPIO_OE1 | GRC_LCLCTRL_GPIO_OUTPUT1);
+		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
 		udelay(40);
 	}

@@ -8045,6 +8057,16 @@
 	 */ 
 	tg3_get_eeprom_hw_cfg(tp);
 
+	/* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
+	 * GPIO1 driven high will bring 5700's external PHY out of reset.
+	 * It is also used as eeprom write protect on LOMs.
+	 */
+	tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
+	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
+	    (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
+		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
+				       GRC_LCLCTRL_GPIO_OUTPUT1);
+
 	/* Force the chip into D0. */
 	err = tg3_set_power_state(tp, 0);
 	if (err) {

Michael Chan

2005-04-18 07:28 UTC #36 lore raw

PATCH 4/11 tg3: Fix tg3_set_power_state()

In reply to Michael Chan

Fix tg3_set_power_state to drive GPIOs properly based on the TG3_FLAG_EEPROM_WRITE_PROTECT flag. Some delays are also added after D0 and D3 power state changes.

Signed-off-by Michael Chan <[email protected]>

drivers/net/tg3.c +8 -2

diff -Nru 103/drivers/net/tg3.c 104/drivers/net/tg3.c
@@ -1005,8 +1005,13 @@
 		pci_write_config_word(tp->pdev,
 				      pm + PCI_PM_CTRL,
 				      power_control);
-		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
-		udelay(100);
+		udelay(100);	/* Delay after power state change */
+
+		/* Switch out of Vaux if it is not a LOM */
+		if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
+			tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
+			udelay(100);
+		}
 
 		return 0;

@@ -1151,6 +1156,7 @@
 
 	/* Finally, set the new power state. */
 	pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
+	udelay(100);	/* Delay after power state change */
 
 	tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);

Michael Chan

2005-04-18 07:37 UTC #37 lore raw

PATCH 5/11 tg3: Workaround 5752 A0 chip ID

In reply to Michael Chan

The 5752 A0 chip ID is wrong in hardware. The simplest way to workaround it is to change it to the correct value in tp->pci_chip_rev_id. This way, it is easier to check for the ASIC_REV_5752 in the rest of the driver.

Signed-off-by Michael Chan <[email protected]>

drivers/net/tg3.c +7 -2

diff -Nru 104/drivers/net/tg3.c 105/drivers/net/tg3.c
@@ -7952,6 +7952,12 @@
 	tp->pci_chip_rev_id = (misc_ctrl_reg >>
 			       MISC_HOST_CTRL_CHIPREV_SHIFT);
 
+	/* Wrong chip ID in 5752 A0. This code can be removed later
+	 * as A0 is not in production.
+	 */
+	if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
+		tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
+
 	/* Initialize misc host control in PCI block. */
 	tp->misc_host_ctrl |= (misc_ctrl_reg &
 			       MISC_HOST_CTRL_CHIPREV);

@@ -7967,8 +7973,7 @@
 	tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
 
 	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752_A0 ||
-	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752_A1)
+	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
 		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
 
 	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||

drivers/net/tg3.h +3 -3

diff -Nru 104/drivers/net/tg3.h 105/drivers/net/tg3.h
@@ -125,7 +125,8 @@
 #define  CHIPREV_ID_5750_A0		 0x4000
 #define  CHIPREV_ID_5750_A1		 0x4001
 #define  CHIPREV_ID_5750_A3		 0x4003
-#define  CHIPREV_ID_5752_A0		 0x5000
+#define  CHIPREV_ID_5752_A0_HW		 0x5000
+#define  CHIPREV_ID_5752_A0		 0x6000
 #define  CHIPREV_ID_5752_A1		 0x6001
 #define  GET_ASIC_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700			 0x07

@@ -134,8 +135,7 @@
 #define   ASIC_REV_5704			 0x02
 #define   ASIC_REV_5705			 0x03
 #define   ASIC_REV_5750			 0x04
-#define   ASIC_REV_5752_A0		 0x05
-#define   ASIC_REV_5752_A1		 0x06
+#define   ASIC_REV_5752			 0x06
 #define  GET_CHIP_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX		 0x70
 #define   CHIPREV_5700_BX		 0x71

Michael Chan

2005-04-18 07:41 UTC #43 lore raw

PATCH 6/11 tg3: Add GPIO3 for 5752

In reply to Michael Chan

Add bit definitions for the new GPIO3 in 5752. GPIO3 must be driven as output when it is unused.

Signed-off-by Michael Chan <[email protected]>

drivers/net/tg3.c +10 -0

diff -Nru 105/drivers/net/tg3.c 106/drivers/net/tg3.c
@@ -5353,6 +5353,11 @@
 
 		gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
 			    GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
+
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+			gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
+				     GRC_LCLCTRL_GPIO_OUTPUT3;
+
 		tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
 
 		/* GPIO1 must be driven high for eeprom write protect */

@@ -8077,6 +8082,11 @@
 	    (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
 		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
 				       GRC_LCLCTRL_GPIO_OUTPUT1);
+	/* Unused GPIO3 must be driven as output on 5752 because there
+	 * are no pull-up resistors on unused GPIO pins.
+	 */
+	else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
 
 	/* Force the chip into D0. */
 	err = tg3_set_power_state(tp, 0);

drivers/net/tg3.h +3 -0

diff -Nru 105/drivers/net/tg3.h 106/drivers/net/tg3.h
@@ -1311,6 +1311,9 @@
 #define  GRC_LCLCTRL_CLEARINT		0x00000002
 #define  GRC_LCLCTRL_SETINT		0x00000004
 #define  GRC_LCLCTRL_INT_ON_ATTN	0x00000008
+#define  GRC_LCLCTRL_GPIO_INPUT3	0x00000020
+#define  GRC_LCLCTRL_GPIO_OE3		0x00000040
+#define  GRC_LCLCTRL_GPIO_OUTPUT3	0x00000080
 #define  GRC_LCLCTRL_GPIO_INPUT0	0x00000100
 #define  GRC_LCLCTRL_GPIO_INPUT1	0x00000200
 #define  GRC_LCLCTRL_GPIO_INPUT2	0x00000400

Michael Chan

2005-04-18 07:47 UTC #38 lore raw

PATCH 7/11 tg3: Add nvram detection for 5752

In reply to Michael Chan

Signed-off-by Michael Chan <[email protected]>

drivers/net/tg3.c +62 -1

diff -Nru 106/drivers/net/tg3.c 107/drivers/net/tg3.c
@@ -7096,6 +7096,63 @@
 	}
 }
 
+static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
+{
+	u32 nvcfg1;
+
+	nvcfg1 = tr32(NVRAM_CFG1);
+
+	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
+		case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
+		case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
+			tp->nvram_jedecnum = JEDEC_ATMEL;
+			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+			break;
+		case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
+			tp->nvram_jedecnum = JEDEC_ATMEL;
+			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+			tp->tg3_flags2 |= TG3_FLG2_FLASH;
+			break;
+		case FLASH_5752VENDOR_ST_M45PE10:
+		case FLASH_5752VENDOR_ST_M45PE20:
+		case FLASH_5752VENDOR_ST_M45PE40:
+			tp->nvram_jedecnum = JEDEC_ST;
+			tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
+			tp->tg3_flags2 |= TG3_FLG2_FLASH;
+			break;
+	}
+
+	if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
+		switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
+			case FLASH_5752PAGE_SIZE_256:
+				tp->nvram_pagesize = 256;
+				break;
+			case FLASH_5752PAGE_SIZE_512:
+				tp->nvram_pagesize = 512;
+				break;
+			case FLASH_5752PAGE_SIZE_1K:
+				tp->nvram_pagesize = 1024;
+				break;
+			case FLASH_5752PAGE_SIZE_2K:
+				tp->nvram_pagesize = 2048;
+				break;
+			case FLASH_5752PAGE_SIZE_4K:
+				tp->nvram_pagesize = 4096;
+				break;
+			case FLASH_5752PAGE_SIZE_264:
+				tp->nvram_pagesize = 264;
+				break;
+		}
+	}
+	else {
+		/* For eeprom, set pagesize to maximum eeprom size */
+		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
+
+		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
+		tw32(NVRAM_CFG1, nvcfg1);
+	}
+}
+
 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
 static void __devinit tg3_nvram_init(struct tg3 *tp)
 {

@@ -7128,7 +7185,11 @@
 			tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
 		}
 
-		tg3_get_nvram_info(tp);
+		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+			tg3_get_5752_nvram_info(tp);
+		else
+			tg3_get_nvram_info(tp);
+
 		tg3_get_nvram_size(tp);
 
 		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {

drivers/net/tg3.h +14 -0

diff -Nru 106/drivers/net/tg3.h 107/drivers/net/tg3.h
@@ -1399,6 +1399,20 @@
 #define  FLASH_VENDOR_SAIFUN		 0x01000003
 #define  FLASH_VENDOR_SST_SMALL		 0x00000001
 #define  FLASH_VENDOR_SST_LARGE		 0x02000001
+#define  NVRAM_CFG1_5752VENDOR_MASK	 0x03c00003
+#define  FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ	 0x00000000
+#define  FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ	 0x02000000
+#define  FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED	 0x02000003
+#define  FLASH_5752VENDOR_ST_M45PE10	 0x02400000
+#define  FLASH_5752VENDOR_ST_M45PE20	 0x02400002
+#define  FLASH_5752VENDOR_ST_M45PE40	 0x02400001
+#define  NVRAM_CFG1_5752PAGE_SIZE_MASK	 0x70000000
+#define  FLASH_5752PAGE_SIZE_256	 0x00000000
+#define  FLASH_5752PAGE_SIZE_512	 0x10000000
+#define  FLASH_5752PAGE_SIZE_1K		 0x20000000
+#define  FLASH_5752PAGE_SIZE_2K		 0x30000000
+#define  FLASH_5752PAGE_SIZE_4K		 0x40000000
+#define  FLASH_5752PAGE_SIZE_264	 0x50000000
 #define NVRAM_CFG2			0x00007018
 #define NVRAM_CFG3			0x0000701c
 #define NVRAM_SWARB			0x00007020

Michael Chan

2005-04-18 07:54 UTC #39 lore raw

PATCH 8/11 tg3: Add nvram lock-out support for 5752 TPM

In reply to Michael Chan

Add support for the NVRAM lock-out feature for TPM in 5752. If lock-out is enabled, certain NVRAM registers cannot be written to.

Signed-off-by Michael Chan <[email protected]>

drivers/net/tg3.c +36 ~~-34~~

diff -Nru 107/drivers/net/tg3.c 108/drivers/net/tg3.c
@@ -3732,6 +3732,28 @@
 }
 
 /* tp->lock is held. */
+static void tg3_enable_nvram_access(struct tg3 *tp)
+{
+	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+	    !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
+		u32 nvaccess = tr32(NVRAM_ACCESS);
+
+		tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
+	}
+}
+
+/* tp->lock is held. */
+static void tg3_disable_nvram_access(struct tg3 *tp)
+{
+	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+	    !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
+		u32 nvaccess = tr32(NVRAM_ACCESS);
+
+		tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
+	}
+}
+
+/* tp->lock is held. */
 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
 {
 	if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))

@@ -7102,6 +7124,10 @@
 
 	nvcfg1 = tr32(NVRAM_CFG1);
 
+	/* NVRAM protection for TPM */
+	if (nvcfg1 & (1 << 27))
+		tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
+
 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
 		case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
 		case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:

@@ -7179,11 +7205,7 @@
 	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
 		tp->tg3_flags |= TG3_FLAG_NVRAM;
 
-		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
-			u32 nvaccess = tr32(NVRAM_ACCESS);
-
-			tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
-		}
+		tg3_enable_nvram_access(tp);
 
 		if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
 			tg3_get_5752_nvram_info(tp);

@@ -7192,11 +7214,7 @@
 
 		tg3_get_nvram_size(tp);
 
-		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
-			u32 nvaccess = tr32(NVRAM_ACCESS);
-
-			tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
-		}
+		tg3_disable_nvram_access(tp);
 
 	} else {
 		tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);

@@ -7285,11 +7303,7 @@
 
 	tg3_nvram_lock(tp);
 
-	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
-		u32 nvaccess = tr32(NVRAM_ACCESS);
-
-		tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
-	}
+	tg3_enable_nvram_access(tp);
 
 	tw32(NVRAM_ADDR, offset);
 	ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |

@@ -7300,11 +7314,7 @@
 
 	tg3_nvram_unlock(tp);
 
-	if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
-		u32 nvaccess = tr32(NVRAM_ACCESS);
-
-		tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
-	}
+	tg3_disable_nvram_access(tp);
 
 	return ret;
 }

@@ -7367,7 +7377,7 @@
 
 	while (len) {
 		int j;
-		u32 phy_addr, page_off, size, nvaccess;
+		u32 phy_addr, page_off, size;
 
 		phy_addr = offset & ~pagemask;

@@ -7390,8 +7400,7 @@
 
 		offset = offset + (pagesize - page_off);
 
-		nvaccess = tr32(NVRAM_ACCESS);
-		tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
+		tg3_enable_nvram_access(tp);
 
 		/*
 		 * Before we can erase the flash page, we need

@@ -7528,13 +7537,10 @@
 
 		tg3_nvram_lock(tp);
 
-		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
-			u32 nvaccess = tr32(NVRAM_ACCESS);
-
-			tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
-
+		tg3_enable_nvram_access(tp);
+		if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+		    !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
 			tw32(NVRAM_WRITE1, 0x406);
-		}
 
 		grc_mode = tr32(GRC_MODE);
 		tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);

@@ -7553,11 +7559,7 @@
 		grc_mode = tr32(GRC_MODE);
 		tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
 
-		if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
-			u32 nvaccess = tr32(NVRAM_ACCESS);
-
-			tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
-		}
+		tg3_disable_nvram_access(tp);
 		tg3_nvram_unlock(tp);
 	}

drivers/net/tg3.h +1 -0

diff -Nru 107/drivers/net/tg3.h 108/drivers/net/tg3.h
@@ -2122,6 +2122,7 @@
 #define TG3_FLG2_SERDES_PREEMPHASIS	0x00020000
 #define TG3_FLG2_5705_PLUS		0x00040000
 #define TG3_FLG2_5750_PLUS		0x00080000
+#define TG3_FLG2_PROTECTED_NVRAM	0x00100000
 
 	u32				split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ		3

Michael Chan

2005-04-18 07:57 UTC #40 lore raw

PATCH 9/11 tg3: Fix bug in tg3_set_eeprom()

In reply to Michael Chan

Fix a bug in tg3_set_eeprom() when the length is less than 4 and the offset is not 4-byte aligned.

Signed-off-by Michael Chan <[email protected]>

drivers/net/tg3.c +3 -1

diff -Nru 108/drivers/net/tg3.c 109/drivers/net/tg3.c
@@ -6560,10 +6560,12 @@
 		start = cpu_to_le32(start);
 		len += b_offset;
 		offset &= ~3;
+		if (len < 4)
+			len = 4;
 	}
 
 	odd_len = 0;
-	if ((len & 3) && ((len > 4) || (b_offset == 0))) {
+	if (len & 3) {
 		/* adjustments to end on required 4 byte boundary */
 		odd_len = 1;
 		len = (len + 3) & ~3;

Michael Chan

2005-04-18 07:59 UTC #41 lore raw

PATCH 10/11 tg3: Add msi support

In reply to Michael Chan

Add MSI support for 5751 C0 and 5752.

Signed-off-by Michael Chan <[email protected]>

drivers/net/tg3.c +71 -5

diff -Nru 109/drivers/net/tg3.c 110/drivers/net/tg3.c
@@ -2907,6 +2907,43 @@
 	return work_exists;
 }
 
+/* MSI ISR - No need to check for interrupt sharing and no need to
+ * flush status block and interrupt mailbox. PCI ordering rules
+ * guarantee that MSI will arrive after the status block.
+ */
+static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
+{
+	struct net_device *dev = dev_id;
+	struct tg3 *tp = netdev_priv(dev);
+	struct tg3_hw_status *sblk = tp->hw_status;
+	unsigned long flags;
+
+	spin_lock_irqsave(&tp->lock, flags);
+
+	/*
+	 * writing any value to intr-mbox-0 clears PCI INTA# and
+	 * chip-internal interrupt pending events.
+	 * writing non-zero to intr-mbox-0 additional tells the
+	 * NIC to stop sending us irqs, engaging "in-intr-handler"
+	 * event coalescing.
+	 */
+	tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
+	sblk->status &= ~SD_STATUS_UPDATED;
+
+	if (likely(tg3_has_work(dev, tp)))
+		netif_rx_schedule(dev);		/* schedule NAPI poll */
+	else {
+		/* no work, re-enable interrupts
+		 */
+		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
+			     0x00000000);
+	}
+
+	spin_unlock_irqrestore(&tp->lock, flags);
+
+	return IRQ_RETVAL(1);
+}
+
 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
 	struct net_device *dev = dev_id;

@@ -2965,7 +3002,9 @@
 #ifdef CONFIG_NET_POLL_CONTROLLER
 static void tg3_poll_controller(struct net_device *dev)
 {
-	tg3_interrupt(dev->irq, dev, NULL);
+	struct tg3 *tp = netdev_priv(dev);
+
+	tg3_interrupt(tp->pdev->irq, dev, NULL);
 }
 #endif

@@ -5778,10 +5817,29 @@
 	if (err)
 		return err;
 
-	err = request_irq(dev->irq, tg3_interrupt,
-			  SA_SHIRQ, dev->name, dev);
+	if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
+	    (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
+	    (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
+		if (pci_enable_msi(tp->pdev) == 0) {
+			u32 msi_mode;
+
+			msi_mode = tr32(MSGINT_MODE);
+			tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
+			tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
+		}
+	}
+	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
+		err = request_irq(tp->pdev->irq, tg3_msi,
+				  0, dev->name, dev);
+	else
+		err = request_irq(tp->pdev->irq, tg3_interrupt,
+				  SA_SHIRQ, dev->name, dev);
 
 	if (err) {
+		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+			pci_disable_msi(tp->pdev);
+			tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+		}
 		tg3_free_consistent(tp);
 		return err;
 	}

@@ -5811,7 +5869,11 @@
 	spin_unlock_irq(&tp->lock);
 
 	if (err) {
-		free_irq(dev->irq, dev);
+		free_irq(tp->pdev->irq, dev);
+		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+			pci_disable_msi(tp->pdev);
+			tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+		}
 		tg3_free_consistent(tp);
 		return err;
 	}

@@ -6086,7 +6148,11 @@
 	spin_unlock(&tp->tx_lock);
 	spin_unlock_irq(&tp->lock);
 
-	free_irq(dev->irq, dev);
+	free_irq(tp->pdev->irq, dev);
+	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+		pci_disable_msi(tp->pdev);
+		tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+	}
 
 	memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
 	       sizeof(tp->net_stats_prev));

drivers/net/tg3.h +1 -0

diff -Nru 109/drivers/net/tg3.h 110/drivers/net/tg3.h
@@ -2123,6 +2123,7 @@
 #define TG3_FLG2_5705_PLUS		0x00040000
 #define TG3_FLG2_5750_PLUS		0x00080000
 #define TG3_FLG2_PROTECTED_NVRAM	0x00100000
+#define TG3_FLG2_USING_MSI		0x00200000
 
 	u32				split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ		3

Michael Chan

2005-04-18 08:02 UTC #42 lore raw

PATCH 11/11 tg3: Add msi test

In reply to Michael Chan

Add MSI test for chips that support MSI. If MSI test fails, it will switch back to INTx mode and will print a message asking the user to report the failure.

Signed-off-by Michael Chan <[email protected]>

drivers/net/tg3.c +151 -3

diff -Nru 110/drivers/net/tg3.c 111/drivers/net/tg3.c
@@ -2996,6 +2996,22 @@
 	return IRQ_RETVAL(handled);
 }
 
+/* ISR for interrupt test */
+static irqreturn_t tg3_test_isr(int irq, void *dev_id,
+		struct pt_regs *regs)
+{
+	struct net_device *dev = dev_id;
+	struct tg3 *tp = netdev_priv(dev);
+	struct tg3_hw_status *sblk = tp->hw_status;
+
+	if (sblk->status & SD_STATUS_UPDATED) {
+		tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
+			     0x00000001);
+		return IRQ_RETVAL(1);
+	}
+	return IRQ_RETVAL(0);
+}
+
 static int tg3_init_hw(struct tg3 *);
 static int tg3_halt(struct tg3 *);

@@ -5796,6 +5812,118 @@
 	add_timer(&tp->timer);
 }
 
+static int tg3_test_interrupt(struct tg3 *tp)
+{
+	struct net_device *dev = tp->dev;
+	int err, i;
+	u32 int_mbox = 0;
+
+	tg3_disable_ints(tp);
+
+	free_irq(tp->pdev->irq, dev);
+
+	err = request_irq(tp->pdev->irq, tg3_test_isr,
+			  SA_SHIRQ, dev->name, dev);
+	if (err)
+		return err;
+
+	tg3_enable_ints(tp);
+
+	tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
+	       HOSTCC_MODE_NOW);
+
+	for (i = 0; i < 5; i++) {
+		int_mbox = tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
+		if (int_mbox != 0)
+			break;
+		msleep(10);
+	}
+
+	tg3_disable_ints(tp);
+
+	free_irq(tp->pdev->irq, dev);
+	
+	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
+		err = request_irq(tp->pdev->irq, tg3_msi,
+				  0, dev->name, dev);
+	else
+		err = request_irq(tp->pdev->irq, tg3_interrupt,
+				  SA_SHIRQ, dev->name, dev);
+
+	if (err)
+		return err;
+
+	if (int_mbox != 0)
+		return 0;
+
+	return -EIO;
+}
+
+/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
+ * successfully restored
+ */
+static int tg3_test_msi(struct tg3 *tp)
+{
+	struct net_device *dev = tp->dev;
+	int err;
+	u16 pci_cmd;
+
+	if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
+		return 0;
+
+	/* Turn off SERR reporting in case MSI terminates with Master
+	 * Abort.
+	 */
+	pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
+	pci_write_config_word(tp->pdev, PCI_COMMAND,
+			      pci_cmd & ~PCI_COMMAND_SERR);
+
+	err = tg3_test_interrupt(tp);
+
+	pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
+
+	if (!err)
+		return 0;
+
+	/* other failures */
+	if (err != -EIO)
+		return err;
+
+	/* MSI test failed, go back to INTx mode */
+	printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
+	       "switching to INTx mode. Please report this failure to "
+	       "the PCI maintainer and include system chipset information.\n",
+		       tp->dev->name);
+
+	free_irq(tp->pdev->irq, dev);
+	pci_disable_msi(tp->pdev);
+
+	tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+
+	err = request_irq(tp->pdev->irq, tg3_interrupt,
+			  SA_SHIRQ, dev->name, dev);
+
+	if (err)
+		return err;
+
+	/* Need to reset the chip because the MSI cycle may have terminated
+	 * with Master Abort.
+	 */
+	spin_lock_irq(&tp->lock);
+	spin_lock(&tp->tx_lock);
+
+	tg3_halt(tp);
+	err = tg3_init_hw(tp);
+
+	spin_unlock(&tp->tx_lock);
+	spin_unlock_irq(&tp->lock);
+
+	if (err)
+		free_irq(tp->pdev->irq, dev);
+
+	return err;
+}
+
 static int tg3_open(struct net_device *dev)
 {
 	struct tg3 *tp = netdev_priv(dev);

@@ -5860,9 +5988,6 @@
 		tp->timer.expires = jiffies + tp->timer_offset;
 		tp->timer.data = (unsigned long) tp;
 		tp->timer.function = tg3_timer;
-		add_timer(&tp->timer);
-
-		tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
 	}
 
 	spin_unlock(&tp->tx_lock);

@@ -5878,9 +6003,32 @@
 		return err;
 	}
 
+	if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+		err = tg3_test_msi(tp);
+		if (err) {
+			spin_lock_irq(&tp->lock);
+			spin_lock(&tp->tx_lock);
+
+			if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
+				pci_disable_msi(tp->pdev);
+				tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
+			}
+			tg3_halt(tp);
+			tg3_free_rings(tp);
+			tg3_free_consistent(tp);
+
+			spin_unlock(&tp->tx_lock);
+			spin_unlock_irq(&tp->lock);
+
+			return err;
+		}
+	}
+
 	spin_lock_irq(&tp->lock);
 	spin_lock(&tp->tx_lock);
 
+	add_timer(&tp->timer);
+	tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
 	tg3_enable_ints(tp);
 
 	spin_unlock(&tp->tx_lock);

David S. Miller

maintainer Applied

2005-04-21 23:57 UTC #31 lore raw

Re: [patch 2.6.12-rc2 1/10] tg3: add basic bcm5752 support

In reply to John W. Linville

Quoted 4 lines · On Wed, 13 Apr 2005 19:38:43 -0400 "John W. Linville" <[email protected]>…

Track-down all references to ASIC_REV_5750 and mirror them with references to the newly defined ASIC_REV_5752.
Signed-off-by John W. Linville <[email protected]>

You don't actually add the ASIC_REV_5752 definition to tg3.h, but I took care of that for you when checking this patch in.

Applied, thanks.

David S. Miller

maintainer Applied

2005-04-21 23:58 UTC #30 lore raw

Re: [patch 2.6.12-rc2 2/10] tg3: add bcm5752 to tg3_pci_tbl

In reply to John W. Linville

Quoted 5 lines · On Wed, 13 Apr 2005 19:38:44 -0400 "John W. Linville" <[email protected]>…

Add hard-coded definition of bcm5752 PCI ID to tg3_pci_tbl.
Signed-off-by John W. Linville <[email protected]>
---
Next patch will change entry to use pci_ids.h-based definition.

Applied, thanks.

David S. Miller

maintainer Applied

2005-04-21 23:59 UTC #18 lore raw

Re: [patch 2.6.12-rc2 3/10] tg3: add bcm5752 entry to pci_ids.h

In reply to John W. Linville

Quoted 6 lines · On Wed, 13 Apr 2005 19:38:44 -0400 "John W. Linville" <[email protected]>…

Add proper entry for bcm5752 PCI ID to pci_ids.h, and use it in tg3.
Signed-off-by John W. Linville <[email protected]>
---
I did this separately in case patches like this (i.e. new PCI IDs) need to come from more "official" sources.

Applied, thanks. Don't we need a drivers/pci/pci.ids update as well?

David S. Miller

maintainer Applied

2005-04-22 00:00 UTC #17 lore raw

Re: [patch 2.6.12-rc2 4/10] tg3: use TG3_FLG2_5705_PLUS instead of multi-way if's

In reply to John W. Linville

Quoted 4 lines · On Wed, 13 Apr 2005 19:38:44 -0400 "John W. Linville" <[email protected]>…

Replace a number of three-way if statements checking for 5705, 5750, and 5752 to reference the equivalent TG3_FLG2_5705_PLUS flag instead.
Signed-off-by John W. Linville <[email protected]>

Applied.

David S. Miller

maintainer Applied

2005-04-22 00:01 UTC #16 lore raw

Re: [patch 2.6.12-rc2 5/10] tg3: define TG3_FLG2_5750_PLUS flag

In reply to John W. Linville

Quoted 4 lines · On Wed, 13 Apr 2005 19:38:45 -0400 "John W. Linville" <[email protected]>…

Define TG3_FLG2_5750_PLUS flag and set it in tg3_get_invariants for ASIC_REV_5750 or ASIC_REV_5752.
Signed-off-by John W. Linville <[email protected]>

Applied, thanks.

David S. Miller

maintainer Applied

2005-04-22 00:02 UTC #15 lore raw

Re: [patch 2.6.12-rc2 6/10] tg3: use new TG3_FLG2_5750_PLUS flag

In reply to John W. Linville

Quoted 4 lines · On Wed, 13 Apr 2005 19:38:45 -0400 "John W. Linville" <[email protected]>…

Replace a number of two-way if statements checking for 5750, and/or 5752 to reference the newly-defined TG3_FLG2_5750_PLUS flag instead.
Signed-off-by John W. Linville <[email protected]>

Applied.

David S. Miller

maintainer Applied

2005-04-22 00:02 UTC #14 lore raw

Re: [patch 2.6.12-rc2 7/10] tg3: more use of TG3_FLG2_5705_PLUS flag

In reply to John W. Linville

Quoted 4 lines · On Wed, 13 Apr 2005 19:38:45 -0400 "John W. Linville" <[email protected]>…

Rewrite of a couple of troublesome multi-way if statements to use TG3_FLG2_5705_PLUS flag.
Signed-off-by John W. Linville <[email protected]>

Applied.

David S. Miller

maintainer Applied

2005-04-22 00:03 UTC #13 lore raw

Re: [patch 2.6.12-rc2 8/10] tg3: use TG3_FLG2_57{05,50}_PLUS flags in tg3_get_invariants

In reply to John W. Linville

Quoted 4 lines · On Wed, 13 Apr 2005 19:38:45 -0400 "John W. Linville" <[email protected]>…

Rewrite checks in tg3_get_invariants to use TG3_FLG2_5705_PLUS and TG3_FLG2_5750_PLUS flags.
Signed-off-by John W. Linville <[email protected]>

Applied.

David S. Miller

maintainer Applied

2005-04-22 00:04 UTC #12 lore raw

Re: [patch 2.6.12-rc2 9/10] tg3: check TG3_FLG2_5750_PLUS flag to set TG3_FLG2_5705_PLUS flag

In reply to John W. Linville

Quoted 4 lines · On Wed, 13 Apr 2005 19:38:46 -0400 "John W. Linville" <[email protected]>…

Use check of TG3_FLG2_5750_PLUS in tg3_get_invariants to set TG3_FLG2_5705_PLUS flag.
Signed-off-by John W. Linville <[email protected]>

Applied.

David S. Miller

maintainer Applied

2005-04-22 00:04 UTC #11 lore raw

Re: [patch 2.6.12-rc2 10/10] tg3: add support for bcm5752 rev a1

In reply to John W. Linville

Quoted 5 lines · On Wed, 13 Apr 2005 19:38:46 -0400 "John W. Linville" <[email protected]>…

Replace existing ASIC_REV_5752 definition with ASIC_REV_5752_A0, and add definition for ASIC_REV_5752_A1. Then, add ASIC_REV_5752_A1 to check for setting TG3_FLG2_5750_PLUS in tg3_get_invariants.
Signed-off-by John W. Linville <[email protected]>

Applied, now off to Michael's additions :-)

David S. Miller

maintainer

2005-04-22 00:15 UTC #44 lore raw

Re: [PATCH 2.6.12-rc2 0/11] tg3: Add complete support for 5752

In reply to Michael Chan

Quoted 8 lines · On Sun, 17 Apr 2005 23:42:31 -0700 "Michael Chan" <[email protected]> wrote:

These patches should be applied on top of John Linville's patches posted a few days ago.
The last 2 patches are MSI patches for 5751 C0 and 5752. They are very similar to the MSI patches posted a few weeks ago. I've modified the MSI test patch to display a warning message to ask the user to report the failure if the MSI test fails. If Jeff still objects to this, then just skip patch 11 but apply patch 10 which enables MSI on the latest chips.

I decided to apply everything, even the MSI test stuff, it seems perfectly reasonable to me.

I'll work on backporting all of this 5752 stuff to 2.4.x later today.

Michael Chan

2005-05-27 18:12 UTC #22 lore raw

Re: [patch 2.6.12-rc5] tg3: add bcm5752 entry to pci.ids

In reply to John W. Linville

Quoted 21 lines · John W. Linville

Quoted 6 lines · Christoph Hellwig
drivers/pci/pci.ids line 7176
Quoted 1 line · John W. Linville
drivers/pci/pci.ids renamed from drivers/pci/pci.ids.orig +1 -0
+	1600  NetXtreme BCM5752 Gigabit Ethernet PCI Express
I don't think you should mention "PCI Express" here. That can trivially befound it looking at the configuration header.
I'm just following what is at pciids.sourceforge.net. Plus, it is already like that for nine other IDs:
        1659  NetXtreme BCM5721 Gigabit Ethernet PCI Express
        1677  NetXtreme BCM5751 Gigabit Ethernet PCI Express
        167d  NetXtreme BCM5751M Gigabit Ethernet PCI Express
        167e  NetXtreme BCM5751F Fast Ethernet PCI Express
        169d  NetLink BCM5789 Gigabit Ethernet PCI Express
        16dd  NetLink BCM5781 Gigabit Ethernet PCI Express
        16f7  NetXtreme BCM5753 Gigabit Ethernet PCI Express
        16fd  NetXtreme BCM5753M Gigabit Ethernet PCI Express
        16fe  NetXtreme BCM5753F Fast Ethernet PCI Express

Quoted 3 lines

The Broadcom guys can speak-up, but I figure they know if "PCI Express" is appropriate for their device... :-)

Yes, "PCI Express" is appropriate. Thanks John.

John W. Linville

author

2005-05-27 18:47 UTC #19 lore raw

PATCH 1/1 tg3: add bcm5752 entry to pci.ids

In reply to David S. Miller

Update pci.ids for BCM5752

Signed-off-by John W. Linville <[email protected]>

---

 drivers/pci/pci.ids |    1 +
 1 files changed, 1 insertion(+)

drivers/pci/pci.ids renamed from drivers/pci/pci.ids.orig +1 -0

@@ -7173,6 +7173,7 @@
 	080f  Sentry5 DDR/SDR RAM Controller
 	0811  Sentry5 External Interface Core
 	0816  BCM3302 Sentry5 MIPS32 CPU
+	1600  NetXtreme BCM5752 Gigabit Ethernet PCI Express
 	1644  NetXtreme BCM5700 Gigabit Ethernet
 		1014 0277  Broadcom Vigil B5700 1000Base-T
 		1028 00d1  Broadcom BCM5700

Signature · 2 lines

John W. Linville
[email protected]

Christoph Hellwig

2005-05-27 18:53 UTC #20 lore raw

Re: [patch 2.6.12-rc5] tg3: add bcm5752 entry to pci.ids

Quoted 11 lines · John W. Linville

Update pci.ids for BCM5752
Signed-off-by John W. Linville <[email protected]>
---
 drivers/pci/pci.ids |    1 +
 1 files changed, 1 insertion(+)

drivers/pci/pci.ids line 7176

Quoted 4 lines

drivers/pci/pci.ids renamed from drivers/pci/pci.ids.orig +1 -0

@@ -7173,6 +7173,7 @@
 	080f  Sentry5 DDR/SDR RAM Controller
 	0811  Sentry5 External Interface Core
 	0816  BCM3302 Sentry5 MIPS32 CPU
+	1600  NetXtreme BCM5752 Gigabit Ethernet PCI Express

I don't think you should mention "PCI Express" here. That can trivially befound it looking at the configuration header.

John W. Linville

author

2005-05-27 19:00 UTC #21 lore raw

Re: [patch 2.6.12-rc5] tg3: add bcm5752 entry to pci.ids

Quoted 6 lines · Christoph Hellwig

drivers/pci/pci.ids line 7176
Quoted 1 line · John W. Linville
drivers/pci/pci.ids renamed from drivers/pci/pci.ids.orig +1 -0
+	1600  NetXtreme BCM5752 Gigabit Ethernet PCI Express
I don't think you should mention "PCI Express" here. That can trivially befound it looking at the configuration header.

I'm just following what is at pciids.sourceforge.net. Plus, it is already like that for nine other IDs:

        1659  NetXtreme BCM5721 Gigabit Ethernet PCI Express
        1677  NetXtreme BCM5751 Gigabit Ethernet PCI Express
        167d  NetXtreme BCM5751M Gigabit Ethernet PCI Express
        167e  NetXtreme BCM5751F Fast Ethernet PCI Express
        169d  NetLink BCM5789 Gigabit Ethernet PCI Express
        16dd  NetLink BCM5781 Gigabit Ethernet PCI Express
        16f7  NetXtreme BCM5753 Gigabit Ethernet PCI Express
        16fd  NetXtreme BCM5753M Gigabit Ethernet PCI Express
        16fe  NetXtreme BCM5753F Fast Ethernet PCI Express

The Broadcom guys can speak-up, but I figure they know if "PCI Express" is appropriate for their device... :-)

John

Signature · 2 lines

John W. Linville
[email protected]

Christoph Hellwig

2005-05-27 19:02 UTC #23 lore raw

Re: [patch 2.6.12-rc5] tg3: add bcm5752 entry to pci.ids

Quoted 21 lines · John W. Linville

Quoted 6 lines · Christoph Hellwig
drivers/pci/pci.ids line 7176
Quoted 1 line · John W. Linville
drivers/pci/pci.ids renamed from drivers/pci/pci.ids.orig +1 -0
+	1600  NetXtreme BCM5752 Gigabit Ethernet PCI Express
I don't think you should mention "PCI Express" here. That can trivially befound it looking at the configuration header.
I'm just following what is at pciids.sourceforge.net. Plus, it is already like that for nine other IDs:
        1659  NetXtreme BCM5721 Gigabit Ethernet PCI Express
        1677  NetXtreme BCM5751 Gigabit Ethernet PCI Express
        167d  NetXtreme BCM5751M Gigabit Ethernet PCI Express
        167e  NetXtreme BCM5751F Fast Ethernet PCI Express
        169d  NetLink BCM5789 Gigabit Ethernet PCI Express
        16dd  NetLink BCM5781 Gigabit Ethernet PCI Express
        16f7  NetXtreme BCM5753 Gigabit Ethernet PCI Express
        16fd  NetXtreme BCM5753M Gigabit Ethernet PCI Express
        16fe  NetXtreme BCM5753F Fast Ethernet PCI Express

Quoted 2 lines

The Broadcom guys can speak-up, but I figure they know if "PCI Express" is appropriate for their device... :-)

ok, it should be an all or nothing. I still think it's more than silly..

Michael Chan

2005-05-27 19:24 UTC #25 lore raw

Re: [patch 2.6.12-rc5] tg3: add bcm5752 entry to pci.ids

In reply to David S. Miller

Quoted 5 lines · David S. Miller

I'll apply this, thanks John.
pci.ids needs several updates for tg3 in fact, and it also now needs entries for bnx2 as well.

The bnx2 IDs are already in, probably from sourceforge. And the tg3 IDs look reasonably complete to me.

So in the future, do we need to patch this file or just let sourceforge take care of it?

David S. Miller

maintainer

2005-05-27 19:30 UTC #24 lore raw

Re: [patch 2.6.12-rc5] tg3: add bcm5752 entry to pci.ids

In reply to John W. Linville

From: "John W. Linville" <[email protected]>
Date: Fri, 27 May 2005 14:47:52 -0400

Quoted 3 lines

Update pci.ids for BCM5752
Signed-off-by John W. Linville <[email protected]>

I'll apply this, thanks John.

pci.ids needs several updates for tg3 in fact, and it also now needs entries for bnx2 as well.

Jeff Garzik

2005-05-27 20:40 UTC #26 lore raw

Re: [patch 2.6.12-rc5] tg3: add bcm5752 entry to pci.ids

In reply to Michael Chan

Quoted 10 lines · Michael Chan

Quoted 5 lines · David S. Miller
I'll apply this, thanks John.
pci.ids needs several updates for tg3 in fact, and it also now needs entries for bnx2 as well.

Quoted 5 lines

The bnx2 IDs are already in, probably from sourceforge. And the tg3 IDs look reasonably complete to me.
So in the future, do we need to patch this file or just let sourceforge take care of it?

Honestly, pci.ids is such a non-critical file, unless DaveM disagrees I would strongly encourage people to -only- send pci.ids updates to sourceforge.

pci.ids is only used in one location -- deprecated /proc/pci -- and will be removed in the next year or so, I imagine. Further, pci.ids is periodically sync'd en masse from sourceforge into the kernel by janitors.

Users should be using 'lspci' not /proc/pci, and lspci takes it data from sourceforge database not the kernel.

Jeff

David S. Miller

maintainer

2005-05-27 20:40 UTC #28 lore raw

Re: [patch 2.6.12-rc5] tg3: add bcm5752 entry to pci.ids

In reply to Michael Chan

From: "Michael Chan" <[email protected]>
Date: Fri, 27 May 2005 12:24:19 -0700

Quoted 2 lines

So in the future, do we need to patch this file or just let sourceforge take care of it?

I think the proper procedure is to send it to sourceforge. But there is some latency in the changes making it back into the kernel.

Either way, if it is submitted to the kernel or sourceforge (or even both), it ends up getting merged together in the end.

David S. Miller

maintainer

2005-05-27 20:41 UTC #27 lore raw

Re: [patch 2.6.12-rc5] tg3: add bcm5752 entry to pci.ids

In reply to Jeff Garzik

From: Jeff Garzik <[email protected]>
Date: Fri, 27 May 2005 16:40:21 -0400

Quoted 3 lines

pci.ids is only used in one location -- deprecated /proc/pci -- and will be removed in the next year or so, I imagine. Further, pci.ids is periodically sync'd en masse from sourceforge into the kernel by janitors.

Good point.

Dave Jones

2005-05-27 22:46 UTC #29 lore raw

Re: [patch 2.6.12-rc5] tg3: add bcm5752 entry to pci.ids

In reply to David S. Miller

Quoted 9 lines · David S. Miller

From: "Michael Chan" <[email protected]>
Date: Fri, 27 May 2005 12:24:19 -0700
Quoted 2 lines
So in the future, do we need to patch this file or just let sourceforge take care of it?
I think the proper procedure is to send it to sourceforge. But there is some latency in the changes making it back into the kernel.

The latest diff vs mainline is always available at http://www.codemonkey.org.uk/projects/pci/
(Comedy aside, I dont even remember which box is running the cronjob that
generates those files any more, good that its still ticking :-)

Greg did a sync up a while ago, but didn't seem too enthusiastic about doing it regularly, due to the fact that /proc/pci is aparently going away.

Dave