main clock calculation invalid

U-Boot-Users Junior 3 participants 8 messages Apr 19, 2007 – Apr 20, 2007 1 message not in the archive

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Junior

author

2007-04-19 15:42 UTC #0 lore raw

Hi all,
I'm trying to figure out why the below calculation of my main frequencey clock is not correct.

In the below equation:
maindiv2 = 28
maindiv1 = 13
prediv = 23
ps = 0
and CONFIG_SYS_CLK_FREQ is 14745600.

but I get 93622108 instead of 265420800. How is this possible?

here is the equation which is what get_FCLK returns:

   return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) / 
             ((prediv + 2) * (1 << ps)));

much thanks.
--Jr.

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Wolfgang Denk

2007-04-19 15:54 UTC #1 lore raw

Quoted 9 lines · In message <[email protected]> you wrote:

I'm trying to figure out why the below calculation of my main frequencey clock is not correct.
In the below equation:
maindiv2 = 28
maindiv1 = 13
prediv = 23
ps = 0
and CONFIG_SYS_CLK_FREQ is 14745600.

I'm sorry, but the user's manual for my Z80 processor does not contain any part which matches your description.

What might be missing?

Best regards,

Wolfgang Denk

Signature · 4 lines

DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk
Office:  Kirchenstr. 5,       D-82194 Groebenzell,            Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Memories of you remind me of you.                   - Karl Lehenbauer

Junior

author

2007-04-19 16:16 UTC #2 lore raw

Quoted 18 lines

-----Original Message-----
From: wd at denx.de
Sent: Thu, 19 Apr 2007 17:54:59 +0200
To: ejr at inbox.com
Subject: Re: [U-Boot-Users] main clock calculation invalid
Quoted 10 lines · In message <[email protected]> you wrote:
I'm trying to figure out why the below calculation of my main frequencey clock is not correct.
In the below equation:
maindiv2 = 28
maindiv1 = 13
prediv = 23
ps = 0
and CONFIG_SYS_CLK_FREQ is 14745600.

Quoted 4 lines

I'm sorry, but the user's manual for my Z80 processor does not contain any part which matches your description.
What might be missing?

I'm not sure what you're missing but my emphasis was on the calculation. This is on an ARM9 LH7A404 chip. Now I might be missing something but even on a 16 bit CPU the calculation result shouldn't change, no?

This is the function, all my printed values are correct before the calculation.

/* return FCLK frequency */
ulong get_FCLK (void)

{
    lh7a40x_csc_t* csc = LH7A404_CSC_PTR;
    ulong maindiv1, maindiv2, prediv, ps;

    /*
     * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
     *                   ((PREDIV+2) * (2^PS))
     */
    maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
    maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
    prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
    ps = (csc->clkset & CLKSET_PS) >> 16;
    printf("maindiv2: %d, maindiv1 %d, prediv %d, ps %d\n",maindiv2,maindiv1,prediv,ps);
    printf("CONFIG_SYS_CLK_FREQ: %d \n",CONFIG_SYS_CLK_FREQ);
    return ( ((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) / ((prediv + 2) * (1 << ps)));
}

Wolfgang Denk

2007-04-19 18:14 UTC #3 lore raw

Quoted 2 lines · In message <[email protected]> you wrote:

Quoted 2 lines
I'm sorry, but the user's manual for my Z80 processor does not contain

...

Quoted 3 lines

I'm not sure what you're missing but my emphasis was on the calculation. This is on an ARM9 LH7A404 chip. Now I might be missing something but even on a 16 bit CPU

You did not understand my little joke about the old Z80 CPU - what I wanted to pointout was that you completely left out all relevant information, like which architecture and CPU and board you were talking about.

Quoted 1 line

the calculation result shouldn't change, no?

You might have overflows here and there...

Quoted 1 line

and CONFIG_SYS_CLK_FREQ is 14745600.

It should probably be 14745600L or "UL".

Quoted 1 line

    ulong maindiv1, maindiv2, prediv, ps;

      ^^^^^

Quoted 1 line

    printf("maindiv2: %d, maindiv1 %d, prediv %d, ps %d\n",maindiv2,maindiv1,prediv,ps);

^^ ^^ ^^ ^^

%d is for int, not for ulong.

Quoted 1 line

    printf("CONFIG_SYS_CLK_FREQ: %d \n",CONFIG_SYS_CLK_FREQ);

Same here.

Quoted 2 lines

    return ( ((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /

((prediv + 2) * (1 << ps)));

Best regards,

Wolfgang Denk

Signature · 4 lines

DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk
Office:  Kirchenstr. 5,       D-82194 Groebenzell,            Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected]
What was sliced bread the greatest thing since?

Junior

author

2007-04-19 18:51 UTC #4 lore raw

In reply to Junior

Quoted 56 lines

-----Original Message-----
From: ejr at inbox.com
Sent: Thu, 19 Apr 2007 08:16:01 -0800
To: wd at denx.de
Subject: Re: [U-Boot-Users] main clock calculation invalid
Quoted 19 lines
-----Original Message-----
From: wd at denx.de
Sent: Thu, 19 Apr 2007 17:54:59 +0200
To: ejr at inbox.com
Subject: Re: [U-Boot-Users] main clock calculation invalid
Quoted 11 lines · In message <[email protected]> you wrote:
I'm trying to figure out why the below calculation of my main frequencey
clock is not correct.
In the below equation:
maindiv2 = 28
maindiv1 = 13
prediv = 23
ps = 0
and CONFIG_SYS_CLK_FREQ is 14745600.
Quoted 4 lines
I'm sorry, but the user's manual for my Z80 processor does not contain any part which matches your description.
What might be missing?
I'm not sure what you're missing but my emphasis was on the calculation. This is on an ARM9 LH7A404 chip. Now I might be missing something but even on a 16 bit CPU
the calculation result shouldn't change, no?
This is the function, all my printed values are correct before the calculation.
/* return FCLK frequency */
ulong get_FCLK (void)
{
    lh7a40x_csc_t* csc = LH7A404_CSC_PTR;
    ulong maindiv1, maindiv2, prediv, ps;

    /*
     * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
     *                   ((PREDIV+2) * (2^PS))
     */
    maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
    maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
    prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
    ps = (csc->clkset & CLKSET_PS) >> 16;
    printf("maindiv2: %d, maindiv1 %d, prediv %d, ps
%d\n",maindiv2,maindiv1,prediv,ps);
    printf("CONFIG_SYS_CLK_FREQ: %d \n",CONFIG_SYS_CLK_FREQ);
    return ( ((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /

Quoted 3 lines

((prediv + 2) * (1 << ps)));
}

I think I see what the problem is but I'm not sure how to fix it in uboot. When I multiply 450 and 14745600, I get a number greater than 32 bits and the MSB is missed.

I could do an alternative calculation to achive the correct result but unless there is a good trick out there I'll do that.

Thanks,
--Jr.

Martin Krause

2007-04-20 07:17 UTC #5 lore raw

Hi Junior,

u-boot-users-bounces at lists.sourceforge.net wrote on Thursday, April 19, 2007 8:52 PM:

Quoted 9 lines

Quoted 3 lines
    return ( ((maindiv2 + 2) * (maindiv1 + 2) *
CONFIG_SYS_CLK_FREQ) / ((prediv + 2) * (1 << ps))); }
I think I see what the problem is but I'm not sure how to fix it in uboot.
When I multiply 450 and 14745600, I get a number greater than 32 bits and the MSB is missed.

You could rearrange your formula:

CONFIG_SYS_CLK_FREQ / ((prediv + 2) * (1 << ps)) * (maindiv2 + 2) * (maindiv1 + 2)

The compiler should do the calculation from left to right.

Regards,
Martin

Wolfgang Denk

2007-04-20 08:18 UTC #6 lore raw

Quoted 7 lines · In message <[email protected]> you…

You could rearrange your formula:
CONFIG_SYS_CLK_FREQ / ((prediv + 2) * (1 << ps)) * (maindiv2 + 2) * (maindiv1 + 2)
The compiler should do the calculation from left to right.

And if in doubt, use parens to define the order of evaluation.

Best regards,

Wolfgang Denk

Signature · 6 lines

DENX Software Engineering GmbH, HRB 165235 Munich, CEO: Wolfgang Denk
Office:  Kirchenstr. 5,       D-82194 Groebenzell,            Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A man either lives life as it happens to him, meets  it  head-on  and
licks it, or he turns his back on it and starts to wither away.
	-- Dr. Boyce, "The Menagerie" ("The Cage"), stardate unknown

Martin Krause

2007-04-20 09:18 UTC #7 lore raw

wd at denx.de wrote on Friday, April 20, 2007 10:18 AM:

Quoted 4 lines

In message <[email protected]> you
Quoted 1 line · wrote:

Quoted 8 lines

Quoted 6 lines
You could rearrange your formula:
CONFIG_SYS_CLK_FREQ / ((prediv + 2) * (1 << ps)) * (maindiv2 + 2) * (maindiv1 + 2)
The compiler should do the calculation from left to right.
And if in doubt, use parens to define the order of evaluation.

Ahhh, I always had a strong feeling, that theses parenthesis things would be good for something ... ;-)

Ragards,
Martin