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Reading data from NAND FLASH without ECC is not recommended

DISCUSSION Polyakov Artem 2 participants 4 messages May 15, 2006 – May 17, 2006 Memory technology devices (MTD)

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#0 lore raw

Hi all! Sorry for my poor english.
I want to ask - why by default reading from NAND flash provided without ECC?
I work with Samsung K9F5608U0С 32M flash.
And one interest thing for me is that debug messages show that oob bytes for ECC are used by system. I mean, after eraseing - all bytes are 0xFF. But my debug messages shows this:

Quoted 1 line

write oob(00001890): 65 55 97 5a ffff 69 57 ff ff ff ff ff ff ff ff

bytes for ECC are not equal 0xFF!
but system dont use this bytes for ECC correction:

Quoted 1 line

Reading data from NAND FLASH without ECC is not recommended

#1 lore raw
Quoted 5 lines · Polyakov Artem

But my debug messages shows this:

Quoted 1 line

write oob(00001890): 65 55 97 5a ffff 69 57 ff ff ff ff ff ff ff ff

bytes for ECC are not equal 0xFF!
but system dont use this bytes for ECC correction:

Quoted 1 line

Reading data from NAND FLASH without ECC is not recommended

You're saying that the system _writes_ ECC data to the flash, but does not use ECC when reading from the flash?

Please show your NAND board driver, and also the code you used for reading from the flash.

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dwmw2
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#2 lore raw

Hello David,

Wednesday, May 17, 2006, 6:36:46 AM, you wrote:

Quoted 5 lines · Polyakov Artem
Quoted 5 lines

But my debug messages shows this:

Quoted 1 line

write oob(00001890): 65 55 97 5a ffff 69 57 ff ff ff ff ff ff ff ff

bytes for ECC are not equal 0xFF!
but system dont use this bytes for ECC correction:

Quoted 1 line

Reading data from NAND FLASH without ECC is not recommended

DW> You're saying that the system _writes_ ECC data to the flash, but does DW> not use ECC when reading from the flash?

DW> Please show your NAND board driver, and also the code you used for DW> reading from the flash.

Setup mtd device from NAND board driver:

        /* Set address of NAND IO lines */
        this->IO_ADDR_R = (void __iomem *)adm5120_fio_base;
        this->IO_ADDR_W = (void __iomem *)adm5120_fio_base;
        /* Set address of hardware control function */       
        this->hwcontrol = adm5120_hwcontrol;
        this->dev_ready = adm5120_device_ready;
       /* 20 us command delay time */
       this->chip_delay = 20;
       this->eccmode = NAND_ECC_SOFT;

and I attach nand_base driver from my kernel.

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Best regards,
 art                            mailto:[email protected]
#3 lore raw
Quoted 1 line · art

and I attach nand_base driver from my kernel.

Either this is the same as the one in the current kernel tree, or it's the one from 2.6.16, or I don't care at all. Which of the three?

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dwmw2