mpc83xx: Correct the burst length for DDR2 with 32 bits
PATCH 1/1 mpc83xx: Correct the burst length for DDR2 with 32 bits
The burst length should be 4 for DDR2 with 32 bits bus
Signed-off-by Dave Liu<[email protected]>
--- cpu/mpc83xx/spd_sdram.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-)
cpu/mpc83xx/spd_sdram.c +6 -2
@@ -730,8 +730,12 @@ long int spd_sdram() sdram_cfg |=0x10000000 ;/* The DIMM is 32bit width */ -if (spd.dataw_lsb ==0x20 ) - sdram_cfg |=0x000C0000 ; +if (spd.dataw_lsb ==0x20 ) { +if (spd.mem_type ==SPD_MEMTYPE_DDR ) + sdram_cfg |=0x000C0000 ; +if (spd.mem_type ==SPD_MEMTYPE_DDR2 ) + sdram_cfg |=0x00080000 ; + } ddrc_ecc_enable =0 ;
Signature · 1 line
1.5.3.rc2.29.gc4640f
PATCH 1/1 mpc83xx: Correct the burst length for DDR2 with 32 bits
Sorry for that, the patch only fix bottom half.
I will resend the new patch.
Thanks,
Dave
Quoted 26 lines · Dave Liu
The burst length should be 4 for DDR2 with 32 bits bus
Signed-off-by Dave Liu<[email protected]>--- cpu/mpc83xx/spd_sdram.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-)cpu/mpc83xx/spd_sdram.c +6
-2@@ -730,8 +730,12 @@ long int spd_sdram() sdram_cfg |=0x10000000 ;/* The DIMM is 32bit width */ -if (spd.dataw_lsb ==0x20 ) - sdram_cfg |=0x000C0000 ; +if (spd.dataw_lsb ==0x20 ) { +if (spd.mem_type ==SPD_MEMTYPE_DDR ) + sdram_cfg |=0x000C0000 ; +if (spd.mem_type ==SPD_MEMTYPE_DDR2 ) + sdram_cfg |=0x00080000 ; + } ddrc_ecc_enable =0 ;