musb_hdrc: Series of patches to clean-up musbhdrc.h

index 25941b5..db1fe8f 100644
@@ -366,7 +366,7 @@ cppi_dump_rx(int level, struct cppi_channel *c, const char *tag)
 		c->chNo, tag,
 		musb_readl(base - DAVINCI_BASE_OFFSET,
 			DAVINCI_RXCPPI_BUFCNT0_REG + 4 *c->chNo),
-		musb_readw(c->hw_ep->regs, MGC_O_HDRC_RXCSR),
+		musb_readw(c->hw_ep->regs, MUSB_RXCSR),
 
 		musb_readl(c->stateRam, 0 * 4),	/* buf offset */
 		musb_readl(c->stateRam, 1 * 4),	/* head ptr */

@@ -393,7 +393,7 @@ cppi_dump_tx(int level, struct cppi_channel *c, const char *tag)
 			"F%08x L%08x .. %08x"
 			"\n",
 		c->chNo, tag,
-		musb_readw(c->hw_ep->regs, MGC_O_HDRC_TXCSR),
+		musb_readw(c->hw_ep->regs, MUSB_TXCSR),
 
 		musb_readl(c->stateRam, 0 * 4),	/* head ptr */
 		musb_readl(c->stateRam, 1 * 4),	/* sop bd */

@@ -500,12 +500,12 @@ static inline int cppi_autoreq_update(struct cppi_channel *rx,
 	if (n_bds && rx->actualLen) {
 		void		*__iomem regs = rx->hw_ep->regs;
 
-		val = musb_readw(regs, MGC_O_HDRC_RXCSR);
+		val = musb_readw(regs, MUSB_RXCSR);
 		if (!(val & MGC_M_RXCSR_H_REQPKT)) {
 			val |= MGC_M_RXCSR_H_REQPKT | MGC_M_RXCSR_H_WZC_BITS;
-			musb_writew(regs, MGC_O_HDRC_RXCSR, val);
+			musb_writew(regs, MUSB_RXCSR, val);
 			/* flush writebufer */
-			val = musb_readw(regs, MGC_O_HDRC_RXCSR);
+			val = musb_readw(regs, MUSB_RXCSR);
 		}
 	}
 	return n_bds;

@@ -1095,7 +1095,7 @@ static int cppi_rx_scan(struct cppi *cppi, unsigned ch)
 			WARN_ON(rx->activeQueueHead);
 		}
 		musb_ep_select(cppi->pCoreBase, rx->chNo + 1);
-		csr = musb_readw(regs, MGC_O_HDRC_RXCSR);
+		csr = musb_readw(regs, MUSB_RXCSR);
 		if (csr & MGC_M_RXCSR_DMAENAB) {
 			DBG(4, "list%d %p/%p, last %08x%s, csr %04x\n",
 				rx->chNo,

@@ -1116,14 +1116,14 @@ static int cppi_rx_scan(struct cppi *cppi, unsigned ch)
 		/* REVISIT seems like "autoreq all but EOP" doesn't...
 		 * setting it here "should" be racey, but seems to work
 		 */
-		csr = musb_readw(rx->hw_ep->regs, MGC_O_HDRC_RXCSR);
+		csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
 		if (is_host_active(cppi->musb)
 				&& bd
 				&& !(csr & MGC_M_RXCSR_H_REQPKT)) {
 			csr |= MGC_M_RXCSR_H_REQPKT;
-			musb_writew(regs, MGC_O_HDRC_RXCSR,
+			musb_writew(regs, MUSB_RXCSR,
 					MGC_M_RXCSR_H_WZC_BITS | csr);
-			csr = musb_readw(rx->hw_ep->regs, MGC_O_HDRC_RXCSR);
+			csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
 		}
 	} else {
 		rx->activeQueueHead = NULL;

@@ -1246,7 +1246,7 @@ void cppi_completion(struct musb *musb, u32 rx, u32 tx)
 						int	csr;
 
 						csr = musb_readw(hw_ep->regs,
-							MGC_O_HDRC_TXCSR);
+							MUSB_TXCSR);
 						if (csr & MGC_M_TXCSR_TXPKTRDY)
 #endif
 							bReqComplete = 0;

@@ -1438,11 +1438,11 @@ static int cppi_channel_abort(struct dma_channel *channel)
 		 * an appropriate status code.
 		 */
 
-		regVal = musb_readw(regs, MGC_O_HDRC_TXCSR);
+		regVal = musb_readw(regs, MUSB_TXCSR);
 		regVal &= ~MGC_M_TXCSR_DMAENAB;
 		regVal |= MGC_M_TXCSR_FLUSHFIFO;
-		musb_writew(regs, MGC_O_HDRC_TXCSR, regVal);
-		musb_writew(regs, MGC_O_HDRC_TXCSR, regVal);
+		musb_writew(regs, MUSB_TXCSR, regVal);
+		musb_writew(regs, MUSB_TXCSR, regVal);
 
 		/* re-enable interrupt */
 		if (enabled)

@@ -1496,7 +1496,7 @@ static int cppi_channel_abort(struct dma_channel *channel)
 			musb_writel(regBase, DAVINCI_AUTOREQ_REG, regVal);
 		}
 
-		csr = musb_readw(regs, MGC_O_HDRC_RXCSR);
+		csr = musb_readw(regs, MUSB_RXCSR);
 
 		/* for host, clear (just) ReqPkt at end of current packet(s) */
 		if (is_host_active(otgCh->pController->musb)) {

@@ -1507,8 +1507,8 @@ static int cppi_channel_abort(struct dma_channel *channel)
 
 		/* clear dma enable */
 		csr &= ~(MGC_M_RXCSR_DMAENAB);
-		musb_writew(regs, MGC_O_HDRC_RXCSR, csr);
-		csr = musb_readw(regs, MGC_O_HDRC_RXCSR);
+		musb_writew(regs, MUSB_RXCSR, csr);
+		csr = musb_readw(regs, MUSB_RXCSR);
 
 		/* quiesce: wait for current dma to finish (if not cleanup)
 		 * we can't use bit zero of stateram->sopDescPtr since that

index 3324543..8b87424 100644
@@ -116,7 +116,7 @@ void musb_platform_disable(struct musb *musb)
 			  DAVINCI_USB_USBINT_MASK
 			| DAVINCI_USB_TXINT_MASK
 			| DAVINCI_USB_RXINT_MASK);
-	musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, 0);
+	musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
 	musb_writel(musb->ctrl_base, DAVINCI_USB_EOI_REG, 0);
 
 	if (is_dma_capable() && !dma_off)

@@ -207,7 +207,7 @@ static void otg_timer(unsigned long _musb)
 	/* We poll because DaVinci's won't expose several OTG-critical
 	* status change events (from the transceiver) otherwise.
 	 */
-	devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
+	devctl = musb_readb(mregs, MUSB_DEVCTL);
 	DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
 
 	spin_lock_irqsave(&musb->lock, flags);

@@ -241,9 +241,9 @@ static void otg_timer(unsigned long _musb)
 		 * NOTE setting the session flag is _supposed_ to trigger
 		 * SRP, but clearly it doesn't.
 		 */
-		musb_writeb(mregs, MGC_O_HDRC_DEVCTL,
+		musb_writeb(mregs, MUSB_DEVCTL,
 				devctl | MGC_M_DEVCTL_SESSION);
-		devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
+		devctl = musb_readb(mregs, MUSB_DEVCTL);
 		if (devctl & MGC_M_DEVCTL_BDEVICE)
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 		else

@@ -310,7 +310,7 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
 	if (tmp & (DAVINCI_INTR_DRVVBUS << DAVINCI_USB_USBINT_SHIFT)) {
 		int	drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
 		void	*__iomem mregs = musb->mregs;
-		u8	devctl = musb_readb(mregs, MGC_O_HDRC_DEVCTL);
+		u8	devctl = musb_readb(mregs, MUSB_DEVCTL);
 		int	err = musb->int_usb & MGC_M_INTR_VBUSERROR;
 
 		err = is_host_enabled(musb)

@@ -440,7 +440,7 @@ int musb_platform_exit(struct musb *musb)
 		 * long time to fall, especially on EVM with huge C133.
 		 */
 		do {
-			devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 			if (!(devctl & MGC_M_DEVCTL_VBUS))
 				break;
 			if ((devctl & MGC_M_DEVCTL_VBUS) != warn) {

193 lines not on this page · raw message

509 lines not on this page · raw message

565 lines not on this page · raw message

165 lines not on this page · raw message

index 79e8da2..d4e8c3e 100644
@@ -219,7 +219,7 @@ enum musb_g_ep0_state {
 /* TUSB mapping: "flat" plus ep0 special cases */
 #if	defined(CONFIG_USB_TUSB6010)
 #define musb_ep_select(_mbase, _epnum) \
-	musb_writeb((_mbase), MGC_O_HDRC_INDEX, (_epnum))
+	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
 #define	MGC_END_OFFSET			MGC_TUSB_OFFSET
 
 /* "flat" mapping: each endpoint has its own i/o address */

@@ -230,7 +230,7 @@ enum musb_g_ep0_state {
 /* "indexed" mapping: INDEX register controls register bank select */
 #else
 #define musb_ep_select(_mbase, _epnum) \
-	musb_writeb((_mbase), MGC_O_HDRC_INDEX, (_epnum))
+	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
 #define	MGC_END_OFFSET			MGC_INDEXED_OFFSET
 #endif
 

@@ -242,7 +242,7 @@ enum musb_g_ep0_state {
 	{ (_musb)->is_host=FALSE; }
 
 #define test_devctl_hst_mode(_x) \
-	(musb_readb((_x)->mregs, MGC_O_HDRC_DEVCTL)&MGC_M_DEVCTL_HM)
+	(musb_readb((_x)->mregs, MUSB_DEVCTL)&MGC_M_DEVCTL_HM)
 
 #define MUSB_MODE(musb) ((musb)->is_host ? "Host" : "Peripheral")
 

118 lines not on this page · raw message

index 1691984..a1365c0 100644
@@ -263,22 +263,22 @@ static int dma_channel_abort(struct dma_channel *pChannel)
 		if (pImplChannel->bTransmit) {
 
 			csr = musb_readw(mbase,
-				MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_TXCSR));
+				MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR));
 			csr &= ~(MGC_M_TXCSR_AUTOSET |
 				 MGC_M_TXCSR_DMAENAB |
 				 MGC_M_TXCSR_DMAMODE);
 			musb_writew(mbase,
-					MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_TXCSR),
+					MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
 					csr);
 		}
 		else {
 			csr = musb_readw(mbase,
-				MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_RXCSR));
+				MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR));
 			csr &= ~(MGC_M_RXCSR_AUTOCLEAR |
 				 MGC_M_RXCSR_DMAENAB |
 				 MGC_M_RXCSR_DMAMODE);
 			musb_writew(mbase,
-					MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_RXCSR),
+					MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR),
 					csr);
 		}
 

@@ -341,7 +341,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
 					"=> reconfig 0": "=> complete");
 
 				u8 devctl = musb_readb(mbase,
-						MGC_O_HDRC_DEVCTL);
+						MUSB_DEVCTL);
 
 				pChannel->status = MGC_DMA_STATUS_FREE;
 

@@ -356,7 +356,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
 					musb_ep_select(mbase,
 						pImplChannel->epnum);
 					musb_writew(mbase,
-						MGC_END_OFFSET(pImplChannel->epnum,MGC_O_HDRC_TXCSR),
+						MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
 						MGC_M_TXCSR_TXPKTRDY);
 				} else
 					musb_dma_completion(

index 65f2c22..e62bb76 100644
@@ -59,7 +59,7 @@ static void omap_set_vbus(struct musb *musb, int is_on)
 	 * that must be ignored.
 	 */
 
-	devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 
 	if (is_on) {
 		musb->is_active = 1;

@@ -81,12 +81,12 @@ static void omap_set_vbus(struct musb *musb, int is_on)
 
 		MUSB_DEV_MODE(musb);
 	}
-	musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, devctl);
+	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 
 	DBG(1, "VBUS %s, devctl %02x "
 		/* otg %3x conf %08x prcm %08x */ "\n",
 		otg_state_string(musb),
-		musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL));
+		musb_readb(musb->mregs, MUSB_DEVCTL));
 }
 static int omap_set_power(struct otg_transceiver *x, unsigned mA)
 {

268 lines not on this page · raw message

index d43b5cc..fff2553 100644
@@ -527,7 +527,7 @@ static void tusb_source_power(struct musb *musb, int is_on)
 
 	prcm = musb_readl(base, TUSB_PRCM_MNGMT);
 	conf = musb_readl(base, TUSB_DEV_CONF);
-	devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+	devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 
 	if (is_on) {
 		if (musb->set_clock)

@@ -562,11 +562,11 @@ static void tusb_source_power(struct musb *musb, int is_on)
 	musb_writel(base, TUSB_PRCM_MNGMT, prcm);
 	musb_writel(base, TUSB_DEV_OTG_TIMER, timer);
 	musb_writel(base, TUSB_DEV_CONF, conf);
-	musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, devctl);
+	musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 
 	DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
 		otg_state_string(musb),
-		musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL),
+		musb_readb(musb->mregs, MUSB_DEVCTL),
 		musb_readl(base, TUSB_DEV_OTG_STAT),
 		conf, prcm);
 }

@@ -707,9 +707,9 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *base)
 			case OTG_STATE_A_IDLE:
 				DBG(2, "Got SRP, turning on VBUS\n");
 				devctl = musb_readb(musb->mregs,
-							MGC_O_HDRC_DEVCTL);
+							MUSB_DEVCTL);
 				devctl |= MGC_M_DEVCTL_SESSION;
-				musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL,
+				musb_writeb(musb->mregs, MUSB_DEVCTL,
 							devctl);
 				musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
 

@@ -753,7 +753,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *base)
 			/* VBUS has probably been valid for a while now,
 			 * but may well have bounced out of range a bit
 			 */
-			devctl = musb_readb(musb->mregs, MGC_O_HDRC_DEVCTL);
+			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 			if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
 				if ((devctl & MGC_M_DEVCTL_VBUS)
 						!= MGC_M_DEVCTL_VBUS) {

index 9359028..4141c12 100644
@@ -223,10 +223,10 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
 		if (chdat->tx) {
 			DBG(2, "terminating short tx packet\n");
 			musb_ep_select(musb_base, chdat->epnum);
-			csr = musb_readw(hw_ep->regs, MGC_O_HDRC_TXCSR);
+			csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
 			csr |= MGC_M_TXCSR_MODE | MGC_M_TXCSR_TXPKTRDY
 				| MGC_M_TXCSR_P_WZC_BITS;
-			musb_writew(hw_ep->regs, MGC_O_HDRC_TXCSR, csr);
+			musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
 		}
 	}
 

@@ -376,17 +376,17 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
 	 */
 	if (chdat->tx) {
 		musb_ep_select(musb_base, chdat->epnum);
-		csr = musb_readw(hw_ep->regs, MGC_O_HDRC_TXCSR);
+		csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
 		csr |= (MGC_M_TXCSR_AUTOSET | MGC_M_TXCSR_DMAENAB
 			| MGC_M_TXCSR_DMAMODE | MGC_M_TXCSR_MODE);
 		csr &= ~MGC_M_TXCSR_P_UNDERRUN;
-		musb_writew(hw_ep->regs, MGC_O_HDRC_TXCSR, csr);
+		musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
 	} else {
 		musb_ep_select(musb_base, chdat->epnum);
-		csr = musb_readw(hw_ep->regs, MGC_O_HDRC_RXCSR);
+		csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
 		csr |= MGC_M_RXCSR_DMAENAB;
 		csr &= ~(MGC_M_RXCSR_AUTOCLEAR | MGC_M_RXCSR_DMAMODE);
-		musb_writew(hw_ep->regs, MGC_O_HDRC_RXCSR,
+		musb_writew(hw_ep->regs, MUSB_RXCSR,
 			csr | MGC_M_RXCSR_P_WZC_BITS);
 	}
 

index 5ad1614..41450c9 100644
@@ -59,18 +59,18 @@ static void musb_port_suspend(struct musb *musb, u8 bSuspend)
 	 * MGC_M_POWER_ENSUSPEND.  PHY may need a clock (sigh) to detect
 	 * SE0 changing to connect (J) or wakeup (K) states.
 	 */
-	power = musb_readb(mbase, MGC_O_HDRC_POWER);
+	power = musb_readb(mbase, MUSB_POWER);
 	if (bSuspend) {
 		int retries = 10000;
 
 		power &= ~MGC_M_POWER_RESUME;
 		power |= MGC_M_POWER_SUSPENDM;
-		musb_writeb(mbase, MGC_O_HDRC_POWER, power);
+		musb_writeb(mbase, MUSB_POWER, power);
 
 		/* Needed for OPT A tests */
-		power = musb_readb(mbase, MGC_O_HDRC_POWER);
+		power = musb_readb(mbase, MUSB_POWER);
 		while (power & MGC_M_POWER_SUSPENDM) {
-			power = musb_readb(mbase, MGC_O_HDRC_POWER);
+			power = musb_readb(mbase, MUSB_POWER);
 			if (retries-- < 1)
 				break;
 		}

@@ -97,7 +97,7 @@ static void musb_port_suspend(struct musb *musb, u8 bSuspend)
 	} else if (power & MGC_M_POWER_SUSPENDM) {
 		power &= ~MGC_M_POWER_SUSPENDM;
 		power |= MGC_M_POWER_RESUME;
-		musb_writeb(mbase, MGC_O_HDRC_POWER, power);
+		musb_writeb(mbase, MUSB_POWER, power);
 
 		DBG(3, "Root port resuming, power %02x\n", power);
 

@@ -114,7 +114,7 @@ static void musb_port_reset(struct musb *musb, u8 bReset)
 
 #ifdef CONFIG_USB_MUSB_OTG
 	/* REVISIT this looks wrong for HNP */
-	u8 devctl = musb_readb(mbase, MGC_O_HDRC_DEVCTL);
+	u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
 
 	if (musb->delay_port_power_off || !(devctl & MGC_M_DEVCTL_HM)) {
 		return;

@@ -127,7 +127,7 @@ static void musb_port_reset(struct musb *musb, u8 bReset)
 	/* NOTE:  caller guarantees it will turn off the reset when
 	 * the appropriate amount of time has passed
 	 */
-	power = musb_readb(mbase, MGC_O_HDRC_POWER);
+	power = musb_readb(mbase, MUSB_POWER);
 	if (bReset) {
 
 		/*

@@ -140,14 +140,14 @@ static void musb_port_reset(struct musb *musb, u8 bReset)
 		if (power &  MGC_M_POWER_RESUME) {
 			while (time_before(jiffies, musb->rh_timer))
 				msleep(1);
-			musb_writeb(mbase, MGC_O_HDRC_POWER,
+			musb_writeb(mbase, MUSB_POWER,
 				power & ~MGC_M_POWER_RESUME);
 			msleep(1);
 		}
 
 		musb->ignore_disconnect = TRUE;
 		power &= 0xf0;
-		musb_writeb(mbase, MGC_O_HDRC_POWER,
+		musb_writeb(mbase, MUSB_POWER,
 				power | MGC_M_POWER_RESET);
 
 		musb->port1_status |= USB_PORT_STAT_RESET;

@@ -155,12 +155,12 @@ static void musb_port_reset(struct musb *musb, u8 bReset)
 		musb->rh_timer = jiffies + msecs_to_jiffies(50);
 	} else {
 		DBG(4, "root port reset stopped\n");
-		musb_writeb(mbase, MGC_O_HDRC_POWER,
+		musb_writeb(mbase, MUSB_POWER,
 				power & ~MGC_M_POWER_RESET);
 
 		musb->ignore_disconnect = FALSE;
 
-		power = musb_readb(mbase, MGC_O_HDRC_POWER);
+		power = musb_readb(mbase, MUSB_POWER);
 		if (power & MGC_M_POWER_HSMODE) {
 			DBG(4, "high-speed device connected\n");
 			musb->port1_status |= USB_PORT_STAT_HIGH_SPEED;

@@ -308,11 +308,11 @@ int musb_hub_control(
 				&& time_after(jiffies, musb->rh_timer)) {
 			u8		power;
 
-			power = musb_readb(musb->mregs, MGC_O_HDRC_POWER);
+			power = musb_readb(musb->mregs, MUSB_POWER);
 			power &= ~MGC_M_POWER_RESUME;
 			DBG(4, "root port resume stopped, power %02x\n",
 					power);
-			musb_writeb(musb->mregs, MGC_O_HDRC_POWER, power);
+			musb_writeb(musb->mregs, MUSB_POWER, power);
 
 			/* ISSUE:  DaVinci (RTL 1.300) disconnects after
 			 * resume of high speed peripherals (but not full

@@ -388,7 +388,7 @@ int musb_hub_control(
 				temp = MGC_M_TEST_FORCE_HOST
 					| MGC_M_TEST_FORCE_HS;
 
-				musb_writeb(musb->mregs, MGC_O_HDRC_DEVCTL, MGC_M_DEVCTL_SESSION);
+				musb_writeb(musb->mregs, MUSB_DEVCTL, MGC_M_DEVCTL_SESSION);
 				break;
 			case 6:
 				pr_debug("TEST_FIFO_ACCESS\n");

@@ -397,7 +397,7 @@ int musb_hub_control(
 			default:
 				goto error;
 			}
-			musb_writeb(musb->mregs, MGC_O_HDRC_TESTMODE, temp);
+			musb_writeb(musb->mregs, MUSB_TESTMODE, temp);
 			break;
 		default:
 			goto error;

index db1fe8f..d902eaa 100644
@@ -501,8 +501,8 @@ static inline int cppi_autoreq_update(struct cppi_channel *rx,
 		void		*__iomem regs = rx->hw_ep->regs;
 
 		val = musb_readw(regs, MUSB_RXCSR);
-		if (!(val & MGC_M_RXCSR_H_REQPKT)) {
-			val |= MGC_M_RXCSR_H_REQPKT | MGC_M_RXCSR_H_WZC_BITS;
+		if (!(val & MUSB_RXCSR_H_REQPKT)) {
+			val |= MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_H_WZC_BITS;
 			musb_writew(regs, MUSB_RXCSR, val);
 			/* flush writebufer */
 			val = musb_readw(regs, MUSB_RXCSR);

@@ -1096,7 +1096,7 @@ static int cppi_rx_scan(struct cppi *cppi, unsigned ch)
 		}
 		musb_ep_select(cppi->pCoreBase, rx->chNo + 1);
 		csr = musb_readw(regs, MUSB_RXCSR);
-		if (csr & MGC_M_RXCSR_DMAENAB) {
+		if (csr & MUSB_RXCSR_DMAENAB) {
 			DBG(4, "list%d %p/%p, last %08x%s, csr %04x\n",
 				rx->chNo,
 				rx->activeQueueHead, rx->activeQueueTail,

@@ -1119,10 +1119,10 @@ static int cppi_rx_scan(struct cppi *cppi, unsigned ch)
 		csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
 		if (is_host_active(cppi->musb)
 				&& bd
-				&& !(csr & MGC_M_RXCSR_H_REQPKT)) {
-			csr |= MGC_M_RXCSR_H_REQPKT;
+				&& !(csr & MUSB_RXCSR_H_REQPKT)) {
+			csr |= MUSB_RXCSR_H_REQPKT;
 			musb_writew(regs, MUSB_RXCSR,
-					MGC_M_RXCSR_H_WZC_BITS | csr);
+					MUSB_RXCSR_H_WZC_BITS | csr);
 			csr = musb_readw(rx->hw_ep->regs, MUSB_RXCSR);
 		}
 	} else {

@@ -1247,7 +1247,7 @@ void cppi_completion(struct musb *musb, u32 rx, u32 tx)
 
 						csr = musb_readw(hw_ep->regs,
 							MUSB_TXCSR);
-						if (csr & MGC_M_TXCSR_TXPKTRDY)
+						if (csr & MUSB_TXCSR_TXPKTRDY)
 #endif
 							bReqComplete = 0;
 					}

@@ -1439,8 +1439,8 @@ static int cppi_channel_abort(struct dma_channel *channel)
 		 */
 
 		regVal = musb_readw(regs, MUSB_TXCSR);
-		regVal &= ~MGC_M_TXCSR_DMAENAB;
-		regVal |= MGC_M_TXCSR_FLUSHFIFO;
+		regVal &= ~MUSB_TXCSR_DMAENAB;
+		regVal |= MUSB_TXCSR_FLUSHFIFO;
 		musb_writew(regs, MUSB_TXCSR, regVal);
 		musb_writew(regs, MUSB_TXCSR, regVal);
 

@@ -1500,13 +1500,13 @@ static int cppi_channel_abort(struct dma_channel *channel)
 
 		/* for host, clear (just) ReqPkt at end of current packet(s) */
 		if (is_host_active(otgCh->pController->musb)) {
-			csr |= MGC_M_RXCSR_H_WZC_BITS;
-			csr &= ~MGC_M_RXCSR_H_REQPKT;
+			csr |= MUSB_RXCSR_H_WZC_BITS;
+			csr &= ~MUSB_RXCSR_H_REQPKT;
 		} else
-			csr |= MGC_M_RXCSR_P_WZC_BITS;
+			csr |= MUSB_RXCSR_P_WZC_BITS;
 
 		/* clear dma enable */
-		csr &= ~(MGC_M_RXCSR_DMAENAB);
+		csr &= ~(MUSB_RXCSR_DMAENAB);
 		musb_writew(regs, MUSB_RXCSR, csr);
 		csr = musb_readw(regs, MUSB_RXCSR);
 

index 8b87424..a7f04a7 100644
@@ -86,7 +86,7 @@ void musb_platform_enable(struct musb *musb)
 	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
 	tmp |= old;
 
-	val = ~MGC_M_INTR_SOF;
+	val = ~MUSB_INTR_SOF;
 	tmp |= ((val & 0x01ff) << DAVINCI_USB_USBINT_SHIFT);
 	musb_writel(musb->ctrl_base, DAVINCI_USB_INT_MASK_SET_REG, tmp);
 

@@ -218,13 +218,13 @@ static void otg_timer(unsigned long _musb)
 		 * case "recover"), in routine "VBUS was valid by the time
 		 * VBUSERR got reported during enumeration" cases.
 		 */
-		if (devctl & MGC_M_DEVCTL_VBUS) {
+		if (devctl & MUSB_DEVCTL_VBUS) {
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 			break;
 		}
 		musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
 		musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
-			MGC_M_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
+			MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
 		break;
 	case OTG_STATE_B_IDLE:
 		if (!is_peripheral_enabled(musb))

@@ -242,9 +242,9 @@ static void otg_timer(unsigned long _musb)
 		 * SRP, but clearly it doesn't.
 		 */
 		musb_writeb(mregs, MUSB_DEVCTL,
-				devctl | MGC_M_DEVCTL_SESSION);
+				devctl | MUSB_DEVCTL_SESSION);
 		devctl = musb_readb(mregs, MUSB_DEVCTL);
-		if (devctl & MGC_M_DEVCTL_BDEVICE)
+		if (devctl & MUSB_DEVCTL_BDEVICE)
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 		else
 			musb->xceiv.state = OTG_STATE_A_IDLE;

@@ -311,10 +311,10 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
 		int	drvvbus = musb_readl(tibase, DAVINCI_USB_STAT_REG);
 		void	*__iomem mregs = musb->mregs;
 		u8	devctl = musb_readb(mregs, MUSB_DEVCTL);
-		int	err = musb->int_usb & MGC_M_INTR_VBUSERROR;
+		int	err = musb->int_usb & MUSB_INTR_VBUSERROR;
 
 		err = is_host_enabled(musb)
-				&& (musb->int_usb & MGC_M_INTR_VBUSERROR);
+				&& (musb->int_usb & MUSB_INTR_VBUSERROR);
 		if (err) {
 			/* The Mentor core doesn't debounce VBUS as needed
 			 * to cope with device connect current spikes. This

@@ -326,7 +326,7 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
 			 * without waiting (on EVM, a **long** time) for VBUS
 			 * to stop registering in devctl.
 			 */
-			musb->int_usb &= ~MGC_M_INTR_VBUSERROR;
+			musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 			musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
 			mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 			WARN("VBUS error workaround (delay coming)\n");

@@ -441,10 +441,10 @@ int musb_platform_exit(struct musb *musb)
 		 */
 		do {
 			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
-			if (!(devctl & MGC_M_DEVCTL_VBUS))
+			if (!(devctl & MUSB_DEVCTL_VBUS))
 				break;
-			if ((devctl & MGC_M_DEVCTL_VBUS) != warn) {
-				warn = devctl & MGC_M_DEVCTL_VBUS;
+			if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
+				warn = devctl & MUSB_DEVCTL_VBUS;
 				DBG(1, "VBUS %d\n", warn >> MGC_S_DEVCTL_VBUS);
 			}
 			msleep(1000);

@@ -452,7 +452,7 @@ int musb_platform_exit(struct musb *musb)
 		} while (maxdelay > 0);
 
 		/* in OTG mode, another host might be connected */
-		if (devctl & MGC_M_DEVCTL_VBUS)
+		if (devctl & MUSB_DEVCTL_VBUS)
 			DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
 	}
 

242 lines not on this page · raw message

504 lines not on this page · raw message

540 lines not on this page · raw message

index ddb478f..1dbacf4 100644
@@ -664,7 +664,7 @@ static int musb_proc_write(struct file *file, const char __user *buffer,
 	case 'C':
 		if (mbase) {
 			bReg = musb_readb(mbase, MUSB_POWER)
-					| MGC_M_POWER_SOFTCONN;
+					| MUSB_POWER_SOFTCONN;
 			musb_writeb(mbase, MUSB_POWER, bReg);
 		}
 		break;

@@ -672,7 +672,7 @@ static int musb_proc_write(struct file *file, const char __user *buffer,
 	case 'c':
 		if (mbase) {
 			bReg = musb_readb(mbase, MUSB_POWER)
-					& ~MGC_M_POWER_SOFTCONN;
+					& ~MUSB_POWER_SOFTCONN;
 			musb_writeb(mbase, MUSB_POWER, bReg);
 		}
 		break;

@@ -680,7 +680,7 @@ static int musb_proc_write(struct file *file, const char __user *buffer,
 	case 'I':
 		if (mbase) {
 			bReg = musb_readb(mbase, MUSB_POWER)
-					| MGC_M_POWER_HSENAB;
+					| MUSB_POWER_HSENAB;
 			musb_writeb(mbase, MUSB_POWER, bReg);
 		}
 		break;

@@ -688,21 +688,21 @@ static int musb_proc_write(struct file *file, const char __user *buffer,
 	case 'i':
 		if (mbase) {
 			bReg = musb_readb(mbase, MUSB_POWER)
-					& ~MGC_M_POWER_HSENAB;
+					& ~MUSB_POWER_HSENAB;
 			musb_writeb(mbase, MUSB_POWER, bReg);
 		}
 		break;
 
 	case 'F':
 		bReg = musb_readb(mbase, MUSB_DEVCTL);
-		bReg |= MGC_M_DEVCTL_SESSION;
+		bReg |= MUSB_DEVCTL_SESSION;
 		musb_writeb(mbase, MUSB_DEVCTL, bReg);
 		break;
 
 	case 'H':
 		if (mbase) {
 			bReg = musb_readb(mbase, MUSB_DEVCTL);
-			bReg |= MGC_M_DEVCTL_HR;
+			bReg |= MUSB_DEVCTL_HR;
 			musb_writeb(mbase, MUSB_DEVCTL, bReg);
 			//MUSB_HST_MODE( ((struct musb*)data) );
 			//WARN("Host Mode\n");

@@ -712,7 +712,7 @@ static int musb_proc_write(struct file *file, const char __user *buffer,
 	case 'h':
 		if (mbase) {
 			bReg = musb_readb(mbase, MUSB_DEVCTL);
-			bReg &= ~MGC_M_DEVCTL_HR;
+			bReg &= ~MUSB_DEVCTL_HR;
 			musb_writeb(mbase, MUSB_DEVCTL, bReg);
 		}
 		break;

@@ -721,7 +721,7 @@ static int musb_proc_write(struct file *file, const char __user *buffer,
 		if (mbase) {
 			musb_load_testpacket(musb);
 			musb_writeb(mbase, MUSB_TESTMODE,
-					MGC_M_TEST_PACKET);
+					MUSB_TEST_PACKET);
 		}
 		break;
 

index d4e8c3e..25dce14 100644
@@ -242,7 +242,7 @@ enum musb_g_ep0_state {
 	{ (_musb)->is_host=FALSE; }
 
 #define test_devctl_hst_mode(_x) \
-	(musb_readb((_x)->mregs, MUSB_DEVCTL)&MGC_M_DEVCTL_HM)
+	(musb_readb((_x)->mregs, MUSB_DEVCTL)&MUSB_DEVCTL_HM)
 
 #define MUSB_MODE(musb) ((musb)->is_host ? "Host" : "Peripheral")
 

304 lines not on this page · raw message

index a1365c0..d25ae87 100644
@@ -61,7 +61,7 @@
 #define MGC_S_HSDMA_ENDPOINT		4
 #define MGC_S_HSDMA_BUSERROR		8
 #define MGC_S_HSDMA_BURSTMODE		9
-#define MGC_M_HSDMA_BURSTMODE		(3 << MGC_S_HSDMA_BURSTMODE)
+#define MUSB_HSDMA_BURSTMODE		(3 << MGC_S_HSDMA_BURSTMODE)
 #define MGC_HSDMA_BURSTMODE_UNSPEC	0
 #define MGC_HSDMA_BURSTMODE_INCR4	1
 #define MGC_HSDMA_BURSTMODE_INCR8	2

@@ -264,9 +264,9 @@ static int dma_channel_abort(struct dma_channel *pChannel)
 
 			csr = musb_readw(mbase,
 				MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR));
-			csr &= ~(MGC_M_TXCSR_AUTOSET |
-				 MGC_M_TXCSR_DMAENAB |
-				 MGC_M_TXCSR_DMAMODE);
+			csr &= ~(MUSB_TXCSR_AUTOSET |
+				 MUSB_TXCSR_DMAENAB |
+				 MUSB_TXCSR_DMAMODE);
 			musb_writew(mbase,
 					MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
 					csr);

@@ -274,9 +274,9 @@ static int dma_channel_abort(struct dma_channel *pChannel)
 		else {
 			csr = musb_readw(mbase,
 				MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR));
-			csr &= ~(MGC_M_RXCSR_AUTOCLEAR |
-				 MGC_M_RXCSR_DMAENAB |
-				 MGC_M_RXCSR_DMAMODE);
+			csr &= ~(MUSB_RXCSR_AUTOCLEAR |
+				 MUSB_RXCSR_DMAENAB |
+				 MUSB_RXCSR_DMAMODE);
 			musb_writew(mbase,
 					MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR),
 					csr);

@@ -346,7 +346,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
 				pChannel->status = MGC_DMA_STATUS_FREE;
 
 				/* completed */
-				if ((devctl & MGC_M_DEVCTL_HM)
+				if ((devctl & MUSB_DEVCTL_HM)
 				    && (pImplChannel->bTransmit)
 				    && ((pChannel->desired_mode == 0)
 					|| (pChannel->actual_len &

@@ -357,7 +357,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
 						pImplChannel->epnum);
 					musb_writew(mbase,
 						MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
-						MGC_M_TXCSR_TXPKTRDY);
+						MUSB_TXCSR_TXPKTRDY);
 				} else
 					musb_dma_completion(
 						pController->pDmaPrivate,

index e62bb76..3664ff8 100644
@@ -65,7 +65,7 @@ static void omap_set_vbus(struct musb *musb, int is_on)
 		musb->is_active = 1;
 		musb->xceiv.default_a = 1;
 		musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
-		devctl |= MGC_M_DEVCTL_SESSION;
+		devctl |= MUSB_DEVCTL_SESSION;
 
 		MUSB_HST_MODE(musb);
 	} else {

@@ -77,7 +77,7 @@ static void omap_set_vbus(struct musb *musb, int is_on)
 
 		musb->xceiv.default_a = 0;
 		musb->xceiv.state = OTG_STATE_B_IDLE;
-		devctl &= ~MGC_M_DEVCTL_SESSION;
+		devctl &= ~MUSB_DEVCTL_SESSION;
 
 		MUSB_DEV_MODE(musb);
 	}

387 lines not on this page · raw message

index fff2553..4b5a4dc 100644
@@ -536,7 +536,7 @@ static void tusb_source_power(struct musb *musb, int is_on)
 		timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
 		musb->xceiv.default_a = 1;
 		musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
-		devctl |= MGC_M_DEVCTL_SESSION;
+		devctl |= MUSB_DEVCTL_SESSION;
 
 		conf |= TUSB_DEV_CONF_USB_HOST_MODE;
 		MUSB_HST_MODE(musb);

@@ -550,7 +550,7 @@ static void tusb_source_power(struct musb *musb, int is_on)
 
 		musb->xceiv.default_a = 0;
 		musb->xceiv.state = OTG_STATE_B_IDLE;
-		devctl &= ~MGC_M_DEVCTL_SESSION;
+		devctl &= ~MUSB_DEVCTL_SESSION;
 
 		conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
 		MUSB_DEV_MODE(musb);

@@ -688,7 +688,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *base)
 				if (musb->xceiv.state != OTG_STATE_B_IDLE) {
 					/* INTR_DISCONNECT can hide... */
 					musb->xceiv.state = OTG_STATE_B_IDLE;
-					musb->int_usb |= MGC_M_INTR_DISCONNECT;
+					musb->int_usb |= MUSB_INTR_DISCONNECT;
 				}
 				musb->is_active = 0;
 			}

@@ -708,7 +708,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *base)
 				DBG(2, "Got SRP, turning on VBUS\n");
 				devctl = musb_readb(musb->mregs,
 							MUSB_DEVCTL);
-				devctl |= MGC_M_DEVCTL_SESSION;
+				devctl |= MUSB_DEVCTL_SESSION;
 				musb_writeb(musb->mregs, MUSB_DEVCTL,
 							devctl);
 				musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;

@@ -755,8 +755,8 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *base)
 			 */
 			devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 			if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
-				if ((devctl & MGC_M_DEVCTL_VBUS)
-						!= MGC_M_DEVCTL_VBUS) {
+				if ((devctl & MUSB_DEVCTL_VBUS)
+						!= MUSB_DEVCTL_VBUS) {
 					DBG(2, "devctl %02x\n", devctl);
 					break;
 				}

index 4141c12..3a4db47 100644
@@ -224,8 +224,8 @@ static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data)
 			DBG(2, "terminating short tx packet\n");
 			musb_ep_select(musb_base, chdat->epnum);
 			csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
-			csr |= MGC_M_TXCSR_MODE | MGC_M_TXCSR_TXPKTRDY
-				| MGC_M_TXCSR_P_WZC_BITS;
+			csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
+				| MUSB_TXCSR_P_WZC_BITS;
 			musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
 		}
 	}

@@ -377,17 +377,17 @@ static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
 	if (chdat->tx) {
 		musb_ep_select(musb_base, chdat->epnum);
 		csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
-		csr |= (MGC_M_TXCSR_AUTOSET | MGC_M_TXCSR_DMAENAB
-			| MGC_M_TXCSR_DMAMODE | MGC_M_TXCSR_MODE);
-		csr &= ~MGC_M_TXCSR_P_UNDERRUN;
+		csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
+			| MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
+		csr &= ~MUSB_TXCSR_P_UNDERRUN;
 		musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
 	} else {
 		musb_ep_select(musb_base, chdat->epnum);
 		csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
-		csr |= MGC_M_RXCSR_DMAENAB;
-		csr &= ~(MGC_M_RXCSR_AUTOCLEAR | MGC_M_RXCSR_DMAMODE);
+		csr |= MUSB_RXCSR_DMAENAB;
+		csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
 		musb_writew(hw_ep->regs, MUSB_RXCSR,
-			csr | MGC_M_RXCSR_P_WZC_BITS);
+			csr | MUSB_RXCSR_P_WZC_BITS);
 	}
 
 	/*

133 lines not on this page · raw message

index a7f04a7..315c06c 100644
@@ -445,7 +445,7 @@ int musb_platform_exit(struct musb *musb)
 				break;
 			if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
 				warn = devctl & MUSB_DEVCTL_VBUS;
-				DBG(1, "VBUS %d\n", warn >> MGC_S_DEVCTL_VBUS);
+				DBG(1, "VBUS %d\n", warn >> MUSB_DEVCTL_VBUS_SHIFT);
 			}
 			msleep(1000);
 			maxdelay--;

index b1601a8..d26910f 100644
@@ -164,7 +164,7 @@
 #define MUSB_DEVCTL_FSDEV      0x40
 #define MUSB_DEVCTL_LSDEV      0x20
 #define MUSB_DEVCTL_VBUS       0x18
-#define MGC_S_DEVCTL_VBUS       3
+#define MUSB_DEVCTL_VBUS_SHIFT	3
 #define MUSB_DEVCTL_HM         0x04
 #define MUSB_DEVCTL_HR         0x02
 #define MUSB_DEVCTL_SESSION    0x01

@@ -219,12 +219,12 @@
 
 /* TxType/RxType */
 #define MUSB_TYPE_SPEED	0xc0
-#define MGC_S_TYPE_SPEED	6
+#define MUSB_TYPE_SPEED_SHIFT	6
 #define MGC_TYPE_SPEED_HIGH	1
 #define MGC_TYPE_SPEED_FULL	2
 #define MGC_TYPE_SPEED_LOW	3
 #define MUSB_TYPE_PROTO	0x30	/* implicitly zero for ep0 */
-#define MGC_S_TYPE_PROTO	4
+#define MUSB_TYPE_PROTO_SHIFT	4
 #define MUSB_TYPE_REMOTE_END	0xf	/* implicitly zero for ep0 */
 
 /* CONFIGDATA */

index d25ae87..5292e2d 100644
@@ -54,14 +54,14 @@
 		(MGC_O_HSDMA_BASE + (_bChannel << 4) + _bOffset)
 
 /* control register (16-bit): */
-#define MGC_S_HSDMA_ENABLE		0
-#define MGC_S_HSDMA_TRANSMIT		1
-#define MGC_S_HSDMA_MODE1		2
-#define MGC_S_HSDMA_IRQENABLE		3
-#define MGC_S_HSDMA_ENDPOINT		4
-#define MGC_S_HSDMA_BUSERROR		8
-#define MGC_S_HSDMA_BURSTMODE		9
-#define MUSB_HSDMA_BURSTMODE		(3 << MGC_S_HSDMA_BURSTMODE)
+#define MUSB_HSDMA_ENABLE_SHIFT		0
+#define MUSB_HSDMA_TRANSMIT_SHIFT		1
+#define MUSB_HSDMA_MODE1_SHIFT		2
+#define MUSB_HSDMA_IRQENABLE_SHIFT		3
+#define MUSB_HSDMA_ENDPOINT_SHIFT		4
+#define MUSB_HSDMA_BUSERROR_SHIFT		8
+#define MUSB_HSDMA_BURSTMODE_SHIFT		9
+#define MUSB_HSDMA_BURSTMODE		(3 << MUSB_HSDMA_BURSTMODE_SHIFT)
 #define MGC_HSDMA_BURSTMODE_UNSPEC	0
 #define MGC_HSDMA_BURSTMODE_INCR4	1
 #define MGC_HSDMA_BURSTMODE_INCR8	2

@@ -185,26 +185,26 @@ static void configure_channel(struct dma_channel *pChannel,
 	    pChannel, packet_sz, dma_addr, dwLength, mode);
 
 	if (mode) {
-		wCsr |= 1 << MGC_S_HSDMA_MODE1;
+		wCsr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
 		if (dwLength < packet_sz) {
 			return FALSE;
 		}
 		if (packet_sz >= 64) {
 			wCsr |=
-			    MGC_HSDMA_BURSTMODE_INCR16 << MGC_S_HSDMA_BURSTMODE;
+			    MGC_HSDMA_BURSTMODE_INCR16 << MUSB_HSDMA_BURSTMODE_SHIFT;
 		} else if (packet_sz >= 32) {
 			wCsr |=
-			    MGC_HSDMA_BURSTMODE_INCR8 << MGC_S_HSDMA_BURSTMODE;
+			    MGC_HSDMA_BURSTMODE_INCR8 << MUSB_HSDMA_BURSTMODE_SHIFT;
 		} else if (packet_sz >= 16) {
 			wCsr |=
-			    MGC_HSDMA_BURSTMODE_INCR4 << MGC_S_HSDMA_BURSTMODE;
+			    MGC_HSDMA_BURSTMODE_INCR4 << MUSB_HSDMA_BURSTMODE_SHIFT;
 		}
 	}
 
-	wCsr |= (pImplChannel->epnum << MGC_S_HSDMA_ENDPOINT)
-		| (1 << MGC_S_HSDMA_ENABLE)
-		| (1 << MGC_S_HSDMA_IRQENABLE)
-		| (pImplChannel->bTransmit ? (1 << MGC_S_HSDMA_TRANSMIT) : 0);
+	wCsr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
+		| (1 << MUSB_HSDMA_ENABLE_SHIFT)
+		| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
+		| (pImplChannel->bTransmit ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) : 0);
 
 	/* address/count */
 	musb_writel(mbase,

@@ -321,7 +321,7 @@ static irqreturn_t dma_controller_irq(int irq, void *private_data)
 				       MGC_HSDMA_CHANNEL_OFFSET(bChannel,
 							MGC_O_HSDMA_CONTROL));
 
-			if (wCsr & (1 << MGC_S_HSDMA_BUSERROR)) {
+			if (wCsr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
 				pImplChannel->Channel.status =
 				    MGC_DMA_STATUS_BUS_ABORT;
 			} else {

index 6e44909..7b516ad 100644
@@ -435,7 +435,7 @@ static irqreturn_t musb_stage0_irq(struct musb * musb, u8 bIntrUSB,
 				 * not get a disconnect irq...
 				 */
 				if ((devctl & MUSB_DEVCTL_VBUS)
-						!= (3 << MGC_S_DEVCTL_VBUS)) {
+						!= (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
 					musb->int_usb |= MUSB_INTR_DISCONNECT;
 					musb->int_usb &= ~MUSB_INTR_SUSPEND;
 					break;

@@ -524,13 +524,13 @@ static irqreturn_t musb_stage0_irq(struct musb * musb, u8 bIntrUSB,
 				devctl,
 				({ char *s;
 				switch (devctl & MUSB_DEVCTL_VBUS) {
-				case 0 << MGC_S_DEVCTL_VBUS:
+				case 0 << MUSB_DEVCTL_VBUS_SHIFT:
 					s = "<SessEnd"; break;
-				case 1 << MGC_S_DEVCTL_VBUS:
+				case 1 << MUSB_DEVCTL_VBUS_SHIFT:
 					s = "<AValid"; break;
-				case 2 << MGC_S_DEVCTL_VBUS:
+				case 2 << MUSB_DEVCTL_VBUS_SHIFT:
 					s = "<VBusValid"; break;
-				//case 3 << MGC_S_DEVCTL_VBUS:
+				//case 3 << MUSB_DEVCTL_VBUS_SHIFT:
 				default:
 					s = "VALID"; break;
 				}; s; }),

@@ -589,7 +589,7 @@ static irqreturn_t musb_stage0_irq(struct musb * musb, u8 bIntrUSB,
 			break;
 		default:
 			if ((devctl & MUSB_DEVCTL_VBUS)
-					== (3 << MGC_S_DEVCTL_VBUS)) {
+					== (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
 				musb->xceiv.state = OTG_STATE_A_HOST;
 				hcd->self.is_b_host = 0;
 			}

index 1fa0cad..9585d00 100644
@@ -497,7 +497,7 @@ static void ep0_txstate(struct musb *musb)
 
 	/* load the data */
 	pFifoSource = (u8 *) request->buf + request->actual;
-	fifo_count = min((unsigned) MGC_END0_FIFOSIZE,
+	fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
 		request->length - request->actual);
 	musb_write_fifo(&musb->endpoints[0], fifo_count, pFifoSource);
 	request->actual += fifo_count;

index 25dce14..5ce0505 100644
@@ -175,7 +175,7 @@ static inline void musb_host_rx(struct musb *m, u8 e) {}
 #endif
 
 #ifndef MUSB_MAX_END0_PACKET
-#define MUSB_MAX_END0_PACKET ((u16)MGC_END0_FIFOSIZE)
+#define MUSB_MAX_END0_PACKET ((u16)MUSB_EP0_FIFOSIZE)
 #endif
 
 /* host side ep0 states */

index d26910f..225fac9 100644
@@ -38,9 +38,7 @@
  * HDRC-specific definitions
  */
 
-#define MGC_MAX_USB_ENDS       16
-
-#define MGC_END0_FIFOSIZE      64	/* this is non-configurable */
+#define MUSB_EP0_FIFOSIZE      64	/* this is non-configurable */
 
 /*
  *     MUSBMHDRC Register map

index 7b516ad..71e89d8 100644
@@ -1335,8 +1335,8 @@ static int __init musb_core_init(u16 wType, struct musb *musb)
 			musb_driver_name, type, aRevision, aDate);
 
 	/* configure ep0 */
-	musb->endpoints[0].max_packet_sz_tx = MGC_END0_FIFOSIZE;
-	musb->endpoints[0].max_packet_sz_rx = MGC_END0_FIFOSIZE;
+	musb->endpoints[0].max_packet_sz_tx = MUSB_EP0_FIFOSIZE;
+	musb->endpoints[0].max_packet_sz_rx = MUSB_EP0_FIFOSIZE;
 
 	/* discover endpoint configuration */
 	musb->nr_endpoints = 1;

index 225fac9..c862e65 100644
@@ -105,17 +105,17 @@
 #define MUSB_CONFIGDATA	MUSB_FIFOSIZE	/* re-used for EP0 */
 
 /* offsets to endpoint registers in indexed model (using INDEX register) */
-#define MGC_INDEXED_OFFSET(_epnum, _bOffset)	\
-	(0x10                   + (_bOffset))
+#define MGC_INDEXED_OFFSET(_epnum, _offset)	\
+	(0x10                   + (_offset))
 
 /* offsets to endpoint registers in flat models */
-#define MGC_FLAT_OFFSET(_epnum, _bOffset)	\
-	(0x100 + (0x10*(_epnum)) + (_bOffset))
+#define MGC_FLAT_OFFSET(_epnum, _offset)	\
+	(0x100 + (0x10*(_epnum)) + (_offset))
 
 #ifdef CONFIG_USB_TUSB6010
 /* TUSB6010 EP0 configuration register is special */
-#define MGC_TUSB_OFFSET(_epnum, _bOffset)	\
-	(0x10 + _bOffset)
+#define MGC_TUSB_OFFSET(_epnum, _offset)	\
+	(0x10 + _offset)
 #include "tusb6010.h"		/* needed "only" for TUSB_EP0_CONF */
 #endif
 

@@ -128,8 +128,8 @@
 #define MUSB_RXHUBADDR	0x06
 #define MUSB_RXHUBPORT	0x07
 
-#define MGC_BUSCTL_OFFSET(_epnum, _bOffset) \
-	(0x80 + (8*(_epnum)) + (_bOffset))
+#define MGC_BUSCTL_OFFSET(_epnum, _offset) \
+	(0x80 + (8*(_epnum)) + (_offset))
 
 /*
  *     MUSBHDRC Register bit masks

index 5292e2d..5b6a42f 100644
@@ -50,8 +50,8 @@
 #define MGC_O_HSDMA_ADDRESS		0x8
 #define MGC_O_HSDMA_COUNT		0xc
 
-#define MGC_HSDMA_CHANNEL_OFFSET(_bChannel, _bOffset)		\
-		(MGC_O_HSDMA_BASE + (_bChannel << 4) + _bOffset)
+#define MGC_HSDMA_CHANNEL_OFFSET(_bChannel, _offset)		\
+		(MGC_O_HSDMA_BASE + (_bChannel << 4) + _offset)
 
 /* control register (16-bit): */
 #define MUSB_HSDMA_ENABLE_SHIFT		0

index ea6db02..99e3dce 100644
@@ -722,13 +722,13 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
 		/* target addr and (for multipoint) hub addr/port */
 		if (musb->is_multipoint) {
 			musb_writeb(mbase,
-				MGC_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
+				MUSB_BUSCTL_OFFSET(epnum, MUSB_TXFUNCADDR),
 				qh->addr_reg);
 			musb_writeb(mbase,
-				MGC_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
+				MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBADDR),
 				qh->h_addr_reg);
 			musb_writeb(mbase,
-				MGC_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
+				MUSB_BUSCTL_OFFSET(epnum, MUSB_TXHUBPORT),
 				qh->h_port_reg);
 /* FIXME if !epnum, do the same for RX ... */
 		} else

index 1dbacf4..dc77420 100644
@@ -285,13 +285,13 @@ dump_end_info(struct musb *musb, u8 epnum, char *aBuffer, unsigned max)
 					musb_readb(regs, MUSB_RXTYPE),
 					/* FIXME:  assumes multipoint */
 					musb_readb(musb->mregs,
-						MGC_BUSCTL_OFFSET(epnum,
+						MUSB_BUSCTL_OFFSET(epnum,
 						MUSB_RXFUNCADDR)),
 					musb_readb(musb->mregs,
-						MGC_BUSCTL_OFFSET(epnum,
+						MUSB_BUSCTL_OFFSET(epnum,
 						MUSB_RXHUBADDR)),
 					musb_readb(musb->mregs,
-						MGC_BUSCTL_OFFSET(epnum,
+						MUSB_BUSCTL_OFFSET(epnum,
 						MUSB_RXHUBPORT))
 					);
 				if (code <= 0)

@@ -373,13 +373,13 @@ dump_end_info(struct musb *musb, u8 epnum, char *aBuffer, unsigned max)
 					musb_readb(regs, MUSB_TXTYPE),
 					/* FIXME:  assumes multipoint */
 					musb_readb(musb->mregs,
-						MGC_BUSCTL_OFFSET(epnum,
+						MUSB_BUSCTL_OFFSET(epnum,
 						MUSB_TXFUNCADDR)),
 					musb_readb(musb->mregs,
-						MGC_BUSCTL_OFFSET(epnum,
+						MUSB_BUSCTL_OFFSET(epnum,
 						MUSB_TXHUBADDR)),
 					musb_readb(musb->mregs,
-						MGC_BUSCTL_OFFSET(epnum,
+						MUSB_BUSCTL_OFFSET(epnum,
 						MUSB_TXHUBPORT))
 					);
 				if (code <= 0)

index 5ce0505..eb09ea2 100644
@@ -220,18 +220,18 @@ enum musb_g_ep0_state {
 #if	defined(CONFIG_USB_TUSB6010)
 #define musb_ep_select(_mbase, _epnum) \
 	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
-#define	MGC_END_OFFSET			MGC_TUSB_OFFSET
+#define	MGC_END_OFFSET			MUSB_TUSB_OFFSET
 
 /* "flat" mapping: each endpoint has its own i/o address */
 #elif	defined(MUSB_FLAT_REG)
 #define musb_ep_select(_mbase, _epnum)	(((void)(_mbase)),((void)(_epnum)))
-#define	MGC_END_OFFSET			MGC_FLAT_OFFSET
+#define	MGC_END_OFFSET			MUSB_FLAT_OFFSET
 
 /* "indexed" mapping: INDEX register controls register bank select */
 #else
 #define musb_ep_select(_mbase, _epnum) \
 	musb_writeb((_mbase), MUSB_INDEX, (_epnum))
-#define	MGC_END_OFFSET			MGC_INDEXED_OFFSET
+#define	MGC_END_OFFSET			MUSB_INDEXED_OFFSET
 #endif
 
 /****************************** FUNCTIONS ********************************/

index c862e65..9646bb6 100644
@@ -105,16 +105,16 @@
 #define MUSB_CONFIGDATA	MUSB_FIFOSIZE	/* re-used for EP0 */
 
 /* offsets to endpoint registers in indexed model (using INDEX register) */
-#define MGC_INDEXED_OFFSET(_epnum, _offset)	\
+#define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
 	(0x10                   + (_offset))
 
 /* offsets to endpoint registers in flat models */
-#define MGC_FLAT_OFFSET(_epnum, _offset)	\
+#define MUSB_FLAT_OFFSET(_epnum, _offset)	\
 	(0x100 + (0x10*(_epnum)) + (_offset))
 
 #ifdef CONFIG_USB_TUSB6010
 /* TUSB6010 EP0 configuration register is special */
-#define MGC_TUSB_OFFSET(_epnum, _offset)	\
+#define MUSB_TUSB_OFFSET(_epnum, _offset)	\
 	(0x10 + _offset)
 #include "tusb6010.h"		/* needed "only" for TUSB_EP0_CONF */
 #endif

@@ -128,7 +128,7 @@
 #define MUSB_RXHUBADDR	0x06
 #define MUSB_RXHUBPORT	0x07
 
-#define MGC_BUSCTL_OFFSET(_epnum, _offset) \
+#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
 	(0x80 + (8*(_epnum)) + (_offset))
 
 /*

index 71e89d8..348c246 100644
@@ -1380,7 +1380,7 @@ static int __init musb_core_init(u16 wType, struct musb *musb)
 
 		hw_ep->regs = MGC_END_OFFSET(i, 0) + mbase;
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
-		hw_ep->target_regs = MGC_BUSCTL_OFFSET(i, 0) + mbase;
+		hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
 		hw_ep->rx_reinit = 1;
 		hw_ep->tx_reinit = 1;
 #endif

index 9646bb6..4a84c2a 100644
@@ -218,9 +218,6 @@
 /* TxType/RxType */
 #define MUSB_TYPE_SPEED	0xc0
 #define MUSB_TYPE_SPEED_SHIFT	6
-#define MGC_TYPE_SPEED_HIGH	1
-#define MGC_TYPE_SPEED_FULL	2
-#define MGC_TYPE_SPEED_LOW	3
 #define MUSB_TYPE_PROTO	0x30	/* implicitly zero for ep0 */
 #define MUSB_TYPE_PROTO_SHIFT	4
 #define MUSB_TYPE_REMOTE_END	0xf	/* implicitly zero for ep0 */

index 4a84c2a..ec2a1af 100644
@@ -1,4 +1,4 @@
-/******************************************************************
+/*
  * Copyright 2005 Mentor Graphics Corporation
  * Copyright (C) 2005-2006 by Texas Instruments
  *

@@ -29,35 +29,29 @@
  * NON-INFRINGEMENT.  MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
  * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
  * GRAPHICS SUPPORT CUSTOMER.
- ******************************************************************/
+ */
 
 #ifndef __MUSB_HDRC_DEFS_H__
 #define __MUSB_HDRC_DEFS_H__
 
-/*
- * HDRC-specific definitions
- */
-
-#define MUSB_EP0_FIFOSIZE      64	/* this is non-configurable */
+#define MUSB_EP0_FIFOSIZE	64	/* This is non-configurable */
 
 /*
- *     MUSBMHDRC Register map
+ * Common USB registers
  */
 
-/* Common USB registers */
-
-#define MUSB_FADDR	0x00	/* 8-bit */
-#define MUSB_POWER	0x01	/* 8-bit */
+#define MUSB_FADDR		0x00	/* 8-bit */
+#define MUSB_POWER		0x01	/* 8-bit */
 
-#define MUSB_INTRTX	0x02	/* 16-bit */
-#define MUSB_INTRRX       0x04
-#define MUSB_INTRTXE      0x06
-#define MUSB_INTRRXE      0x08
-#define MUSB_INTRUSB      0x0A	/* 8 bit */
-#define MUSB_INTRUSBE     0x0B	/* 8 bit */
-#define MUSB_FRAME        0x0C
-#define MUSB_INDEX        0x0E	/* 8 bit */
-#define MUSB_TESTMODE     0x0F	/* 8 bit */
+#define MUSB_INTRTX		0x02	/* 16-bit */
+#define MUSB_INTRRX		0x04
+#define MUSB_INTRTXE		0x06
+#define MUSB_INTRRXE		0x08
+#define MUSB_INTRUSB		0x0A	/* 8 bit */
+#define MUSB_INTRUSBE		0x0B	/* 8 bit */
+#define MUSB_FRAME		0x0C
+#define MUSB_INDEX		0x0E	/* 8 bit */
+#define MUSB_TESTMODE		0x0F	/* 8 bit */
 
 /* Get offset for a given FIFO from musb->mregs */
 #ifdef	CONFIG_USB_TUSB6010

@@ -66,49 +60,51 @@
 #define MUSB_FIFO_OFFSET(epnum)	(0x20 + ((epnum) * 4))
 #endif
 
-/* Additional Control Registers */
+/*
+ * Additional Control Registers
+ */
 
-#define MUSB_DEVCTL	0x60	/* 8 bit */
+#define MUSB_DEVCTL		0x60	/* 8 bit */
 
 /* These are always controlled through the INDEX register */
-#define MUSB_TXFIFOSZ	0x62	/* 8-bit (see masks) */
-#define MUSB_RXFIFOSZ	0x63	/* 8-bit (see masks) */
-#define MUSB_TXFIFOADD	0x64	/* 16-bit offset shifted right 3 */
-#define MUSB_RXFIFOADD	0x66	/* 16-bit offset shifted right 3 */
-
-// vctrl/vstatus:  optional vendor utmi+phy register at 0x68
-#define MUSB_HWVERS	0x6C	/* 8 bit */
-
-#define MUSB_EPINFO	0x78	/* 8 bit */
-#define MUSB_RAMINFO	0x79	/* 8 bit */
-#define MUSB_LINKINFO	0x7a	/* 8 bit */
-#define MUSB_VPLEN	0x7b	/* 8 bit */
-#define MUSB_HS_EOF1	0x7c	/* 8 bit */
-#define MUSB_FS_EOF1	0x7d	/* 8 bit */
-#define MUSB_LS_EOF1	0x7e	/* 8 bit */
-
-/* offsets to endpoint registers */
-#define MUSB_TXMAXP	0x00
-#define MUSB_TXCSR	0x02
-#define MUSB_CSR0		MUSB_TXCSR	/* re-used for EP0 */
-#define MUSB_RXMAXP	0x04
-#define MUSB_RXCSR	0x06
-#define MUSB_RXCOUNT	0x08
-#define MUSB_COUNT0	MUSB_RXCOUNT	/* re-used for EP0 */
-#define MUSB_TXTYPE	0x0A
-#define MUSB_TYPE0	MUSB_TXTYPE	/* re-used for EP0 */
-#define MUSB_TXINTERVAL	0x0B
-#define MUSB_NAKLIMIT0	MUSB_TXINTERVAL	/* re-used for EP0 */
-#define MUSB_RXTYPE	0x0C
-#define MUSB_RXINTERVAL	0x0D
-#define MUSB_FIFOSIZE	0x0F
-#define MUSB_CONFIGDATA	MUSB_FIFOSIZE	/* re-used for EP0 */
-
-/* offsets to endpoint registers in indexed model (using INDEX register) */
+#define MUSB_TXFIFOSZ		0x62	/* 8-bit (see masks) */
+#define MUSB_RXFIFOSZ		0x63	/* 8-bit (see masks) */
+#define MUSB_TXFIFOADD		0x64	/* 16-bit offset shifted right 3 */
+#define MUSB_RXFIFOADD		0x66	/* 16-bit offset shifted right 3 */
+
+/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
+#define MUSB_HWVERS		0x6C	/* 8 bit */
+
+#define MUSB_EPINFO		0x78	/* 8 bit */
+#define MUSB_RAMINFO		0x79	/* 8 bit */
+#define MUSB_LINKINFO		0x7a	/* 8 bit */
+#define MUSB_VPLEN		0x7b	/* 8 bit */
+#define MUSB_HS_EOF1		0x7c	/* 8 bit */
+#define MUSB_FS_EOF1		0x7d	/* 8 bit */
+#define MUSB_LS_EOF1		0x7e	/* 8 bit */
+
+/* Offsets to endpoint registers */
+#define MUSB_TXMAXP		0x00
+#define MUSB_TXCSR		0x02
+#define MUSB_CSR0		MUSB_TXCSR	/* Re-used for EP0 */
+#define MUSB_RXMAXP		0x04
+#define MUSB_RXCSR		0x06
+#define MUSB_RXCOUNT		0x08
+#define MUSB_COUNT0		MUSB_RXCOUNT	/* Re-used for EP0 */
+#define MUSB_TXTYPE		0x0A
+#define MUSB_TYPE0		MUSB_TXTYPE	/* Re-used for EP0 */
+#define MUSB_TXINTERVAL		0x0B
+#define MUSB_NAKLIMIT0		MUSB_TXINTERVAL	/* Re-used for EP0 */
+#define MUSB_RXTYPE		0x0C
+#define MUSB_RXINTERVAL		0x0D
+#define MUSB_FIFOSIZE		0x0F
+#define MUSB_CONFIGDATA		MUSB_FIFOSIZE	/* Re-used for EP0 */
+
+/* Offsets to endpoint registers in indexed model (using INDEX register) */
 #define MUSB_INDEXED_OFFSET(_epnum, _offset)	\
-	(0x10                   + (_offset))
+	(0x10 + (_offset))
 
-/* offsets to endpoint registers in flat models */
+/* Offsets to endpoint registers in flat models */
 #define MUSB_FLAT_OFFSET(_epnum, _offset)	\
 	(0x100 + (0x10*(_epnum)) + (_offset))
 

@@ -116,96 +112,94 @@
 /* TUSB6010 EP0 configuration register is special */
 #define MUSB_TUSB_OFFSET(_epnum, _offset)	\
 	(0x10 + _offset)
-#include "tusb6010.h"		/* needed "only" for TUSB_EP0_CONF */
+#include "tusb6010.h"		/* Needed "only" for TUSB_EP0_CONF */
 #endif
 
 /* "bus control"/target registers, for host side multipoint (external hubs) */
-#define MUSB_TXFUNCADDR	0x00
-#define MUSB_TXHUBADDR	0x02
-#define MUSB_TXHUBPORT	0x03
+#define MUSB_TXFUNCADDR		0x00
+#define MUSB_TXHUBADDR		0x02
+#define MUSB_TXHUBPORT		0x03
 
-#define MUSB_RXFUNCADDR	0x04
-#define MUSB_RXHUBADDR	0x06
-#define MUSB_RXHUBPORT	0x07
+#define MUSB_RXFUNCADDR		0x04
+#define MUSB_RXHUBADDR		0x06
+#define MUSB_RXHUBPORT		0x07
 
 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
 	(0x80 + (8*(_epnum)) + (_offset))
 
 /*
- *     MUSBHDRC Register bit masks
+ * MUSB Register bits
  */
 
 /* POWER */
-
-#define MUSB_POWER_ISOUPDATE   0x80
-#define MUSB_POWER_SOFTCONN    0x40
+#define MUSB_POWER_ISOUPDATE	0x80
+#define MUSB_POWER_SOFTCONN	0x40
 #define MUSB_POWER_HSENAB	0x20
 #define MUSB_POWER_HSMODE	0x10
-#define MUSB_POWER_RESET       0x08
-#define MUSB_POWER_RESUME      0x04
-#define MUSB_POWER_SUSPENDM    0x02
-#define MUSB_POWER_ENSUSPEND   0x01
+#define MUSB_POWER_RESET	0x08
+#define MUSB_POWER_RESUME	0x04
+#define MUSB_POWER_SUSPENDM	0x02
+#define MUSB_POWER_ENSUSPEND	0x01
 
 /* INTRUSB */
-#define MUSB_INTR_SUSPEND    0x01
-#define MUSB_INTR_RESUME     0x02
-#define MUSB_INTR_RESET      0x04
-#define MUSB_INTR_BABBLE     0x04
-#define MUSB_INTR_SOF        0x08
-#define MUSB_INTR_CONNECT    0x10
-#define MUSB_INTR_DISCONNECT 0x20
-#define MUSB_INTR_SESSREQ    0x40
-#define MUSB_INTR_VBUSERROR  0x80	/* FOR SESSION END */
+#define MUSB_INTR_SUSPEND	0x01
+#define MUSB_INTR_RESUME	0x02
+#define MUSB_INTR_RESET		0x04
+#define MUSB_INTR_BABBLE	0x04
+#define MUSB_INTR_SOF		0x08
+#define MUSB_INTR_CONNECT	0x10
+#define MUSB_INTR_DISCONNECT	0x20
+#define MUSB_INTR_SESSREQ	0x40
+#define MUSB_INTR_VBUSERROR	0x80	/* For SESSION end */
 
 /* DEVCTL */
-#define MUSB_DEVCTL_BDEVICE    0x80
-#define MUSB_DEVCTL_FSDEV      0x40
-#define MUSB_DEVCTL_LSDEV      0x20
-#define MUSB_DEVCTL_VBUS       0x18
+#define MUSB_DEVCTL_BDEVICE	0x80
+#define MUSB_DEVCTL_FSDEV	0x40
+#define MUSB_DEVCTL_LSDEV	0x20
+#define MUSB_DEVCTL_VBUS	0x18
 #define MUSB_DEVCTL_VBUS_SHIFT	3
-#define MUSB_DEVCTL_HM         0x04
-#define MUSB_DEVCTL_HR         0x02
-#define MUSB_DEVCTL_SESSION    0x01
+#define MUSB_DEVCTL_HM		0x04
+#define MUSB_DEVCTL_HR		0x02
+#define MUSB_DEVCTL_SESSION	0x01
 
 /* TESTMODE */
-
-#define MUSB_TEST_FORCE_HOST   0x80
-#define MUSB_TEST_FIFO_ACCESS  0x40
-#define MUSB_TEST_FORCE_FS     0x20
-#define MUSB_TEST_FORCE_HS     0x10
-#define MUSB_TEST_PACKET       0x08
-#define MUSB_TEST_K            0x04
-#define MUSB_TEST_J            0x02
-#define MUSB_TEST_SE0_NAK      0x01
-
-/* allocate for double-packet buffering (effectively doubles assigned _SIZE) */
+#define MUSB_TEST_FORCE_HOST	0x80
+#define MUSB_TEST_FIFO_ACCESS	0x40
+#define MUSB_TEST_FORCE_FS	0x20
+#define MUSB_TEST_FORCE_HS	0x10
+#define MUSB_TEST_PACKET	0x08
+#define MUSB_TEST_K		0x04
+#define MUSB_TEST_J		0x02
+#define MUSB_TEST_SE0_NAK	0x01
+
+/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
 #define MUSB_FIFOSZ_DPB	0x10
-/* allocation size (8, 16, 32, ... 4096) */
+/* Allocation size (8, 16, 32, ... 4096) */
 #define MUSB_FIFOSZ_SIZE	0x0f
 
 /* CSR0 */
-#define MUSB_CSR0_FLUSHFIFO      0x0100
-#define MUSB_CSR0_TXPKTRDY       0x0002
-#define MUSB_CSR0_RXPKTRDY       0x0001
+#define MUSB_CSR0_FLUSHFIFO	0x0100
+#define MUSB_CSR0_TXPKTRDY	0x0002
+#define MUSB_CSR0_RXPKTRDY	0x0001
 
 /* CSR0 in Peripheral mode */
-#define MUSB_CSR0_P_SVDSETUPEND  0x0080
-#define MUSB_CSR0_P_SVDRXPKTRDY  0x0040
-#define MUSB_CSR0_P_SENDSTALL    0x0020
-#define MUSB_CSR0_P_SETUPEND     0x0010
-#define MUSB_CSR0_P_DATAEND      0x0008
-#define MUSB_CSR0_P_SENTSTALL    0x0004
+#define MUSB_CSR0_P_SVDSETUPEND	0x0080
+#define MUSB_CSR0_P_SVDRXPKTRDY	0x0040
+#define MUSB_CSR0_P_SENDSTALL	0x0020
+#define MUSB_CSR0_P_SETUPEND	0x0010
+#define MUSB_CSR0_P_DATAEND	0x0008
+#define MUSB_CSR0_P_SENTSTALL	0x0004
 
 /* CSR0 in Host mode */
-#define MUSB_CSR0_H_DIS_PING	0x0800
-#define MUSB_CSR0_H_WR_DATATOGGLE   0x0400	/* set to allow setting: */
-#define MUSB_CSR0_H_DATATOGGLE	    0x0200	/* data toggle control */
-#define MUSB_CSR0_H_NAKTIMEOUT   0x0080
-#define MUSB_CSR0_H_STATUSPKT    0x0040
-#define MUSB_CSR0_H_REQPKT       0x0020
-#define MUSB_CSR0_H_ERROR        0x0010
-#define MUSB_CSR0_H_SETUPPKT     0x0008
-#define MUSB_CSR0_H_RXSTALL      0x0004
+#define MUSB_CSR0_H_DIS_PING		0x0800
+#define MUSB_CSR0_H_WR_DATATOGGLE	0x0400	/* Set to allow setting: */
+#define MUSB_CSR0_H_DATATOGGLE		0x0200	/* Data toggle control */
+#define MUSB_CSR0_H_NAKTIMEOUT		0x0080
+#define MUSB_CSR0_H_STATUSPKT		0x0040
+#define MUSB_CSR0_H_REQPKT		0x0020
+#define MUSB_CSR0_H_ERROR		0x0010
+#define MUSB_CSR0_H_SETUPPKT		0x0008
+#define MUSB_CSR0_H_RXSTALL		0x0004
 
 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
 #define MUSB_CSR0_P_WZC_BITS	\

@@ -214,52 +208,47 @@
 	( MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
 	| MUSB_CSR0_RXPKTRDY )
 
-
 /* TxType/RxType */
-#define MUSB_TYPE_SPEED	0xc0
+#define MUSB_TYPE_SPEED		0xc0
 #define MUSB_TYPE_SPEED_SHIFT	6
-#define MUSB_TYPE_PROTO	0x30	/* implicitly zero for ep0 */
+#define MUSB_TYPE_PROTO		0x30	/* Implicitly zero for ep0 */
 #define MUSB_TYPE_PROTO_SHIFT	4
-#define MUSB_TYPE_REMOTE_END	0xf	/* implicitly zero for ep0 */
+#define MUSB_TYPE_REMOTE_END	0xf	/* Implicitly zero for ep0 */
 
 /* CONFIGDATA */
-
-#define MUSB_CONFIGDATA_MPRXE      0x80	/* auto bulk pkt combining */
-#define MUSB_CONFIGDATA_MPTXE      0x40	/* auto bulk pkt splitting */
-#define MUSB_CONFIGDATA_BIGENDIAN  0x20
-#define MUSB_CONFIGDATA_HBRXE      0x10	/* HB-ISO for RX */
-#define MUSB_CONFIGDATA_HBTXE      0x08	/* HB-ISO for TX */
-#define MUSB_CONFIGDATA_DYNFIFO    0x04	/* dynamic FIFO sizing */
-#define MUSB_CONFIGDATA_SOFTCONE   0x02	/* SoftConnect */
-#define MUSB_CONFIGDATA_UTMIDW     0x01	/* data width 0/1 => 8/16bits */
+#define MUSB_CONFIGDATA_MPRXE		0x80	/* Auto bulk pkt combining */
+#define MUSB_CONFIGDATA_MPTXE		0x40	/* Auto bulk pkt splitting */
+#define MUSB_CONFIGDATA_BIGENDIAN	0x20
+#define MUSB_CONFIGDATA_HBRXE		0x10	/* HB-ISO for RX */
+#define MUSB_CONFIGDATA_HBTXE		0x08	/* HB-ISO for TX */
+#define MUSB_CONFIGDATA_DYNFIFO		0x04	/* Dynamic FIFO sizing */
+#define MUSB_CONFIGDATA_SOFTCONE	0x02	/* SoftConnect */
+#define MUSB_CONFIGDATA_UTMIDW		0x01	/* Data width 0/1 => 8/16bits */
 
 /* TXCSR in Peripheral and Host mode */
-
-#define MUSB_TXCSR_AUTOSET       0x8000
-#define MUSB_TXCSR_MODE          0x2000
-#define MUSB_TXCSR_DMAENAB       0x1000
-#define MUSB_TXCSR_FRCDATATOG    0x0800
-#define MUSB_TXCSR_DMAMODE       0x0400
-#define MUSB_TXCSR_CLRDATATOG    0x0040
-#define MUSB_TXCSR_FLUSHFIFO     0x0008
-#define MUSB_TXCSR_FIFONOTEMPTY  0x0002
-#define MUSB_TXCSR_TXPKTRDY      0x0001
+#define MUSB_TXCSR_AUTOSET		0x8000
+#define MUSB_TXCSR_MODE			0x2000
+#define MUSB_TXCSR_DMAENAB		0x1000
+#define MUSB_TXCSR_FRCDATATOG		0x0800
+#define MUSB_TXCSR_DMAMODE		0x0400
+#define MUSB_TXCSR_CLRDATATOG		0x0040
+#define MUSB_TXCSR_FLUSHFIFO		0x0008
+#define MUSB_TXCSR_FIFONOTEMPTY		0x0002
+#define MUSB_TXCSR_TXPKTRDY		0x0001
 
 /* TXCSR in Peripheral mode */
-
-#define MUSB_TXCSR_P_ISO         0x4000
-#define MUSB_TXCSR_P_INCOMPTX    0x0080
-#define MUSB_TXCSR_P_SENTSTALL   0x0020
-#define MUSB_TXCSR_P_SENDSTALL   0x0010
-#define MUSB_TXCSR_P_UNDERRUN    0x0004
+#define MUSB_TXCSR_P_ISO		0x4000
+#define MUSB_TXCSR_P_INCOMPTX		0x0080
+#define MUSB_TXCSR_P_SENTSTALL		0x0020
+#define MUSB_TXCSR_P_SENDSTALL		0x0010
+#define MUSB_TXCSR_P_UNDERRUN		0x0004
 
 /* TXCSR in Host mode */
-
-#define MUSB_TXCSR_H_WR_DATATOGGLE   0x0200
-#define MUSB_TXCSR_H_DATATOGGLE      0x0100
-#define MUSB_TXCSR_H_NAKTIMEOUT  0x0080
-#define MUSB_TXCSR_H_RXSTALL     0x0020
-#define MUSB_TXCSR_H_ERROR       0x0004
+#define MUSB_TXCSR_H_WR_DATATOGGLE	0x0200
+#define MUSB_TXCSR_H_DATATOGGLE		0x0100
+#define MUSB_TXCSR_H_NAKTIMEOUT		0x0080
+#define MUSB_TXCSR_H_RXSTALL		0x0020
+#define MUSB_TXCSR_H_ERROR		0x0004
 
 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 #define MUSB_TXCSR_P_WZC_BITS	\

@@ -269,36 +258,32 @@
 	( MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
 	| MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY )
 
-
 /* RXCSR in Peripheral and Host mode */
-
-#define MUSB_RXCSR_AUTOCLEAR     0x8000
-#define MUSB_RXCSR_DMAENAB       0x2000
-#define MUSB_RXCSR_DISNYET       0x1000
-#define MUSB_RXCSR_PID_ERR       0x1000
-#define MUSB_RXCSR_DMAMODE       0x0800
-#define MUSB_RXCSR_INCOMPRX      0x0100
-#define MUSB_RXCSR_CLRDATATOG    0x0080
-#define MUSB_RXCSR_FLUSHFIFO     0x0010
-#define MUSB_RXCSR_DATAERROR     0x0008
-#define MUSB_RXCSR_FIFOFULL      0x0002
-#define MUSB_RXCSR_RXPKTRDY      0x0001
+#define MUSB_RXCSR_AUTOCLEAR		0x8000
+#define MUSB_RXCSR_DMAENAB		0x2000
+#define MUSB_RXCSR_DISNYET		0x1000
+#define MUSB_RXCSR_PID_ERR		0x1000
+#define MUSB_RXCSR_DMAMODE		0x0800
+#define MUSB_RXCSR_INCOMPRX		0x0100
+#define MUSB_RXCSR_CLRDATATOG		0x0080
+#define MUSB_RXCSR_FLUSHFIFO		0x0010
+#define MUSB_RXCSR_DATAERROR		0x0008
+#define MUSB_RXCSR_FIFOFULL		0x0002
+#define MUSB_RXCSR_RXPKTRDY		0x0001
 
 /* RXCSR in Peripheral mode */
-
-#define MUSB_RXCSR_P_ISO         0x4000
-#define MUSB_RXCSR_P_SENTSTALL   0x0040
-#define MUSB_RXCSR_P_SENDSTALL   0x0020
-#define MUSB_RXCSR_P_OVERRUN     0x0004
+#define MUSB_RXCSR_P_ISO		0x4000
+#define MUSB_RXCSR_P_SENTSTALL		0x0040
+#define MUSB_RXCSR_P_SENDSTALL		0x0020
+#define MUSB_RXCSR_P_OVERRUN		0x0004
 
 /* RXCSR in Host mode */
-
-#define MUSB_RXCSR_H_AUTOREQ     0x4000
-#define MUSB_RXCSR_H_WR_DATATOGGLE   0x0400
-#define MUSB_RXCSR_H_DATATOGGLE        0x0200
-#define MUSB_RXCSR_H_RXSTALL     0x0040
-#define MUSB_RXCSR_H_REQPKT      0x0020
-#define MUSB_RXCSR_H_ERROR       0x0004
+#define MUSB_RXCSR_H_AUTOREQ		0x4000
+#define MUSB_RXCSR_H_WR_DATATOGGLE	0x0400
+#define MUSB_RXCSR_H_DATATOGGLE		0x0200
+#define MUSB_RXCSR_H_RXSTALL		0x0040
+#define MUSB_RXCSR_H_REQPKT		0x0020
+#define MUSB_RXCSR_H_ERROR		0x0004
 
 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 #define MUSB_RXCSR_P_WZC_BITS	\

@@ -308,9 +293,7 @@
 	( MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
 	| MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY )
 
-
 /* HUBADDR */
 #define MUSB_HUBADDR_MULTI_TT		0x80
 
-
 #endif	/* __MUSB_HDRC_DEFS_H__ */

@@ -1,34 +1,35 @@
 /*
+ * MUSB OTG driver register defines
+ *
  * Copyright 2005 Mentor Graphics Corporation
  * Copyright (C) 2005-2006 by Texas Instruments
+ * Copyright (C) 2006-2007 Nokia Corporation
  *
- * This file is part of the Inventra Controller Driver for Linux.
- *
- * The Inventra Controller Driver for Linux is free software; you
- * can redistribute it and/or modify it under the terms of the GNU
- * General Public License version 2 as published by the Free Software
- * Foundation.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
  *
- * The Inventra Controller Driver for Linux is distributed in
- * the hope that it will be useful, but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
- * License for more details.
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
- * along with The Inventra Controller Driver for Linux ; if not,
- * write to the Free Software Foundation, Inc., 59 Temple Place,
- * Suite 330, Boston, MA  02111-1307  USA
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
- * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
- * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
- * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
- * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
- * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
- * NON-INFRINGEMENT.  MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
- * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
- * GRAPHICS SUPPORT CUSTOMER.
  */
 
 #ifndef __MUSB_HDRC_DEFS_H__