ColdFire: Add MCF547x_8x related header files

ColdFire: Add MCF547x_8x related header files

---
 include/asm-m68k/fec.h           |    7 +-
 include/asm-m68k/fsl_mcdmafec.h  |  167 +++++++++++++
 include/asm-m68k/immap.h         |   93 +++++++
 include/asm-m68k/immap_547x_8x.h |  297 ++++++++++++++++++++++
 include/asm-m68k/m547x_8x.h      |  503 +++++++++++++++++++++++++++++++
+++++++
 5 files changed, 1063 insertions(+), 4 deletions(-)
 create mode 100644 include/asm-m68k/fsl_mcdmafec.h
 create mode 100644 include/asm-m68k/immap_547x_8x.h
 create mode 100644 include/asm-m68k/m547x_8x.h

index 344c5e1..e2bf0db 100644
@@ -95,11 +95,8 @@ typedef struct cpm_buf_desc {
 #define BD_ENET_TX_CSL		((ushort)0x0001)
 #define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
 
-#ifdef CONFIG_MCFFEC
 /*********************************************************************
-*
 * Fast Ethernet Controller (FEC)
-*
 *********************************************************************/
 /* FEC private information */
 struct fec_info_s {

@@ -117,8 +114,10 @@ struct fec_info_s {
 	uint txIdx;
 	char *txbuf;
 	int initialized;
+	struct fec_info_s *next;
 };
 
+#ifdef CONFIG_MCFFEC
 /* Register read/write struct */
 typedef struct fec {
 #ifdef CONFIG_M5272

@@ -254,6 +253,7 @@ typedef struct fec {
 	u32 ieee_r_fdxfc;
 	u32 ieee_r_octets_ok;
 } fec_t;
+#endif				/* CONFIG_MCFFEC */
 
 /*********************************************************************
 * Fast Ethernet Controller (FEC)

@@ -351,5 +351,4 @@ typedef struct fec {
 #define	FEC_RESET_DELAY		100
 #define FEC_RX_TOUT		100
 
-#endif				/* CONFIG_MCFFEC */
 #endif				/* fec_h */

m68k/fsl_mcdmafec.h
new file mode 100644
index 0000000..3c647c2

m68k/immap_547x_8x.h
new file mode 100644
index 0000000..fe1723f

*/
+#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
+#define PCI_SCR_B (0x00000004) /* Bus master enable */
+#define PCI_SCR_M (0x00000002) /* Memory access control */
+#define PCI_SCR_IO (0x00000001) /* I/O access control */
+
+#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
+#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
+#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
+#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
+
+#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
+#define PCI_BAR_BAR1(x) (x & 0xC0000000)
+#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
+#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
+#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
+
+#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
+#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
+#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
+#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
+
+#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
+#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
+#define PCI_GSCR_SE (0x10000000) /* SERR detected */
+#define PCI_GSCR_ER (0x08000000) /* Error response detected */
+#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable
*/
+#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable
*/
+#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable
*/
+#define PCI_GSCR_PR (0x00000001) /* PCI reset */
+
+#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
+#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable
*/
+#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
+#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
+

+#define PCI_TCR1_B5E			(0x00002000)	/*  */
+#define PCI_TCR1_B4E			(0x00001000)	/*  */
+#define PCI_TCR1_B3E			(0x00000800)	/*  */
+#define PCI_TCR1_B2E			(0x00000400)	/*  */
+#define PCI_TCR1_B1E			(0x00000200)	/*  */
+#define PCI_TCR1_B0E			(0x00000100)	/*  */

+#define PCI_TCR1_CR (0x00000001) /* */
+
+#define PCI_TBATR_BAT0(x) (x & 0xFFFC0000)
+#define PCI_TBATR_BAT1(x) (x & 0xC0000000)
+#define PCI_TBATR_EN (0x00000001) /* Enable */
+
+#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
+#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read
multiple */
+#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
+#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
+#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize
*/
+#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
+#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read
multiple */
+#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
+#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
+#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize
*/
+#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
+#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read
multiple */
+#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
+#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
+#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize
*/
+
+#define PCI_ICR_REE (0x04000000) /* Retry error enable */
+#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
+#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
+#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
+
+#define PCIARB_ACR_DS (0x80000000)
+#define PCIARB_ARC_EXTMINTEN(x) (((x)&0x1F) << 17)
+#define PCIARB_ARC_INTMINTEN (0x00010000)
+#define PCIARB_ARC_EXTMPRI(x) (((x)&0x1F) << 1)
+#define PCIARB_ARC_INTMPRI (0x00000001)
+
+#endif /* mcf547x_8x_h */

1.5.2