ppc4xx: Add AMCC Glacier 406GT eval board support
PATCH 1/1 ppc4xx: Add AMCC Glacier 406GT eval board support
This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here:
- 4 ethernet ports instead of 2
- no SATA port
- no USB port
Currently EMAC2+3 are not working. This will be fixed in a later release.
Signed-off-by Stefan Roese <[email protected]>
--- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 9 ++- board/amcc/canyonlands/canyonlands.c | 25 ++++--- cpu/ppc4xx/4xx_enet.c | 51 +++++++++++++- include/configs/canyonlands.h | 125 +++++++++++++++++++++++++++++++--- include/ppc440.h | 4 + include/ppc4xx_enet.h | 4 + 8 files changed, 195 insertions(+), 25 deletions(-)
MAINTAINERS +1 -0
@@ -321,6 +321,7 @@ Stefan Roese <[email protected]> bunbinga PPC405EP canyonlands PPC460EX ebony PPC440GP + glacier PPC460GT haleakala PPC405EXr katmai PPC440SPe kilauea PPC405EX
MAKEALL +1 -0
@@ -185,6 +185,7 @@ LIST_4xx=" \ ERIC \ EXBITGEN \ G2000 \ + glacier \ haleakala \ haleakala_nand \ hcu4 \
Makefile +7 -2
@@ -1170,8 +1170,13 @@ bubinga_config: unconfig CANBT_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd -canyonlands_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc ppc4xx canyonlands amcc +# Canyonlands & Glacier use different U-Boot images +canyonlands_config \ +glacier_config: unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \ + tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h + @$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc canyonlands_nand_config: unconfig @mkdir -p $(obj)include $(obj)board/amcc/canyonlands
board/amcc/canyonlands/canyonlands.c +16 -9
@@ -35,6 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;int board_early_init_f (void ) {u32 sdr0_cust0; +u32 pvr =get_pvr ();/*------------------------------------------------------------------+ * Setup the interrupt controller polarities, triggers, etc.
@@ -105,14 +106,16 @@ int board_early_init_f(void)mtdcr (AHB_TOP ,0x8000004B );mtdcr (AHB_BOT ,0x8000004B ); -/* -* Configure USB-STP pins as alternate and not GPIO -* It seems to be neccessary to configure the STP pins as GPIO -* input at powerup (perhaps while USB reset is asserted). So -* we configure those pins to their "real" function now. -*/ -gpio_config (16 ,GPIO_OUT ,GPIO_ALT1 ,GPIO_OUT_1 ); -gpio_config (19 ,GPIO_OUT ,GPIO_ALT1 ,GPIO_OUT_1 ); +if ((pvr ==PVR_460EX_RA ) || (pvr ==PVR_460EX_SE_RA )) { +/* +* Configure USB-STP pins as alternate and not GPIO +* It seems to be neccessary to configure the STP pins as GPIO +* input at powerup (perhaps while USB reset is asserted). So +* we configure those pins to their "real" function now. +*/ +gpio_config (16 ,GPIO_OUT ,GPIO_ALT1 ,GPIO_OUT_1 ); +gpio_config (19 ,GPIO_OUT ,GPIO_ALT1 ,GPIO_OUT_1 ); + }return 0 ; }
@@ -369,6 +372,7 @@ int misc_init_r(void) {u32 sdr0_srst1 =0 ;u32 eth_cfg; +u32 pvr =get_pvr ();/* * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
@@ -382,7 +386,10 @@ int misc_init_r(void)/* Set the for 2 RGMII mode */ /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL ; - eth_cfg |=SDR0_ETH_CFG_GMC1_BRIDGE_SEL ; +if ((pvr ==PVR_460EX_RA ) || (pvr ==PVR_460EX_SE_RA )) + eth_cfg |=SDR0_ETH_CFG_GMC1_BRIDGE_SEL ; +else + eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL ;mtsdr (SDR0_ETH_CFG , eth_cfg);/*
cpu/ppc4xx/4xx_enet.c +48 -3
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include/configs/canyonlands.h +114 -11
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include/ppc440.h +4 -0
@@ -2018,9 +2018,13 @@#define malrxctp2r (MAL_DCR_BASE+0x42)/* RX 2 Channel table pointer reg */ #define malrxctp3r (MAL_DCR_BASE+0x43)/* RX 3 Channel table pointer reg */ #define malrxctp8r (MAL_DCR_BASE+0x48)/* RX 8 Channel table pointer reg */ +#define malrxctp16r (MAL_DCR_BASE+0x50)/* RX 16 Channel table pointer reg */ +#define malrxctp24r (MAL_DCR_BASE+0x58)/* RX 24 Channel table pointer reg */ #define malrcbs2 (MAL_DCR_BASE+0x62)/* RX 2 Channel buffer size reg */ #define malrcbs3 (MAL_DCR_BASE+0x63)/* RX 3 Channel buffer size reg */ #define malrcbs8 (MAL_DCR_BASE+0x68)/* RX 8 Channel buffer size reg */ +#define malrcbs16 (MAL_DCR_BASE+0x70)/* RX 16 Channel buffer size reg */ +#define malrcbs24 (MAL_DCR_BASE+0x78)/* RX 24 Channel buffer size reg */ #endif /* CONFIG_440GX */
include/ppc4xx_enet.h +4 -0
@@ -213,6 +213,10 @@ typedef struct emac_4xx_hw_st {#define RGMII_FER (RGMII_BASE + 0x00)#define RGMII_SSR (RGMII_BASE + 0x04) +#if defined(CONFIG_460GT ) +#define RGMII1_BASE_OFFSET 0x100 +#endif +/* RGMII Function Enable (FER) Register Bit Definitions */ /* Note: for EMAC 2 and 3 only, 440GX only */ #define RGMII_FER_DIS (0x00)
Signature · 1 line
1.5.4.4