ppc4xx: Optimization for DDR2 initialization for IBM DDR2 memory controller
PATCH 1/1 ppc4xx: Optimization for DDR2 initialization for IBM DDR2 memory controller
PATCH 1/1 ppc4xx: Optimization for DDR2 initialization for IBM DDR2 memory controller
Dear Prodyut Hazarika,
Quoted 27 lines · In message <1219876124.31178.25.camel@svdcld02> you wrote:
Quoted 1 line
From
5dd36e0d171286f59e4ca4e9eb2a040143b4ec33Mon Sep 17 00:00:00 2001From: Prodyut Hazarika <[email protected]>
Date: Wed, 27 Aug 2008 14:51:08 -0700
Subject: [PATCH] Optimization for DDR2 initialization for IBM DDR2 memory controller
Optimized values suggested by Hardware Team at AMCC
Removed Magic numbers from Initialization preload registers
Tested with Kilauea, Glacier, Canyonlands and Katmai boards
About 5-7% improvement seen for LMBench memtestsSigned-off-by Prodyut Hazarika <[email protected]>--- cpu/ppc4xx/44x_spd_ddr2.c | 59 ++++++++++++++++++++++++++++++++------------- 1 files changed, 42 insertions(+), 17 deletions(-)cpu/ppc4xx/44x_spd_ddr2.c +1
-0@@ -118,6 +118,7 @@ static inline void ppc4xx_ibm_ddr2_register_dump(void);#define ODS_FULL 0x00000000#define ODS_REDUCED 0x00000002 +#define OCD_CALIB_DEF 0x00000380/* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */ #define ODT_EB0R (0x80000000 >> 8)
cpu/ppc4xx/44x_spd_ddr2.c phys_size_t initdram(int board_type) · line 574
Quoted 5 lines
cpu/ppc4xx/44x_spd_ddr2.c +1
-1@@ -570,15 +571,24 @@ phys_size_t initdram(int board_type)mtsdram (SDRAM_MCOPT2 , (val & ~(SDRAM_MCOPT2_SREN_MASK |SDRAM_MCOPT2_DCEN_MASK |SDRAM_MCOPT2_IPTR_MASK |SDRAM_MCOPT2_ISIE_MASK )) | - (SDRAM_MCOPT2_DCEN_ENABLE |SDRAM_MCOPT2_IPTR_EXECUTE )); +SDRAM_MCOPT2_IPTR_EXECUTE );
Indentation seems wrong here.
...
Quoted 38 lines
cpu/ppc4xx/44x_spd_ddr2.c +18
-14@@ -1343,22 +1353,36 @@ static void program_initplr(unsigned long *dimm_populated, emr =CMD_EMR |SELECT_EMR | odt | ods; emr2 =CMD_EMR |SELECT_EMR2 ; emr3 =CMD_EMR |SELECT_EMR3 ; -mtsdram (SDRAM_INITPLR0 ,0xB5000000 |CMD_NOP );/* NOP */ +mtsdram (SDRAM_INITPLR0 ,SDRAM_INITPLR_ENABLE |CMD_NOP |/* NOP */ +SDRAM_INITPLR_IMWT_ENCODE (106 ));/* Wait 106 MemClk cycles */ udelay (1000 ); -mtsdram (SDRAM_INITPLR1 ,0x82000400 |CMD_PRECHARGE );/* precharge 8 DDR clock cycle */ -mtsdram (SDRAM_INITPLR2 ,0x80800000 | emr2);/* EMR2 */ -mtsdram (SDRAM_INITPLR3 ,0x80800000 | emr3);/* EMR3 */ -mtsdram (SDRAM_INITPLR4 ,0x80800000 | emr);/* EMR DLL ENABLE */ -mtsdram (SDRAM_INITPLR5 ,0x80800000 | mr |DLL_RESET );/* MR w/ DLL reset */ +mtsdram (SDRAM_INITPLR1 ,SDRAM_INITPLR_ENABLE |CMD_PRECHARGE |/* precharge 4 MemClk cycles */ +SDRAM_INITPLR_IMWT_ENCODE (4 )); +mtsdram (SDRAM_INITPLR2 ,SDRAM_INITPLR_ENABLE | emr2 |/* EMR2 */ +SDRAM_INITPLR_IMWT_ENCODE (2 ));/* Wait tMRD (2 MemClk cycles) */ +mtsdram (SDRAM_INITPLR3 ,SDRAM_INITPLR_ENABLE | emr3 |/* EMR3 */ +SDRAM_INITPLR_IMWT_ENCODE (2 ));/* Wait tMRD (2 MemClk cycles) */ +mtsdram (SDRAM_INITPLR4 ,SDRAM_INITPLR_ENABLE | emr |/* EMR DLL ENABLE */ +SDRAM_INITPLR_IMWT_ENCODE (2 ));/* Wait tMRD (2 MemClk cycles) */ +mtsdram (SDRAM_INITPLR5 ,SDRAM_INITPLR_ENABLE | mr |DLL_RESET |/* MR w/ DLL reset */ +SDRAM_INITPLR_IMWT_ENCODE (200 ));/* 200 cycle wait for DLL reset */ udelay (1000 ); -mtsdram (SDRAM_INITPLR6 ,0x82000400 |CMD_PRECHARGE );/* precharge 8 DDR clock cycle */ -mtsdram (SDRAM_INITPLR7 ,0x8a000000 |CMD_REFRESH );/* Refresh 50 DDR clock cycle */ -mtsdram (SDRAM_INITPLR8 ,0x8a000000 |CMD_REFRESH );/* Refresh 50 DDR clock cycle */ -mtsdram (SDRAM_INITPLR9 ,0x8a000000 |CMD_REFRESH );/* Refresh 50 DDR clock cycle */ -mtsdram (SDRAM_INITPLR10 ,0x8a000000 |CMD_REFRESH );/* Refresh 50 DDR clock cycle */ -mtsdram (SDRAM_INITPLR11 ,0x80000000 | mr);/* MR w/o DLL reset */ -mtsdram (SDRAM_INITPLR12 ,0x80800380 | emr);/* EMR OCD Default */ -mtsdram (SDRAM_INITPLR13 ,0x80800000 | emr);/* EMR OCD Exit */ +mtsdram (SDRAM_INITPLR6 ,SDRAM_INITPLR_ENABLE |CMD_PRECHARGE | +SDRAM_INITPLR_IMWT_ENCODE (4 ));/* precharge 4 MemClk cycles */ +mtsdram (SDRAM_INITPLR7 ,SDRAM_INITPLR_ENABLE |CMD_REFRESH | +SDRAM_INITPLR_IMWT_ENCODE (25 ));/* Refresh 25 MemClk cycles */ +mtsdram (SDRAM_INITPLR8 ,SDRAM_INITPLR_ENABLE |CMD_REFRESH | +SDRAM_INITPLR_IMWT_ENCODE (25 ));/* Refresh 25 MemClk cycles */
cpu/ppc4xx/44x_spd_ddr2.c static void program_initplr(unsigned long *dimm_populated, · line 1385
Quoted 10 lines
cpu/ppc4xx/44x_spd_ddr2.c +10
-0+mtsdram (SDRAM_INITPLR9 ,SDRAM_INITPLR_ENABLE |CMD_REFRESH | +SDRAM_INITPLR_IMWT_ENCODE (25 ));/* Refresh 25 MemClk cycles */ +mtsdram (SDRAM_INITPLR10 ,SDRAM_INITPLR_ENABLE |CMD_REFRESH | +SDRAM_INITPLR_IMWT_ENCODE (25 ));/* Refresh 25 MemClk cycles */ +mtsdram (SDRAM_INITPLR11 ,SDRAM_INITPLR_ENABLE | mr |/* MR w/o DLL reset */ +SDRAM_INITPLR_IMWT_ENCODE (2 ));/* Wait tMRD (2 MemClk cycles) */ +mtsdram (SDRAM_INITPLR12 ,SDRAM_INITPLR_ENABLE |OCD_CALIB_DEF |/* EMR OCD Default */ +SDRAM_INITPLR_IMWT_ENCODE (2 ) | emr);/* Wait tMRD (2 MemClk cycles) */ +mtsdram (SDRAM_INITPLR13 ,SDRAM_INITPLR_ENABLE | emr |/* EMR OCD Exit */ +SDRAM_INITPLR_IMWT_ENCODE (2 ));
Maximum line leength exceeded (significantly!!)
Please clean up and resubmit.
Best regards,
Wolfgang Denk
Signature · 5 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de "Unix is simple, but it takes a genius to understand the simplicity." - Dennis Ritchie