omap3: remove typedefs for configuration structs

Index: u-boot-main/board/omap3/beagle/beagle.c
===================================================================
@@ -103,8 +103,8 @@ void beagle_identify(void)
  */
 int misc_init_r(void)
 {
-	gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
-	gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
 
 	twl4030_power_init();
 	twl4030_led_init();

Index: u-boot-main/board/omap3/evm/evm.c
===================================================================
@@ -92,9 +92,9 @@ void set_muxconf_regs(void)
  */
 static void setup_net_chip(void)
 {
-	gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
-	gpmc_t *gpmc = (gpmc_t *)GPMC_BASE;
-	ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+	struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
+	struct gpmc *gpmc = (struct gpmc *)GPMC_BASE;
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 
 	/* Configure GPMC registers */
 	writel(NET_GPMC_CONFIG1, &gpmc->cs[5].config1);

Index: u-boot-main/board/omap3/pandora/pandora.c
===================================================================
@@ -60,10 +60,10 @@ int board_init(void)
  */
 int misc_init_r(void)
 {
-	gpio_t *gpio1_base = (gpio_t *)OMAP34XX_GPIO1_BASE;
-	gpio_t *gpio4_base = (gpio_t *)OMAP34XX_GPIO4_BASE;
-	gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
-	gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
+	struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
+	struct gpio *gpio4_base = (struct gpio *)OMAP34XX_GPIO4_BASE;
+	struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+	struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
 
 	twl4030_power_init();
 	twl4030_led_init();

Index: u-boot-main/board/omap3/zoom2/zoom2.c
===================================================================
@@ -123,7 +123,7 @@ void zoom2_identify(void)
 int board_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	gpmc_t *gpmc = (gpmc_t *)GPMC_BASE;
+	struct gpmc *gpmc = (struct gpmc *)GPMC_BASE;
 	u32 *gpmc_config;
 
 	gpmc_init ();		/* in SRAM or SDRAM, finish GPMC */

Index: u-boot-main/cpu/arm_cortexa8/omap3/board.c
===================================================================
@@ -59,11 +59,11 @@ static inline void delay(unsigned long l
  *****************************************************************************/
 void secure_unlock_mem(void)
 {
-	pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM;
-	pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM;
-	pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM;
-	pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM;
-	sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;
+	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
+	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
+	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
+	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
+	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
 
 	/* Protection Module Register Target APE (PM_RT) */
 	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);

@@ -234,7 +234,7 @@ void s_init(void)
  * Routine: wait_for_command_complete
  * Description: Wait for posting to finish on watchdog
  *****************************************************************************/
-void wait_for_command_complete(watchdog_t *wd_base)
+void wait_for_command_complete(struct watchdog *wd_base)
 {
 	int pending = 1;
 	do {

@@ -248,8 +248,8 @@ void wait_for_command_complete(watchdog_
  *****************************************************************************/
 void watchdog_init(void)
 {
-	watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 
 	/*
 	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is

Index: u-boot-main/cpu/arm_cortexa8/omap3/clock.c
===================================================================
@@ -41,10 +41,10 @@
 u32 get_osc_clk_speed(void)
 {
 	u32 start, cstart, cend, cdiff, val;
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
-	prm_t *prm_base = (prm_t *)PRM_BASE;
-	gptimer_t *gpt1_base = (gptimer_t *)OMAP34XX_GPT1;
-	s32ktimer_t *s32k_base = (s32ktimer_t *)SYNC_32KTIMER_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+	struct prm *prm_base = (struct prm *)PRM_BASE;
+	struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
+	struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
 
 	val = readl(&prm_base->clksrc_ctrl);
 

@@ -133,8 +133,8 @@ void prcm_init(void)
 	int xip_safe, p0, p1, p2, p3;
 	u32 osc_clk = 0, sys_clkin_sel;
 	u32 clk_index, sil_index = 0;
-	prm_t *prm_base = (prm_t *)PRM_BASE;
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+	struct prm *prm_base = (struct prm *)PRM_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 	dpll_param *dpll_param_p;
 
 	f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +

@@ -341,7 +341,7 @@ void prcm_init(void)
  *****************************************************************************/
 void per_clocks_enable(void)
 {
-	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 
 	/* Enable GP2 timer. */
 	sr32(&prcm_base->clksel_per, 0, 1, 0x1);	/* GPT2 = sys clk */

Index: u-boot-main/cpu/arm_cortexa8/omap3/mem.c
===================================================================
@@ -51,7 +51,7 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
 	M_NAND_GPMC_CONFIG6, 0
 };
 
-gpmc_t *gpmc_cfg_base;
+struct gpmc *gpmc_cfg;
 
 #if defined(CONFIG_ENV_IS_IN_NAND)
 #define GPMC_CS 0

@@ -79,7 +79,7 @@ static u32 gpmc_onenand[GPMC_MAX_REG] =
 
 #endif
 
-static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
 
 /**************************************************************************
  * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow

@@ -146,12 +146,12 @@ void sdrc_init(void)
 
 void do_sdrc_init(u32 cs, u32 early)
 {
-	sdrc_actim_t *sdrc_actim_base;
+	struct sdrc_actim *sdrc_actim_base;
 
 	if(cs)
-		sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL1_BASE;
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
 	else
-		sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL0_BASE;
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
 
 	if (early) {
 		/* reset sdrc controller */

@@ -219,7 +219,7 @@ void gpmc_init(void)
 {
 	/* putting a blanket check on GPMC based on ZeBu for now */
 	u32 *gpmc_config = NULL;
-	gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
+	struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
 	u32 base = 0;
 	u32 size = 0;
 	u32 f_off = CONFIG_SYS_MONITOR_LEN;

@@ -243,7 +243,7 @@ void gpmc_init(void)
 
 #if defined(CONFIG_CMD_NAND)	/* CS 0 */
 	gpmc_config = gpmc_m_nand;
-	gpmc_cfg_base = gpmc_base;
+	gpmc_cfg = gpmc_base;
 
 	base = PISMO1_NAND_BASE;
 	size = PISMO1_NAND_SIZE;

Index: u-boot-main/cpu/arm_cortexa8/omap3/sys_info.c
===================================================================
@@ -32,9 +32,9 @@
 #include <i2c.h>
 
 extern omap3_sysinfo sysinfo;
-static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
-static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
-static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
+static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 static char *rev_s[CPU_3XX_MAX_REV] = {
 				"1.0",
 				"2.0",

@@ -47,7 +47,7 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
  *****************************************************************/
 void dieid_num_r(void)
 {
-	ctrl_id_t *id_base = (ctrl_id_t *)OMAP34XX_ID_L4_IO_BASE;
+	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
 	char *uid_s, die_id[34];
 	u32 id[4];
 

@@ -82,7 +82,7 @@ u32 get_cpu_type(void)
 u32 get_cpu_rev(void)
 {
 	u32 cpuid = 0;
-	ctrl_id_t *id_base;
+	struct ctrl_id *id_base;
 
 	/*
 	 * On ES1.0 the IDCODE register is not exposed on L4

@@ -93,7 +93,7 @@ u32 get_cpu_rev(void)
 		return CPU_3XX_ES10;
 	else {
 		/* Decode the IDs on > ES1.0 */
-		id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
+		id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
 
 		cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
 

Index: u-boot-main/cpu/arm_cortexa8/omap3/timer.c
===================================================================
@@ -37,7 +37,7 @@
 
 static ulong timestamp;
 static ulong lastinc;
-static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
+static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 
 /*
  * Nothing really to do with interrupts, just starts up a counter.

Index: u-boot-main/drivers/mtd/nand/omap_gpmc.c
===================================================================
@@ -30,7 +30,7 @@
 #include <nand.h>
 
 static uint8_t cs;
-static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
+static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
 static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
 
 /*

178 lines not on this page · raw message

Index: u-boot-main/include/asm-arm/arch-omap3/mem.h
===================================================================
@@ -29,12 +29,12 @@
 #define CS1		0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
 
 #ifndef __ASSEMBLY__
-typedef enum {
+enum {
 	STACKED = 0,
 	IP_DDR = 1,
 	COMBO_DDR = 2,
 	IP_SDR = 3,
-} mem_t;
+};
 #endif /* __ASSEMBLY__ */
 
 #define EARLY_INIT	1

Index: u-boot-main/include/asm-arm/arch-omap3/omap3.h
===================================================================
@@ -79,10 +79,10 @@
 
 #ifndef __ASSEMBLY__
 
-typedef struct s32ktimer {
+struct s32ktimer {
 	unsigned char res[0x10];
 	unsigned int s32k_cr;		/* 0x10 */
-} s32ktimer_t;
+};
 
 #endif /* __ASSEMBLY__ */
 

@@ -95,14 +95,14 @@ typedef struct s32ktimer {
 #define OMAP34XX_GPIO6_BASE		0x49058000
 
 #ifndef __ASSEMBLY__
-typedef struct gpio {
+struct gpio {
 	unsigned char res1[0x34];
 	unsigned int oe;		/* 0x34 */
 	unsigned int datain;		/* 0x38 */
 	unsigned char res2[0x54];
 	unsigned int cleardataout;	/* 0x90 */
 	unsigned int setdataout;	/* 0x94 */
-} gpio_t;
+};
 #endif /* __ASSEMBLY__ */
 
 #define GPIO0				(0x1 << 0)

Index: u-boot-main/include/configs/omap3_beagle.h
===================================================================
@@ -300,7 +300,7 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

Index: u-boot-main/include/configs/omap3_evm.h
===================================================================
@@ -292,7 +292,7 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

Index: u-boot-main/include/configs/omap3_overo.h
===================================================================
@@ -285,7 +285,7 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

Index: u-boot-main/include/configs/omap3_pandora.h
===================================================================
@@ -289,7 +289,7 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

Index: u-boot-main/include/configs/omap3_zoom1.h
===================================================================
@@ -297,7 +297,7 @@
 #define CONFIG_SYS_JFFS2_NUM_BANKS	1
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

Index: u-boot-main/include/configs/omap3_zoom2.h
===================================================================
@@ -252,7 +252,7 @@
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
 
 #ifndef __ASSEMBLY__
-extern gpmc_t *gpmc_cfg_base;
+extern struct gpmc *gpmc_cfg;
 extern unsigned int boot_flash_base;
 extern volatile unsigned int boot_flash_env_addr;
 extern unsigned int boot_flash_off;

Index: u-boot-main/board/omap3/evm/evm.c
===================================================================
@@ -93,17 +93,16 @@ void set_muxconf_regs(void)
 static void setup_net_chip(void)
 {
 	struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
-	struct gpmc *gpmc = (struct gpmc *)GPMC_BASE;
 	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 
 	/* Configure GPMC registers */
-	writel(NET_GPMC_CONFIG1, &gpmc->cs[5].config1);
-	writel(NET_GPMC_CONFIG2, &gpmc->cs[5].config2);
-	writel(NET_GPMC_CONFIG3, &gpmc->cs[5].config3);
-	writel(NET_GPMC_CONFIG4, &gpmc->cs[5].config4);
-	writel(NET_GPMC_CONFIG5, &gpmc->cs[5].config5);
-	writel(NET_GPMC_CONFIG6, &gpmc->cs[5].config6);
-	writel(NET_GPMC_CONFIG7, &gpmc->cs[5].config7);
+	writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
+	writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
+	writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
+	writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
+	writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
+	writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
+	writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
 
 	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);

Index: u-boot-main/board/omap3/zoom2/zoom2.c
===================================================================
@@ -123,14 +123,13 @@ void zoom2_identify(void)
 int board_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	struct gpmc *gpmc = (struct gpmc *)GPMC_BASE;
 	u32 *gpmc_config;
 
 	gpmc_init ();		/* in SRAM or SDRAM, finish GPMC */
 
 	/* Configure console support on zoom2 */
 	gpmc_config = gpmc_serial_TL16CP754C;
-	enable_gpmc_cs_config(gpmc_config, &gpmc->cs[4],
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[4],
 			SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
 
 	/* board id for Linux */

Index: u-boot-main/cpu/arm_cortexa8/omap3/mem.c
===================================================================
@@ -41,6 +41,8 @@ unsigned int boot_flash_sec;
 unsigned int boot_flash_type;
 volatile unsigned int boot_flash_env_addr;
 
+struct gpmc *gpmc_cfg;
+
 #if defined(CONFIG_CMD_NAND)
 static u32 gpmc_m_nand[GPMC_MAX_REG] = {
 	M_NAND_GPMC_CONFIG1,

@@ -51,8 +53,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
 	M_NAND_GPMC_CONFIG6, 0
 };
 
-struct gpmc *gpmc_cfg;
-
 #if defined(CONFIG_ENV_IS_IN_NAND)
 #define GPMC_CS 0
 #else

@@ -219,7 +219,7 @@ void gpmc_init(void)
 {
 	/* putting a blanket check on GPMC based on ZeBu for now */
 	u32 *gpmc_config = NULL;
-	struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
+	gpmc_cfg = (struct gpmc *)GPMC_BASE;
 	u32 base = 0;
 	u32 size = 0;
 	u32 f_off = CONFIG_SYS_MONITOR_LEN;

@@ -227,27 +227,26 @@ void gpmc_init(void)
 	u32 config = 0;
 
 	/* global settings */
-	writel(0, &gpmc_base->irqenable); /* isr's sources masked */
-	writel(0, &gpmc_base->timeout_control);/* timeout disable */
+	writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
+	writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
 
-	config = readl(&gpmc_base->config);
+	config = readl(&gpmc_cfg->config);
 	config &= (~0xf00);
-	writel(config, &gpmc_base->config);
+	writel(config, &gpmc_cfg->config);
 
 	/*
 	 * Disable the GPMC0 config set by ROM code
 	 * It conflicts with our MPDB (both at 0x08000000)
 	 */
-	writel(0, &gpmc_base->cs[0].config7);
+	writel(0, &gpmc_cfg->cs[0].config7);
 	sdelay(1000);
 
 #if defined(CONFIG_CMD_NAND)	/* CS 0 */
 	gpmc_config = gpmc_m_nand;
-	gpmc_cfg = gpmc_base;
 
 	base = PISMO1_NAND_BASE;
 	size = PISMO1_NAND_SIZE;
-	enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size);
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
 #if defined(CONFIG_ENV_IS_IN_NAND)
 	f_off = SMNAND_ENV_OFFSET;
 	f_sec = SZ_128K;

@@ -263,7 +262,7 @@ void gpmc_init(void)
 	gpmc_config = gpmc_onenand;
 	base = PISMO1_ONEN_BASE;
 	size = PISMO1_ONEN_SIZE;
-	enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size);
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
 #if defined(CONFIG_ENV_IS_IN_ONENAND)
 	f_off = ONENAND_ENV_OFFSET;
 	f_sec = SZ_128K;

Index: u-boot-main/cpu/arm_cortexa8/omap3/sys_info.c
===================================================================
@@ -32,7 +32,6 @@
 #include <i2c.h>
 
 extern omap3_sysinfo sysinfo;
-static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 static char *rev_s[CPU_3XX_MAX_REV] = {

@@ -160,7 +159,7 @@ u32 get_gpmc0_base(void)
 {
 	u32 b;
 
-	b = readl(&gpmc_base->cs[0].config7);
+	b = readl(&gpmc_cfg->cs[0].config7);
 	b &= 0x1F;		/* keep base [5:0] */
 	b = b << 24;		/* ret 0x0b000000 */
 	return b;

Index: u-boot-main/drivers/mtd/nand/omap_gpmc.c
===================================================================
@@ -30,7 +30,6 @@
 #include <nand.h>
 
 static uint8_t cs;
-static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
 static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
 
 /*

@@ -48,13 +47,13 @@ static void omap_nand_hwcontrol(struct m
 	 */
 	switch (ctrl) {
 	case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
-		this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd;
+		this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 		break;
 	case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
-		this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_adr;
+		this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
 		break;
 	case NAND_CTRL_CHANGE | NAND_NCE:
-		this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_dat;
+		this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 		break;
 	}
 

@@ -74,8 +73,8 @@ static void omap_hwecc_init(struct nand_
 	 * Init ECC Control Register
 	 * Clear all ECC | Enable Reg1
 	 */
-	writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control);
-	writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_base->ecc_size_config);
+	writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
+	writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
 }
 
 /*

@@ -178,7 +177,7 @@ static int omap_calculate_ecc(struct mtd
 	u_int32_t val;
 
 	/* Start Reading from HW ECC1_Result = 0x200 */
-	val = readl(&gpmc_base->ecc1_result);
+	val = readl(&gpmc_cfg->ecc1_result);
 
 	ecc_code[0] = val & 0xFF;
 	ecc_code[1] = (val >> 16) & 0xFF;

@@ -188,7 +187,7 @@ static int omap_calculate_ecc(struct mtd
 	 * Stop reading anymore ECC vals and clear old results
 	 * enable will be called if more reads are required
 	 */
-	writel(0x000, &gpmc_base->ecc_config);
+	writel(0x000, &gpmc_cfg->ecc_config);
 
 	return 0;
 }

@@ -207,7 +206,7 @@ static void omap_enable_hwecc(struct mtd
 	case NAND_ECC_READ:
 	case NAND_ECC_WRITE:
 		/* Clear the ecc result registers, select ecc reg as 1 */
-		writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control);
+		writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 
 		/*
 		 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes

@@ -215,9 +214,9 @@ static void omap_enable_hwecc(struct mtd
 		 * we just have a single ECC engine for all CS
 		 */
 		writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
-			&gpmc_base->ecc_size_config);
+			&gpmc_cfg->ecc_size_config);
 		val = (dev_width << 7) | (cs << 1) | (0x1);
-		writel(val, &gpmc_base->ecc_config);
+		writel(val, &gpmc_cfg->ecc_config);
 		break;
 	default:
 		printf("Error: Unrecognized Mode[%d]!\n", mode);

@@ -311,7 +310,7 @@ int board_nand_init(struct nand_chip *na
 	 */
 	while (cs < GPMC_MAX_CS) {
 		/* Check if NAND type is set */
-		if ((readl(&gpmc_base->cs[cs].config1) & 0xC00) == 0x800) {
+		if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
 			/* Found it!! */
 			break;
 		}

@@ -323,18 +322,18 @@ int board_nand_init(struct nand_chip *na
 		return -ENODEV;
 	}
 
-	gpmc_config = readl(&gpmc_base->config);
+	gpmc_config = readl(&gpmc_cfg->config);
 	/* Disable Write protect */
 	gpmc_config |= 0x10;
-	writel(gpmc_config, &gpmc_base->config);
+	writel(gpmc_config, &gpmc_cfg->config);
 
-	nand->IO_ADDR_R = (void __iomem *)&gpmc_base->cs[cs].nand_dat;
-	nand->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd;
+	nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
+	nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 
 	nand->cmd_ctrl = omap_nand_hwcontrol;
 	nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
 	/* If we are 16 bit dev, our gpmc config tells us that */
-	if ((readl(&gpmc_base->cs[cs].config1) & 0x3000) == 0x1000)
+	if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
 		nand->options |= NAND_BUSWIDTH_16;
 
 	nand->chip_delay = 100;

Index: u-boot-main/include/asm-arm/arch-omap3/cpu.h
===================================================================
@@ -25,34 +25,40 @@
 #ifndef _CPU_H
 #define _CPU_H
 
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
+
 /* Register offsets of common modules */
 /* Control */
+#ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct ctrl {
-	unsigned char res1[0xC0];
-	unsigned short gpmc_nadv_ale;	/* 0xC0 */
-	unsigned short gpmc_noe;	/* 0xC2 */
-	unsigned short gpmc_nwe;	/* 0xC4 */
-	unsigned char res2[0x22A];
-	unsigned int status;		/* 0x2F0 */
-	unsigned int gpstatus;		/* 0x2F4 */
-	unsigned char res3[0x08];
-	unsigned int rpubkey_0;		/* 0x300 */
-	unsigned int rpubkey_1;		/* 0x304 */
-	unsigned int rpubkey_2;		/* 0x308 */
-	unsigned int rpubkey_3;		/* 0x30C */
-	unsigned int rpubkey_4;		/* 0x310 */
-	unsigned char res4[0x04];
-	unsigned int randkey_0;		/* 0x318 */
-	unsigned int randkey_1;		/* 0x31C */
-	unsigned int randkey_2;		/* 0x320 */
-	unsigned int randkey_3;		/* 0x324 */
-	unsigned char res5[0x124];
-	unsigned int ctrl_omap_stat;	/* 0x44C */
+	u8 res1[0xC0];
+	u16 gpmc_nadv_ale;	/* 0xC0 */
+	u16 gpmc_noe;		/* 0xC2 */
+	u16 gpmc_nwe;		/* 0xC4 */
+	u8 res2[0x22A];
+	u32 status;		/* 0x2F0 */
+	u32 gpstatus;		/* 0x2F4 */
+	u8 res3[0x08];
+	u32 rpubkey_0;		/* 0x300 */
+	u32 rpubkey_1;		/* 0x304 */
+	u32 rpubkey_2;		/* 0x308 */
+	u32 rpubkey_3;		/* 0x30C */
+	u32 rpubkey_4;		/* 0x310 */
+	u8 res4[0x04];
+	u32 randkey_0;		/* 0x318 */
+	u32 randkey_1;		/* 0x31C */
+	u32 randkey_2;		/* 0x320 */
+	u32 randkey_3;		/* 0x324 */
+	u8 res5[0x124];
+	u32 ctrl_omap_stat;	/* 0x44C */
 };
 #else /* __ASSEMBLY__ */
 #define CONTROL_STATUS		0x2F0
 #endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
 
 /* cpu type */
 #define OMAP3503		0x5c00

@@ -60,18 +66,20 @@ struct ctrl {
 #define OMAP3525		0x4c00
 #define OMAP3530		0x0c00
 
+#ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct ctrl_id {
-	unsigned char res1[0x4];
-	unsigned int idcode;		/* 0x04 */
-	unsigned int prod_id;		/* 0x08 */
-	unsigned char res2[0x0C];
-	unsigned int die_id_0;		/* 0x18 */
-	unsigned int die_id_1;		/* 0x1C */
-	unsigned int die_id_2;		/* 0x20 */
-	unsigned int die_id_3;		/* 0x24 */
+	u8 res1[0x4];
+	u32 idcode;		/* 0x04 */
+	u32 prod_id;		/* 0x08 */
+	u8 res2[0x0C];
+	u32 die_id_0;		/* 0x18 */
+	u32 die_id_1;		/* 0x1C */
+	u32 die_id_2;		/* 0x20 */
+	u32 die_id_3;		/* 0x24 */
 };
 #endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
 
 /* device type */
 #define DEVICE_MASK		(0x7 << 8)

@@ -84,47 +92,48 @@ struct ctrl_id {
 #define GPMC_BASE		(OMAP34XX_GPMC_BASE)
 #define GPMC_CONFIG_CS0		0x60
 
+#ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct gpmc_cs {
-	unsigned int config1;		/* 0x00 */
-	unsigned int config2;		/* 0x04 */
-	unsigned int config3;		/* 0x08 */
-	unsigned int config4;		/* 0x0C */
-	unsigned int config5;		/* 0x10 */
-	unsigned int config6;		/* 0x14 */
-	unsigned int config7;		/* 0x18 */
-	unsigned int nand_cmd;		/* 0x1C */
-	unsigned int nand_adr;		/* 0x20 */
-	unsigned int nand_dat;		/* 0x24 */
-	unsigned char res[8];		/* blow up to 0x30 byte */
+	u32 config1;		/* 0x00 */
+	u32 config2;		/* 0x04 */
+	u32 config3;		/* 0x08 */
+	u32 config4;		/* 0x0C */
+	u32 config5;		/* 0x10 */
+	u32 config6;		/* 0x14 */
+	u32 config7;		/* 0x18 */
+	u32 nand_cmd;		/* 0x1C */
+	u32 nand_adr;		/* 0x20 */
+	u32 nand_dat;		/* 0x24 */
+	u8 res[8];		/* blow up to 0x30 byte */
 };
 
 struct gpmc {
-	unsigned char res1[0x10];
-	unsigned int sysconfig;		/* 0x10 */
-	unsigned char res2[0x4];
-	unsigned int irqstatus;		/* 0x18 */
-	unsigned int irqenable;		/* 0x1C */
-	unsigned char res3[0x20];
-	unsigned int timeout_control; 	/* 0x40 */
-	unsigned char res4[0xC];
-	unsigned int config;		/* 0x50 */
-	unsigned int status;		/* 0x54 */
-	unsigned char res5[0x8];
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u8 res2[0x4];
+	u32 irqstatus;		/* 0x18 */
+	u32 irqenable;		/* 0x1C */
+	u8 res3[0x20];
+	u32 timeout_control; 	/* 0x40 */
+	u8 res4[0xC];
+	u32 config;		/* 0x50 */
+	u32 status;		/* 0x54 */
+	u8 res5[0x8];
 	struct gpmc_cs cs[8];	/* 0x60, 0x90, .. */
-	unsigned char res6[0x18];
-	unsigned int ecc_config;	/* 0x1F4 */
-	unsigned int ecc_control;	/* 0x1F8 */
-	unsigned int ecc_size_config;	/* 0x1FC */
-	unsigned int ecc1_result;	/* 0x200 */
-	unsigned int ecc2_result;	/* 0x204 */
-	unsigned int ecc3_result;	/* 0x208 */
-	unsigned int ecc4_result;	/* 0x20C */
-	unsigned int ecc5_result;	/* 0x210 */
-	unsigned int ecc6_result;	/* 0x214 */
-	unsigned int ecc7_result;	/* 0x218 */
-	unsigned int ecc8_result;	/* 0x21C */
-	unsigned int ecc9_result;	/* 0x220 */
+	u8 res6[0x18];
+	u32 ecc_config;		/* 0x1F4 */
+	u32 ecc_control;	/* 0x1F8 */
+	u32 ecc_size_config;	/* 0x1FC */
+	u32 ecc1_result;	/* 0x200 */
+	u32 ecc2_result;	/* 0x204 */
+	u32 ecc3_result;	/* 0x208 */
+	u32 ecc4_result;	/* 0x20C */
+	u32 ecc5_result;	/* 0x210 */
+	u32 ecc6_result;	/* 0x214 */
+	u32 ecc7_result;	/* 0x218 */
+	u32 ecc8_result;	/* 0x21C */
+	u32 ecc9_result;	/* 0x220 */
 };
 #else /* __ASSEMBLY__ */
 #define GPMC_CONFIG1		0x00

@@ -135,6 +144,7 @@ struct gpmc {
 #define GPMC_CONFIG6		0x14
 #define GPMC_CONFIG7		0x18
 #endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
 
 /* GPMC Mapping */
 #define FLASH_BASE		0x10000000	/* NOR flash, */

@@ -150,54 +160,58 @@ struct gpmc {
 #define ONENAND_MAP		0x20000000	/* OneNand addr */
 						/* (actual size small port) */
 /* SMS */
+#ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct sms {
-	unsigned char res1[0x10];
-	unsigned int sysconfig;		/* 0x10 */
-	unsigned char res2[0x34];
-	unsigned int rg_att0;		/* 0x48 */
-	unsigned char res3[0x84];
-	unsigned int class_arb0;	/* 0xD0 */
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u8 res2[0x34];
+	u32 rg_att0;		/* 0x48 */
+	u8 res3[0x84];
+	u32 class_arb0;		/* 0xD0 */
 };
 #endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
 
 #define BURSTCOMPLETE_GROUP7	(0x1 << 31)
 
 /* SDRC */
+#ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct sdrc_cs {
-	unsigned int mcfg;		/* 0x80 || 0xB0 */
-	unsigned int mr;		/* 0x84 || 0xB4 */
-	unsigned char res1[0x4];
-	unsigned int emr2;		/* 0x8C || 0xBC */
-	unsigned char res2[0x14];
-	unsigned int rfr_ctrl;		/* 0x84 || 0xD4 */
-	unsigned int manual;		/* 0xA8 || 0xD8 */
-	unsigned char res3[0x4];
+	u32 mcfg;		/* 0x80 || 0xB0 */
+	u32 mr;			/* 0x84 || 0xB4 */
+	u8 res1[0x4];
+	u32 emr2;		/* 0x8C || 0xBC */
+	u8 res2[0x14];
+	u32 rfr_ctrl;		/* 0x84 || 0xD4 */
+	u32 manual;		/* 0xA8 || 0xD8 */
+	u8 res3[0x4];
 };
 
 struct sdrc_actim {
-	unsigned int ctrla;		/* 0x9C || 0xC4 */
-	unsigned int ctrlb;		/* 0xA0 || 0xC8 */
+	u32 ctrla;		/* 0x9C || 0xC4 */
+	u32 ctrlb;		/* 0xA0 || 0xC8 */
 };
 
 struct sdrc {
-	unsigned char res1[0x10];
-	unsigned int sysconfig;		/* 0x10 */
-	unsigned int status;		/* 0x14 */
-	unsigned char res2[0x28];
-	unsigned int cs_cfg;		/* 0x40 */
-	unsigned int sharing;		/* 0x44 */
-	unsigned char res3[0x18];
-	unsigned int dlla_ctrl;		/* 0x60 */
-	unsigned int dlla_status;	/* 0x64 */
-	unsigned int dllb_ctrl;		/* 0x68 */
-	unsigned int dllb_status;	/* 0x6C */
-	unsigned int power;		/* 0x70 */
-	unsigned char res4[0xC];
-	struct sdrc_cs cs[2];		/* 0x80 || 0xB0 */
+	u8 res1[0x10];
+	u32 sysconfig;		/* 0x10 */
+	u32 status;		/* 0x14 */
+	u8 res2[0x28];
+	u32 cs_cfg;		/* 0x40 */
+	u32 sharing;		/* 0x44 */
+	u8 res3[0x18];
+	u32 dlla_ctrl;		/* 0x60 */
+	u32 dlla_status;	/* 0x64 */
+	u32 dllb_ctrl;		/* 0x68 */
+	u32 dllb_status;	/* 0x6C */
+	u32 power;		/* 0x70 */
+	u8 res4[0xC];
+	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };
 #endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
 
 #define DLLPHASE_90		(0x1 << 1)
 #define LOADDLL			(0x1 << 2)

@@ -239,39 +253,43 @@ struct sdrc {
 
 /* timer regs offsets (32 bit regs) */
 
+#ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct gptimer {
-	unsigned int tidr;	/* 0x00 r */
-	unsigned char res[0xc];
-	unsigned int tiocp_cfg;	/* 0x10 rw */
-	unsigned int tistat;	/* 0x14 r */
-	unsigned int tisr;	/* 0x18 rw */
-	unsigned int tier;	/* 0x1c rw */
-	unsigned int twer;	/* 0x20 rw */
-	unsigned int tclr;	/* 0x24 rw */
-	unsigned int tcrr;	/* 0x28 rw */
-	unsigned int tldr;	/* 0x2c rw */
-	unsigned int ttgr;	/* 0x30 rw */
-	unsigned int twpc;	/* 0x34 r*/
-	unsigned int tmar;	/* 0x38 rw*/
-	unsigned int tcar1;	/* 0x3c r */
-	unsigned int tcicr;	/* 0x40 rw */
-	unsigned int tcar2;	/* 0x44 r */
+	u32 tidr;	/* 0x00 r */
+	u8 res[0xc];
+	u32 tiocp_cfg;	/* 0x10 rw */
+	u32 tistat;	/* 0x14 r */
+	u32 tisr;	/* 0x18 rw */
+	u32 tier;	/* 0x1c rw */
+	u32 twer;	/* 0x20 rw */
+	u32 tclr;	/* 0x24 rw */
+	u32 tcrr;	/* 0x28 rw */
+	u32 tldr;	/* 0x2c rw */
+	u32 ttgr;	/* 0x30 rw */
+	u32 twpc;	/* 0x34 r*/
+	u32 tmar;	/* 0x38 rw*/
+	u32 tcar1;	/* 0x3c r */
+	u32 tcicr;	/* 0x40 rw */
+	u32 tcar2;	/* 0x44 r */
 };
 #endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
 
 /* enable sys_clk NO-prescale /1 */
 #define GPT_EN			((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
 
 /* Watchdog */
+#ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct watchdog {
-	unsigned char res1[0x34];
-	unsigned int wwps;	/* 0x34 r */
-	unsigned char res2[0x10];
-	unsigned int wspr;	/* 0x48 rw */
+	u8 res1[0x34];
+	u32 wwps;	/* 0x34 r */
+	u8 res2[0x10];
+	u32 wspr;	/* 0x48 rw */
 };
 #endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
 
 #define WD_UNLOCK1		0xAAAA
 #define WD_UNLOCK2		0x5555

@@ -279,71 +297,72 @@ struct watchdog {
 /* PRCM */
 #define PRCM_BASE		0x48004000
 
+#ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct prcm {
-	unsigned int fclken_iva2;	/* 0x00 */
-	unsigned int clken_pll_iva2;	/* 0x04 */
-	unsigned char res1[0x1c];
-	unsigned int idlest_pll_iva2;	/* 0x24 */
-	unsigned char res2[0x18];
-	unsigned int clksel1_pll_iva2 ;	/* 0x40 */
-	unsigned int clksel2_pll_iva2;	/* 0x44 */
-	unsigned char res3[0x8bc];
-	unsigned int clken_pll_mpu;	/* 0x904 */
-	unsigned char res4[0x1c];
-	unsigned int idlest_pll_mpu;	/* 0x924 */
-	unsigned char res5[0x18];
-	unsigned int clksel1_pll_mpu;	/* 0x940 */
-	unsigned int clksel2_pll_mpu;	/* 0x944 */
-	unsigned char res6[0xb8];
-	unsigned int fclken1_core;	/* 0xa00 */
-	unsigned char res7[0xc];
-	unsigned int iclken1_core;	/* 0xa10 */
-	unsigned int iclken2_core;	/* 0xa14 */
-	unsigned char res8[0x28];
-	unsigned int clksel_core;	/* 0xa40 */
-	unsigned char res9[0xbc];
-	unsigned int fclken_gfx;	/* 0xb00 */
-	unsigned char res10[0xc];
-	unsigned int iclken_gfx;	/* 0xb10 */
-	unsigned char res11[0x2c];
-	unsigned int clksel_gfx;	/* 0xb40 */
-	unsigned char res12[0xbc];
-	unsigned int fclken_wkup;	/* 0xc00 */
-	unsigned char res13[0xc];
-	unsigned int iclken_wkup;	/* 0xc10 */
-	unsigned char res14[0xc];
-	unsigned int idlest_wkup;	/* 0xc20 */
-	unsigned char res15[0x1c];
-	unsigned int clksel_wkup;	/* 0xc40 */
-	unsigned char res16[0xbc];
-	unsigned int clken_pll;		/* 0xd00 */
-	unsigned char res17[0x1c];
-	unsigned int idlest_ckgen;	/* 0xd20 */
-	unsigned char res18[0x1c];
-	unsigned int clksel1_pll;	/* 0xd40 */
-	unsigned int clksel2_pll;	/* 0xd44 */
-	unsigned int clksel3_pll;	/* 0xd48 */
-	unsigned char res19[0xb4];
-	unsigned int fclken_dss;	/* 0xe00 */
-	unsigned char res20[0xc];
-	unsigned int iclken_dss;	/* 0xe10 */
-	unsigned char res21[0x2c];
-	unsigned int clksel_dss;	/* 0xe40 */
-	unsigned char res22[0xbc];
-	unsigned int fclken_cam;	/* 0xf00 */
-	unsigned char res23[0xc];
-	unsigned int iclken_cam;	/* 0xf10 */
-	unsigned char res24[0x2c];
-	unsigned int clksel_cam;	/* 0xf40 */
-	unsigned char res25[0xbc];
-	unsigned int fclken_per;	/* 0x1000 */
-	unsigned char res26[0xc];
-	unsigned int iclken_per;	/* 0x1010 */
-	unsigned char res27[0x2c];
-	unsigned int clksel_per;	/* 0x1040 */
-	unsigned char res28[0xfc];
-	unsigned int clksel1_emu;	/* 0x1140 */
+	u32 fclken_iva2;	/* 0x00 */
+	u32 clken_pll_iva2;	/* 0x04 */
+	u8 res1[0x1c];
+	u32 idlest_pll_iva2;	/* 0x24 */
+	u8 res2[0x18];
+	u32 clksel1_pll_iva2 ;	/* 0x40 */
+	u32 clksel2_pll_iva2;	/* 0x44 */
+	u8 res3[0x8bc];
+	u32 clken_pll_mpu;	/* 0x904 */
+	u8 res4[0x1c];
+	u32 idlest_pll_mpu;	/* 0x924 */
+	u8 res5[0x18];
+	u32 clksel1_pll_mpu;	/* 0x940 */
+	u32 clksel2_pll_mpu;	/* 0x944 */
+	u8 res6[0xb8];
+	u32 fclken1_core;	/* 0xa00 */
+	u8 res7[0xc];
+	u32 iclken1_core;	/* 0xa10 */
+	u32 iclken2_core;	/* 0xa14 */
+	u8 res8[0x28];
+	u32 clksel_core;	/* 0xa40 */
+	u8 res9[0xbc];
+	u32 fclken_gfx;		/* 0xb00 */
+	u8 res10[0xc];
+	u32 iclken_gfx;		/* 0xb10 */
+	u8 res11[0x2c];
+	u32 clksel_gfx;		/* 0xb40 */
+	u8 res12[0xbc];
+	u32 fclken_wkup;	/* 0xc00 */
+	u8 res13[0xc];
+	u32 iclken_wkup;	/* 0xc10 */
+	u8 res14[0xc];
+	u32 idlest_wkup;	/* 0xc20 */
+	u8 res15[0x1c];
+	u32 clksel_wkup;	/* 0xc40 */
+	u8 res16[0xbc];
+	u32 clken_pll;		/* 0xd00 */
+	u8 res17[0x1c];
+	u32 idlest_ckgen;	/* 0xd20 */
+	u8 res18[0x1c];
+	u32 clksel1_pll;	/* 0xd40 */
+	u32 clksel2_pll;	/* 0xd44 */
+	u32 clksel3_pll;	/* 0xd48 */
+	u8 res19[0xb4];
+	u32 fclken_dss;		/* 0xe00 */
+	u8 res20[0xc];
+	u32 iclken_dss;		/* 0xe10 */
+	u8 res21[0x2c];
+	u32 clksel_dss;		/* 0xe40 */
+	u8 res22[0xbc];
+	u32 fclken_cam;		/* 0xf00 */
+	u8 res23[0xc];
+	u32 iclken_cam;		/* 0xf10 */
+	u8 res24[0x2c];
+	u32 clksel_cam;		/* 0xf40 */
+	u8 res25[0xbc];
+	u32 fclken_per;		/* 0x1000 */
+	u8 res26[0xc];
+	u32 iclken_per;		/* 0x1010 */
+	u8 res27[0x2c];
+	u32 clksel_per;		/* 0x1040 */
+	u8 res28[0xfc];
+	u32 clksel1_emu;	/* 0x1140 */
 };
 #else /* __ASSEMBLY__ */
 #define CM_CLKSEL_CORE		0x48004a40

@@ -353,21 +372,24 @@ struct prcm {
 #define CM_CLKSEL1_PLL		0x48004d40
 #define CM_CLKSEL1_EMU		0x48005140
 #endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
 
 #define PRM_BASE		0x48306000
 
+#ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct prm {
-	unsigned char res1[0xd40];
-	unsigned int clksel;		/* 0xd40 */
-	unsigned char res2[0x50c];
-	unsigned int rstctrl;		/* 0x1250 */
-	unsigned char res3[0x1c];
-	unsigned int clksrc_ctrl;	/* 0x1270 */
+	u8 res1[0xd40];
+	u32 clksel;		/* 0xd40 */
+	u8 res2[0x50c];
+	u32 rstctrl;		/* 0x1250 */
+	u8 res3[0x1c];
+	u32 clksrc_ctrl;	/* 0x1270 */
 };
 #else /* __ASSEMBLY__ */
 #define PRM_RSTCTRL		0x48307250
 #endif /* __ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
 
 #define SYSCLKDIV_1		(0x1 << 6)
 #define SYSCLKDIV_2		(0x1 << 7)

@@ -399,22 +421,24 @@ struct prm {
 #define PM_OCM_RAM_BASE_ADDR_ARM	(SMX_APE_BASE + 0x12800)
 #define PM_IVA2_BASE_ADDR_ARM		(SMX_APE_BASE + 0x14000)
 
+#ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
 struct pm {
-	unsigned char res1[0x48];
-	unsigned int req_info_permission_0;	/* 0x48 */
-	unsigned char res2[0x4];
-	unsigned int read_permission_0;		/* 0x50 */
-	unsigned char res3[0x4];
-	unsigned int wirte_permission_0;	/* 0x58 */
-	unsigned char res4[0x4];
-	unsigned int addr_match_1;		/* 0x58 */
-	unsigned char res5[0x4];
-	unsigned int req_info_permission_1;	/* 0x68 */
-	unsigned char res6[0x14];
-	unsigned int addr_match_2;		/* 0x80 */
+	u8 res1[0x48];
+	u32 req_info_permission_0;	/* 0x48 */
+	u8 res2[0x4];
+	u32 read_permission_0;		/* 0x50 */
+	u8 res3[0x4];
+	u32 wirte_permission_0;		/* 0x58 */
+	u8 res4[0x4];
+	u32 addr_match_1;		/* 0x58 */
+	u8 res5[0x4];
+	u32 req_info_permission_1;	/* 0x68 */
+	u8 res6[0x14];
+	u32 addr_match_2;		/* 0x80 */
 };
 #endif /*__ASSEMBLY__ */
+#endif /* __KERNEL_STRICT_NAMES */
 
 /* Permission values for registers -Full fledged permissions to all */
 #define UNLOCK_1			0xFFFFFFFF