Skip to contentSkip to conversation

X86: Fix x86_cache_size value

PATCH Superseded Jaswinder Singh Rajput 2 participants 3 messages Aug 14, 2009 x86

lore
Share & tools
lore

Jaswinder Singh Rajput

author
#0 lore raw

PATCH 1/1 X86: Fix x86_cache_size value

Currently x86_cache_size is showing partial value: L1 or L2 or L3. It should add all caches like L1 + L2 + L3.

Signed-off-by Jaswinder Singh Rajput <[email protected]>
---
 arch/x86/kernel/cpu/common.c          |    2 +-
 arch/x86/kernel/cpu/intel_cacheinfo.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/x86/kernel/cpu/common.c +1 -1
index 5ce60a8..581fe17 100644
@@ -422,7 +422,7 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 		return;		/* Again, no L2 cache is possible */
 #endif
 
-	c->x86_cache_size = l2size;
+	c->x86_cache_size += l2size;
 
 	printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 			l2size, ecx & 0xFF);
arch/x86/kernel/cpu/intel_cacheinfo.c +1 -1
index 789efe2..473c75e 100644
@@ -503,7 +503,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
 	if (l3)
 		printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
 
-	c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
+	c->x86_cache_size = l3 + l2 + l1i + l1d;
 
 	return l2;
 }
Signature · 1 line
1.6.0.6
author
#1 lore raw

PATCH v2 1/1 X86: Fix x86_cache_size value

Currently x86_cache_size is showing partial value: L1 or L2 or L3. It should add all caches like L1 + L2 + L3 + Trace.

Signed-off-by Jaswinder Singh Rajput <[email protected]>
---
 arch/x86/kernel/cpu/common.c          |    2 +-
 arch/x86/kernel/cpu/intel_cacheinfo.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/x86/kernel/cpu/common.c +1 -1
index 5ce60a8..581fe17 100644
@@ -422,7 +422,7 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 		return;		/* Again, no L2 cache is possible */
 #endif
 
-	c->x86_cache_size = l2size;
+	c->x86_cache_size += l2size;
 
 	printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 			l2size, ecx & 0xFF);
arch/x86/kernel/cpu/intel_cacheinfo.c +1 -1
index 789efe2..43da49e 100644
@@ -503,7 +503,7 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
 	if (l3)
 		printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
 
-	c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
+	c->x86_cache_size = l3 + l2 + l1i + l1d + trace;
 
 	return l2;
 }
Signature · 1 line
1.6.0.6
#2 lore raw
Quoted 2 lines · Jaswinder Singh Rajput

Currently x86_cache_size is showing partial value: L1 or L2 or L3. It should add all caches like L1 + L2 + L3 + Trace.

*Why* should it? Adding the L1 cache probably makes little or no difference when the L2/L3 caches are usually so much larger (on my laptop, there's a whole whopping 32K of L1, but 4M of L2 and no L3). It *might* make sense to report L2+L3. It would depend on who uses that number, and for what.

But adding the trace cache is just batshit crazy.