powerpc: Adjust base and index registers in Altivec macros
PATCH 1/1 powerpc: Adjust base and index registers in Altivec macros
On POWER6 systems RA needs to be the base and RB the index. If they are reversed you take a misdirect hit.
Signed-off-by Mike Wolf <[email protected]>
----
arch/powerpc/include/asm/ppc_asm.h +6 -6
@@ -98,13 +98,13 @@#define REST_16FPRS (n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)#define REST_32FPRS (n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) -#define SAVE_VR (n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base +#define SAVE_VR (n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b#define SAVE_2VRS (n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)#define SAVE_4VRS (n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)#define SAVE_8VRS (n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)#define SAVE_16VRS (n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)#define SAVE_32VRS (n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) -#define REST_VR (n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base +#define REST_VR (n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b#define REST_2VRS (n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)#define REST_4VRS (n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)#define REST_8VRS (n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
@@ -112,26 +112,26 @@#define REST_32VRS (n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)/* Save the lower 32 VSRs in the thread VSR region */ -#define SAVE_VSR (n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,b,base) +#define SAVE_VSR (n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,base,b)#define SAVE_2VSRS (n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)#define SAVE_4VSRS (n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)#define SAVE_8VSRS (n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)#define SAVE_16VSRS (n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)#define SAVE_32VSRS (n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) -#define REST_VSR (n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base) +#define REST_VSR (n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b)#define REST_2VSRS (n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)#define REST_4VSRS (n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)#define REST_8VSRS (n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)#define REST_16VSRS (n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)#define REST_32VSRS (n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ -#define SAVE_VSRU (n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,b,base) +#define SAVE_VSRU (n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,base,b)#define SAVE_2VSRSU (n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)#define SAVE_4VSRSU (n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)#define SAVE_8VSRSU (n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)#define SAVE_16VSRSU (n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)#define SAVE_32VSRSU (n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base) -#define REST_VSRU (n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base) +#define REST_VSRU (n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b)#define REST_2VSRSU (n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)#define REST_4VSRSU (n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)#define REST_8VSRSU (n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
Quoted 4 lines
On POWER6 systems RA needs to be the base and RB the index. If they are reversed you take a misdirect hit.
Signed-off-by Mike Wolf <[email protected]>
Looks good.... thanks Mike!
Acked-by Michael Neuling <[email protected]>
Quoted 3 lines
----
---altivec.orig/arch/powerpc/include/asm/ppc_asm.h2009-08-17 15:39:52.000
000000 -0500
Quoted 1 line
+++
altivec/arch/powerpc/include/asm/ppc_asm.h2009-08-20 18:08:30.000
000000 -0500
Quoted 17 lines
arch/powerpc/include/asm/ppc_asm.h +2
-2@@ -98,13 +98,13 @@#define REST_16FPRS (n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)#define REST_32FPRS (n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) -#define SAVE_VR (n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base +#define SAVE_VR (n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b#define SAVE_2VRS (n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)#define SAVE_4VRS (n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)#define SAVE_8VRS (n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)#define SAVE_16VRS (n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)#define SAVE_32VRS (n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) -#define REST_VR (n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base +#define REST_VR (n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b#define REST_2VRS (n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)#define REST_4VRS (n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)#define REST_8VRS (n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
arch/powerpc/include/asm/ppc_asm.h line 119
Quoted 9 lines
arch/powerpc/include/asm/ppc_asm.h +1
-1@@ -112,26 +112,26 @@#define REST_32VRS (n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)/* Save the lower 32 VSRs in the thread VSR region */ -#define SAVE_VSR (n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,b,base) +#define SAVE_VSR (n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,base,b)#define SAVE_2VSRS (n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)#define SAVE_4VSRS (n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)#define SAVE_8VSRS (n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)#define SAVE_16VSRS (n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,
base)
Review line 120
Quoted 1 line
(quoted diff) +0
-0#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16
,b,base)
arch/powerpc/include/asm/ppc_asm.h
Quoted 6 lines
arch/powerpc/include/asm/ppc_asm.h +1
-1-#define REST_VSR (n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,b,base) +#define REST_VSR (n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b)#define REST_2VSRS (n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base)#define REST_4VSRS (n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)#define REST_8VSRS (n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)#define REST_16VSRS (n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,
base)
Review line 126
Quoted 1 line
(quoted diff) +0
-0#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16
,b,base)
arch/powerpc/include/asm/ppc_asm.h
Quoted 4 lines
arch/powerpc/include/asm/ppc_asm.h +1
-1/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ -#define SAVE_VSRU (n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,b,base) +#define SAVE_VSRU (n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,base,b)#define SAVE_2VSRSU (n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,ba
se)
Review line 130
Quoted 1 line
(quoted diff) +0
-0#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,
b,base)
Review line 131
Quoted 1 line
(quoted diff) +0
-0#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,
b,base)
Review line 132
Quoted 1 line
(quoted diff) +0
-0#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,
b,base)
Review line 133
Quoted 1 line
(quoted diff) +0
-0#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+
16,b,base)
arch/powerpc/include/asm/ppc_asm.h
Quoted 3 lines
arch/powerpc/include/asm/ppc_asm.h +1
-1-#define REST_VSRU (n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,b,base) +#define REST_VSRU (n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b)#define REST_2VSRSU (n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,ba
se)
Review line 136
Quoted 1 line
(quoted diff) +0
-0#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,
b,base)
Review line 137
Quoted 1 line
(quoted diff) +0
-0#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,
b,base)
Quoted 7 lines
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