mpc83xx: vme8349: Fix power up reset sequence for tsi148

index d15203c..380f4fb 100644
@@ -2,6 +2,9 @@
  * pci.c -- esd VME8349 PCI board support.
  * Copyright (c) 2006 Wind River Systems, Inc.
  * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <[email protected]>
  *
  * Based on MPC8349 PCI support but w/o PIB related code.
  *

@@ -32,6 +35,7 @@
 #include <pci.h>
 #include <i2c.h>
 #include <asm/fsl_i2c.h>
+#include "vme8349pin.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -93,17 +97,24 @@ pci_init_board(void)
 	udelay(2000);
 
 	/*
-	 * Assert/deassert PCI reset
+	 * Assert/deassert VME reset
 	 */
-	setbits_be32(&immr->gpio[0].dat, 0x00800000);
-	setbits_be32(&immr->gpio[0].dir, 0x00800000);
-	setbits_be32(&immr->gpio[1].dir, 0x08800000);
+	clrbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N |
+		     GPIO2_TSI_PLL_RESET_N);
+	setbits_be32(&immr->gpio[1].dat, GPIO2_VME_RESET_N  |
+		     GPIO2_L_RESET_EN_N);
+
+	setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
+		     GPIO2_TSI_POWERUP_RESET_N |
+		     GPIO2_VME_RESET_N |
+		     GPIO2_L_RESET_EN_N);
+	clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
 	udelay(200);
-	setbits_be32(&immr->gpio[1].dat, 0x08000000);
+	setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
 	udelay(200);
-	setbits_be32(&immr->gpio[1].dat, 0x08800000);
+	setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
 	udelay(600000);
-	clrbits_be32(&immr->gpio[1].dat, 0x00100000);
+	clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
 
 	/* Configure PCI Local Access Windows */
 	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;

@@ -114,6 +125,14 @@ pci_init_board(void)
 
 	udelay(2000);
 
-	if (monarch == 0)
+	if (monarch == 0) {
 		mpc83xx_pci_init(1, reg, 0);
+	} else {
+		/*
+		 * Release PCI RST Output signal
+		 */
+		immr->pci_ctrl[0].gcr = 0;
+		udelay(2000);
+		immr->pci_ctrl[0].gcr = 1;
+	}
 }

new file mode 100644
index 0000000..d1fd1b2
@@ -0,0 +1,36 @@
+/*
+ * vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __VME8349PIN_H__
+#define __VME8349PIN_H__
+
+#define GPIO2_V_SCON		0x80000000 /* In:  from tsi148 1: is syscon */
+#define GPIO2_VME_RESET_N	0x20000000 /* Out: to tsi148                */
+#define GPIO2_TSI_PLL_RESET_N	0x08000000 /* Out: to tsi148                */
+#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148              */
+#define GPIO2_L_RESET_EN_N	0x00100000 /* Out: 0:vme can assert cpu lrst*/
+
+#endif /* of ifndef __VME8349PIN_H__ */