(no subject)

Bcc:
Subject: GPIO chip select support in omap2_mcspi driver

Hey,

Recently I have been looking to use a BeagleBoard to drive several serial ADCs and DACs in a data acquisition and analysis setup. Unfortunately, the BeagleBoard is severely limited by the number of SPI controllers it exposes on the expansion connector (McSPI3 with 2 CS lines and McSPI4 with one). This is insufficient for our application and thus I have been investigating adding support to the mcspi driver for using GPIO lines as chip select lines, as is done in the pxa2xx, bfin5xx, and s3c24xx drivers.

To this end, I have a few questions about how this support was implemented. First, it seems that the s3c24xx driver is built on the spi_bitbang driver, despite interfacing with a dedicated hardware SPI controller. What is the reason for this? Was this done specifically for the purpose of incorporating support for GPIO CS pins?

It seems like the rough idea is to add a cs_gpio field to the device struct (omap2_mcspi) and add the appropriate code to the omap2_mcspi_force_cs() to bring cs_gpio high or low if it is valid. The potential problem I can see with this is that omap2_mcspi_set_enable() is called to enable the channel before the force_cs() is called (in omap2_mcspi_work()). If I'm interpreting the documentation correctly, the enable bit starts the clocks, meaning that the chip will begin clocking out data before CS is brought high. I must be missing something here, no?

For reference, I included a short list of relevant commits below, largely for my own benefit. I would greatly appreciate any feedback you might have.

Thanks,
- Ben

pxa2xx_spi: a7bb3909b3293d503211d7f6af8ed62c1644b686
bfin_spi: 42c78b2bf51bafb4cfa98dfecc28dd9b8bcd04b0

Bcc:
Subject: GPIO chip select support in omap2_mcspi driver

Hey,

Recently I have been looking to use a BeagleBoard to drive several serial ADCs and DACs in a data acquisition and analysis setup. Unfortunately, the BeagleBoard is severely limited by the number of SPI controllers it exposes on the expansion connector (McSPI3 with 2 CS lines and McSPI4 with one). This is insufficient for our application and thus I have been investigating adding support to the mcspi driver for using GPIO lines as chip select lines, as is done in the pxa2xx, bfin5xx, and s3c24xx drivers.

To this end, I have a few questions about how this support was implemented. First, it seems that the s3c24xx driver is built on the spi_bitbang driver, despite interfacing with a dedicated hardware SPI controller. What is the reason for this? Was this done specifically for the purpose of incorporating support for GPIO CS pins?

It seems like the rough idea is to add a cs_gpio field to the device struct (omap2_mcspi) and add the appropriate code to the omap2_mcspi_force_cs() to bring cs_gpio high or low if it is valid. The potential problem I can see with this is that omap2_mcspi_set_enable() is called to enable the channel before the force_cs() is called (in omap2_mcspi_work()). If I'm interpreting the documentation correctly, the enable bit starts the clocks, meaning that the chip will begin clocking out data before CS is brought high. I must be missing something here, no?

For reference, I included a short list of relevant commits below, largely for my own benefit. I would greatly appreciate any feedback you might have.

Thanks,
- Ben

pxa2xx_spi: a7bb3909b3293d503211d7f6af8ed62c1644b686
bfin_spi: 42c78b2bf51bafb4cfa98dfecc28dd9b8bcd04b0

Bcc:
Subject: GPIO chip select support in omap2_mcspi driver

Hey,

Recently I have been looking to use a BeagleBoard to drive several serial ADCs and DACs in a data acquisition and analysis setup. Unfortunately, the BeagleBoard is severely limited by the number of SPI controllers it exposes on the expansion connector (McSPI3 with 2 CS lines and McSPI4 with one). This is insufficient for our application and thus I have been investigating adding support to the mcspi driver for using GPIO lines as chip select lines, as is done in the pxa2xx, bfin5xx, and s3c24xx drivers.

To this end, I have a few questions about how this support was implemented. First, it seems that the s3c24xx driver is built on the spi_bitbang driver, despite interfacing with a dedicated hardware SPI controller. What is the reason for this? Was this done specifically for the purpose of incorporating support for GPIO CS pins?

It seems like the rough idea is to add a cs_gpio field to the device struct (omap2_mcspi) and add the appropriate code to the omap2_mcspi_force_cs() to bring cs_gpio high or low if it is valid. The potential problem I can see with this is that omap2_mcspi_set_enable() is called to enable the channel before the force_cs() is called (in omap2_mcspi_work()). If I'm interpreting the documentation correctly, the enable bit starts the clocks, meaning that the chip will begin clocking out data before CS is brought high. I must be missing something here, no?

For reference, I included a short list of relevant commits below, largely for my own benefit. I would greatly appreciate any feedback you might have.

Thanks,
- Ben

pxa2xx_spi: a7bb3909b3293d503211d7f6af8ed62c1644b686
bfin_spi: 42c78b2bf51bafb4cfa98dfecc28dd9b8bcd04b0

Bcc:
Subject: GPIO chip select support in omap2_mcspi driver

It seems like the rough idea is to add a cs_gpio field to the device struct (omap2_mcspi) and add the appropriate code to the omap2_mcspi_force_cs() to bring cs_gpio high or low if it is valid. The potential problem I can see with this is that omap2_mcspi_set_enable() is called to enable the channel before the force_cs() is called (in omap2_mcspi_work()). If I'm interpreting the documentation correctly, the enable bit starts the clocks, meaning that the chip will begin clocking out data before CS is brought high. I must be missing something here, no?

As I am writing this, it now occurs to me that perhaps the chip doesn't start SPI_CLK until it has data to send.

Quoted 2 lines · Ben Gamari

As I am writing this, it now occurs to me that perhaps the chip doesn't start SPI_CLK until it has data to send.

... or receive. This is indeed the case.

Thanks for your prompt reply. Hopefully you'll see a patch from me about this in the next few days. I'm assuming this functionality would be welcome in mainline?

Hey all!

Recently I've been thinking about adding support to the McSPI driver for using GPIO pins as chip selects. As a starting point, I've browsed the driver source trying to identify what changes would be necessary to add this support. It seems like the rough idea is,

Quoted 6 lines

Hey all!

Recently I've been thinking about adding support to the McSPI driver for using GPIO pins as chip selects. As a starting point, I've browsed the driver source trying to identify what changes would be necessary to add this support. It seems like the rough idea is,

You may loot at drivers/spi/spi_s3c64xx.c in Grant Likely's tree.

Excerpts from jassi brar's message of Wed Jan 27 23:33:20 -0500 2010:

Quoted 9 lines · Ben Gamari

Quoted 6 lines

Hey all!

Recently I've been thinking about adding support to the McSPI driver for using GPIO pins as chip selects. As a starting point, I've browsed the driver source trying to identify what changes would be necessary to add this support. It seems like the rough idea is,

You may loot at drivers/spi/spi_s3c64xx.c in Grant Likely's tree.

Grant,

I think that you might be missing a file in your spi-next branch. I've been unable to find <plat/s3c64xx-spi.h> as referenced in drivers/spi/spi_s3c64xx.c. I don't have an ARM toolchain to try compiling the tree at the moment, but both ctags and find have been unable to find this header. Sorry if I'm just being dense.

the arch/mach specific stuff will come via the SoC maintainer's(Ben Dooks) tree as I already mentioned.

This mechanism is in large part stolen from the s3c64xx-spi module. To use this functionality, one simply must define a set_level function to set the CS state and a omap2_mcspi_csinfo struct for each chip select in the board file.

Each spi_board_info.controller_data should then be set
to point to the appropriate csinfo struct. This will cause the driver to call the csinfo->set_level function instead of toggling the McSPI chip select lines.

Signed-off-by Ben Gamari <[email protected]>

---
 arch/arm/plat-omap/include/plat/mcspi.h |   14 ++++++++++++++
 drivers/spi/omap2_mcspi.c               |   14 +++++++++-----
 2 files changed, 23 insertions(+), 5 deletions(-)

arch/arm/plat-omap/include/plat/mcspi.h +14 -0

index 1254e49..ab84b8d 100644
@@ -1,6 +1,20 @@
 #ifndef _OMAP2_MCSPI_H
 #define _OMAP2_MCSPI_H
 
+/**
+ * struct omap2_mcspi_csinfo - Chip Select description
+ * @line: Custom 'identity' of the CS line
+ * @set_level: Function to set the state of a given CS line
+ *
+ * This is to allow use of GPIO lines as CS lines. Allocate and initialize one
+ * in the machine init code and make spi_board_info.controller_data point to
+ * it.
+ */
+struct omap2_mcspi_csinfo {
+        unsigned line;
+        void (*set_level)(unsigned line_id, int lvl);
+};
+
 struct omap2_mcspi_platform_config {
 	unsigned short	num_cs;
 };

drivers/spi/omap2_mcspi.c +9 -5

index 2a651e6..92ccbd6 100644
@@ -35,6 +35,7 @@
 #include <linux/slab.h>
 
 #include <linux/spi/spi.h>
+#include <linux/gpio.h>
 
 #include <plat/dma.h>
 #include <plat/clock.h>

@@ -235,11 +236,14 @@ static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 
 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 {
-	u32 l;
-
-	l = mcspi_cached_chconf0(spi);
-	MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
-	mcspi_write_chconf0(spi, l);
+	if (spi->controller_data) {
+		struct omap2_mcspi_csinfo *csinfo = spi->controller_data;
+		(*csinfo->set_level)(csinfo->line, cs_active);
+	} else {
+		u32 l = mcspi_cached_chconf0(spi);
+		MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
+		mcspi_write_chconf0(spi, l);
+	}
 }
 
 static void omap2_mcspi_set_master_mode(struct spi_master *master)

Signature · 6 lines

1.7.1

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This mechanism is in large part stolen from the s3c64xx-spi module. To use this functionality, one simply must define a set_level function to set the CS state and a omap2_mcspi_csinfo struct for each chip select in the board file.

Each spi_board_info.controller_data should then be set
to point to the appropriate csinfo struct. This will cause the driver to call the csinfo->set_level function instead of toggling the McSPI chip select lines.

Signed-off-by Ben Gamari <[email protected]>

---
 arch/arm/plat-omap/include/plat/mcspi.h |   14 ++++++++++++++ drivers/spi/omap2_mcspi.c               |   14 +++++++++-----

 2 files changed, 23 insertions(+), 5 deletions(-)

arch/arm/plat-omap/include/plat/mcspi.h +14 -0

index 1254e49..ab84b8d 100644
@@ -1,6 +1,20 @@
  #ifndef _OMAP2_MCSPI_H
  #define _OMAP2_MCSPI_H
 
+/**
+ * struct omap2_mcspi_csinfo - Chip Select description
+ * @line: Custom 'identity' of the CS line
+ * @set_level: Function to set the state of a given CS line
+ *
+ * This is to allow use of GPIO lines as CS lines. Allocate and initialize one
+ * in the machine init code and make spi_board_info.controller_data point to
+ * it.
+ */
+struct omap2_mcspi_csinfo {
+        unsigned line;
+        void (*set_level)(unsigned line_id, int lvl);
+};
+
  struct omap2_mcspi_platform_config {
        unsigned short  num_cs;
  };

drivers/spi/omap2_mcspi.c +9 -6

index 2a651e6..92ccbd6 100644
@@ -35,6 +35,7 @@
  #include <linux/slab.h>
 
  #include <linux/spi/spi.h>
+#include <linux/gpio.h>
 
  #include <plat/dma.h>
  #include <plat/clock.h>

@@ -235,11 +236,14 @@ static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 
  static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
  {
-       u32 l;
-
-       l = mcspi_cached_chconf0(spi);
-       MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
-       mcspi_write_chconf0(spi, l);
+       if (spi->controller_data) {
+               struct omap2_mcspi_csinfo *csinfo = spi->controller_data;
+               (*csinfo->set_level)(csinfo->line, cs_active);
+       } else {
+               u32 l = mcspi_cached_chconf0(spi);
+               MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
+               mcspi_write_chconf0(spi, l);
+       }
  }
 
  static void omap2_mcspi_set_master_mode(struct spi_master *master)
--

1.7.1

Quoted 10 lines · Ben Gamari

This mechanism is in large part stolen from the s3c64xx-spi module. To use this functionality, one simply must define a set_level function to set the CS state and a omap2_mcspi_csinfo struct for each chip select in the board file.

Each spi_board_info.controller_data should then be set
to point to the appropriate csinfo struct. This will cause the driver to call the csinfo->set_level function instead of toggling the McSPI chip select lines.

Quoted 1 line

Signed-off-by Ben Gamari <[email protected]>

I'd rather see the spi driver modified to use the gpio api directly. The drivers are already tending in that direction and it doesn't require machine specific set_level functions to be defined.

Quoted 13 lines · Grant Likely

Quoted 11 lines · Ben Gamari

This mechanism is in large part stolen from the s3c64xx-spi module. To use this functionality, one simply must define a set_level function to set the CS state and a omap2_mcspi_csinfo struct for each chip select in the board file.

Each spi_board_info.controller_data should then be set
to point to the appropriate csinfo struct. This will cause the driver to call the csinfo->set_level function instead of toggling the McSPI chip select lines.

Signed-off-by Ben Gamari <[email protected]>

Quoted 4 lines

I'd rather see the spi driver modified to use the gpio api directly. The drivers are already tending in that direction and it doesn't require machine specific set_level functions to be defined.

The reason I left this up to the board is it's easy to foresee cases where you want a non-trivial mapping between logical CS numbers and CS pin states. In my case, I using a 2-to-4 multiplexer as the source of chip select.

Quoted 4 lines · Ben Gamari

The reason I left this up to the board is it's easy to foresee cases where you want a non-trivial mapping between logical CS numbers and CS pin states. In my case, I using a 2-to-4 multiplexer as the source of chip select.

Hi Ben,

I understand and appreciate the motivation. However in practice, the gpio api is sufficient for pretty much any use case, even when the backing gpio controller driver ends up driving some oddball device with different constraints. The big downside to using a callback is that it forces all users to do the extra work of implementing the callback. With the gpio api, only the oddball cases have to do extra code (to adapt the custom device to the gpio api).

Quoted 8 lines · Grant Likely

Quoted 4 lines · Ben Gamari

The reason I left this up to the board is it's easy to foresee cases where you want a non-trivial mapping between logical CS numbers and CS pin states. In my case, I using a 2-to-4 multiplexer as the source of chip select.

Hi Ben,

Quoted 7 lines

I understand and appreciate the motivation. However in practice, the gpio api is sufficient for pretty much any use case, even when the backing gpio controller driver ends up driving some oddball device with different constraints. The big downside to using a callback is that it forces all users to do the extra work of implementing the callback. With the gpio api, only the oddball cases have to do extra code (to adapt the custom device to the gpio api).

I understand your concerns, but I'm not sure how to satisfy them without crippling the design's ability to accomodate my use-case. I can't pass a GPIO line per spi_board_info since in my case of a multiplexed CS configuration a single pin's state does not uniquely determine the desired CS. The only other option I can think of is that we somehow provide a list of GPIOs for each bus and map the CS numbers to permutations of GPIO states. Unfortunately, I don't know of any suitable structure to put this GPIO list in. Perhaps I'm missing something obvious?

Quoted 8 lines · Ben Gamari

I understand your concerns, but I'm not sure how to satisfy them without crippling the design's ability to accomodate my use-case. I can't pass a GPIO line per spi_board_info since in my case of a multiplexed CS configuration a single pin's state does not uniquely determine the desired CS. The only other option I can think of is that we somehow provide a list of GPIOs for each bus and map the CS numbers to permutations of GPIO states. Unfortunately, I don't know of any suitable structure to put this GPIO list in. Perhaps I'm missing something obvious?

Close, but not quite. Assign one gpio number to each cs state, and write a gpio controller driver that maps the linux-gpio number to the physical gpio state permutation. The mapping from gpio# to ss# is 1:1, but the driver behind the gpio# can do whatever you need it to do.

Quoted 10 lines · Grant Likely

Quoted 8 lines · Ben Gamari

I understand your concerns, but I'm not sure how to satisfy them without crippling the design's ability to accomodate my use-case. I can't pass a GPIO line per spi_board_info since in my case of a multiplexed CS configuration a single pin's state does not uniquely determine the desired CS. The only other option I can think of is that we somehow provide a list of GPIOs for each bus and map the CS numbers to permutations of GPIO states. Unfortunately, I don't know of any suitable structure to put this GPIO list in. Perhaps I'm missing something obvious?

Quoted 6 lines

Close, but not quite. Assign one gpio number to each cs state, and write a gpio controller driver that maps the linux-gpio number to the physical gpio state permutation. The mapping from gpio# to ss# is 1:1, but the driver behind the gpio# can do whatever you need it to do.

I see. I'm still not convinced that this is the route to take, however. It seems like this virtual gpio interface is not only pretty clunky (simple board file glue turns into an entire gpio chip driver), it seems like this is a very inaccurate and not very useful way to expose a multiplexed CS configuration; e.g. what is this chip driver to do if the user tries to set two CS pins at once?

Is there precedent for
using the GPIO subsystem in this way?

(Sorry for the really laggy reply)

I don't see it being that big a deal. gpio drivers are pretty lightweight and it is fine to have domain-specific limitations on how gpios for a particular "gpio controller" behave. In your example, if the hardware doesn't support enabling 2 CS pins at once, then you make a choice, either setting one when the other is already set simply does not work; or it could reset the other state. Either choice would be fine. The SPI driver must do the right thing regardless and deselect the previous CS line before enabling a new one.

The other alternative would be to implement a new SPI chipselect common infrastructure, but IMO, that would just end up looking like a duplication of the gpio infrastructure.

Hey all!

Recently I've been thinking about adding support to the McSPI driver for using GPIO pins as chip selects. As a starting point, I've browsed the driver source trying to identify what changes would be necessary to add this support. It seems like the rough idea is,

a) add a cs_gpio field to the device struct (omap2_mcspi)
b) modify omap2_mcspi_force_cs() to use cs_gpio instead of the CHxCONF[FORCE] bit if cs_gpio is valid

Unfortunately, I'm having a bit of difficulty seeing how the existing configuration works. In master mode, it seems that the controller is configured in single forced channel mode (MCSPI_MODULECTRL_SINGLE). As far as I can tell, this means that the driver is responsible for managing the chip selects through the MCSPI_CHxCONF[FORCE] bits. It seems that this is ideal as little will need to be changed to incorporate GPIO CS support.

Nevertheless, the timing of the various operations isn't making sense to me. As far as I understand it, the callgraph is as follows,

omap2_mcspi_work():
loop over messages
omap2_mcspi_set_enable(1)
loop over transfers:

     configure bus parameters
     if (!cs_active) cs = 1
     if (dma):
       omap2_mcspi_txrx_dma()
     else:
       omap2_mcspi_txrx_pio()
     if (cs_change) cs = 0

end loop

if (cs_active) cs = 0
omap2_mcspi_set_enable(0)
end loop

It seems that omap2_mcspi_set_enable() is called to enable the channel (MCSPI_CHCTRLx[EN] is set) before force_cs() is called. If I'm interpreting the hardware documentation correctly, the enable bit (among other things) starts the SPI clock, meaning that the chip will begin clocking out zeros to the device before CS is brought high. Furthermore, even after CS is brought high, it seems there could be a fair amount of time before the chip begins actually clocking out valid data.

As I am writing this, it now occurs to me that perhaps the chip doesn't start SPI_CLK until it has data to send. It seems that if this were the case my concerns would be resolved. However, it is not at all clear that this is the case from the documentation. When exactly does the controller start the bus clock? Is this stated explicitly anywhere in the documentation?

Any input you could offer would be greatly appreciated. Thanks for your time.

- Ben

P.S. The more and more I think about it, it seems like my hypothesis is the only logical behavior. It would be great if someone could confirm my suspicions, however. It really seems like this should be in the documentation either way.

P.P.S. I apologize if this is something someone familiar with SPI should just know. My knowledge is a little spotty on this sort of thing. --
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---
 arch/arm/mach-omap2/board-omap3beagle.c |    4 ++--
 arch/arm/mach-omap2/devices.c           |   15 +++++++++++++++
 2 files changed, 17 insertions(+), 2 deletions(-)

arch/arm/mach-omap2/board-omap3beagle.c +2 -2

index 67999da..481c1a9 100644
@@ -661,8 +661,8 @@ static struct spi_board_info
 beagledaq_mcspi_board_info[] = {
       },
 };
 
-static int mcspi3_cs_gpios[4];
-static int mcspi4_cs_gpios[4];
+int mcspi3_cs_gpios[4];
+int mcspi4_cs_gpios[4];
 
 static void __init beagledaq_init(void)

{

arch/arm/mach-omap2/devices.c +15 -0

index 5b8ca68..6808251 100644
@@ -341,6 +341,9 @@ struct omap_device_pm_latency omap_mcspi_latency[] = {
       },
 };
 
+extern int mcspi3_cs_gpios[4];
+extern int mcspi4_cs_gpios[4];
+
 static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
 {
       struct omap_device *od;

@@ -369,6 +372,18 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void
 *unused)
                       return -EINVAL;
       }
 
+       /* HACK: Not enough time to figure out how to export cs_gpios from
+        * board file to driver correctly */
+       if (spi_num == 2) {
+               // Setup McSPI3 cs_gpios
+               pdata->num_cs = 4;
+               pdata->cs_gpios = mcspi3_cs_gpios;
+       } else if (spi_num == 3) {
+               // Setup McSPI4 cs_gpios
+               pdata->num_cs = 4;
+               pdata->cs_gpios = mcspi4_cs_gpios;
+       }
+
       spi_num++;
       od = omap_device_build(name, spi_num, oh, pdata,

sizeof(*pdata), omap_mcspi_latency,
--
1.7.4.1