OMAP3: Avoid re-write to PRM_CLKSRC_CTRL
PATCH v2 1/1 OMAP3: Avoid re-write to PRM_CLKSRC_CTRL
The function get_osc_clk_speed() is used to determine the master clock. If SYS_CLK is being divided by 2, the divider is changed to 1 - without following any sequence.
Before reaching this function, some of the clocks have already been set (by x-loader or equiv) OR power-on defaults are in use. This change is too sudden, leading to instability beyond certain tolerance zone.
The problem was observed with DM3730 (silimar to OMAP3630), on the OMAP3EVM.
This patch removes the step to change clock divider. Instead, uses a multiplication factor (if needed). Mathematically, the formula is unchanged.
Tested on OMAP3EVM with OMAP3530 and DM3730.
--- cpu/arm_cortexa8/omap3/clock.c | 15 +++++++++++---- 1 files changed, 11 insertions(+), 4 deletions(-)
cpu/arm_cortexa8/omap3/clock.c +11 -4
@@ -40,7 +40,7 @@*****************************************************************************/ u32 get_osc_clk_speed (void ) { -u32 start, cstart, cend, cdiff, val; +u32 start, cstart, cend, cdiff, cdiv, val;struct prcm *prcm_base = (struct prcm *)PRCM_BASE ;struct prm *prm_base = (struct prm *)PRM_BASE ;struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1 ;
@@ -48,9 +48,13 @@ u32 get_osc_clk_speed(void) val =readl (&prm_base->clksrc_ctrl); -/* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~SYSCLKDIV_2 )) |SYSCLKDIV_1 ; -writel (val, &prm_base->clksrc_ctrl); +if (val &SYSCLKDIV_2 ) + cdiv =2 ; +else if (val &SYSCLKDIV_1 ) + cdiv =1 ; +else +/*Should never reach here! (Assume divider as 1) */ + cdiv =1 ;/* enable timer2 */ val =readl (&prcm_base->clksel_wkup) |CLKSEL_GPT1 ;
@@ -83,6 +87,9 @@ u32 get_osc_clk_speed(void) cend =readl (&gpt1_base->tcrr);/* get end sys_clk count */ cdiff = cend - cstart;/* get elapsed ticks */ +if (cdiv ==2 ) + cdiff *=2 ; +/* based on number of ticks assign speed */ if (cdiff >19000 )return S38_4M ;
Signature · 1 line
1.6.2.2
Premi
PATCH v2 1/1 OMAP3: Avoid re-write to PRM_CLKSRC_CTRL
Quoted 79 lines
-----Original Message-----
From: Premi, Sanjeev
Sent: Friday, January 29, 2010 6:44 PM
To: u-boot at lists.denx.de
Cc: Premi, Sanjeev; Hiremath, Vaibhav
Subject: [PATCHv2] OMAP3: Avoid re-write toPRM_CLKSRC_CTRLThe function
get_osc_clk_speed()is used to determine the master clock. IfSYS_CLKis being divided by 2, the divider is changed to 1 - without following any sequence.Before reaching this function, some of the clocks have already been set (by x-loader or equiv) OR power-on defaults are in use. This change is too sudden, leading to instability beyond certain tolerance zone.
The problem was observed with DM3730 (silimar to OMAP3630), on the OMAP3EVM.
This patch removes the step to change clock divider. Instead, uses a multiplication factor (if needed). Mathematically, the formula is unchanged.
Tested on OMAP3EVM with OMAP3530 and DM3730.
Signed-off-by Sanjeev Premi <[email protected]>Signed-off-by Hiremath Vaibhav <[email protected]>--- cpu/arm_cortexa8/omap3/clock.c | 15 +++++++++++---- 1 files changed, 11 insertions(+), 4 deletions(-)cpu/arm_cortexa8/omap3/clock.c +1
-1@@ -40,7 +40,7 @@************************************************************** ***************/ u32 get_osc_clk_speed (void ) { -u32 start, cstart, cend, cdiff, val; +u32 start, cstart, cend, cdiff, cdiv, val;struct prcm *prcm_base = (struct prcm *)PRCM_BASE ;cpu/arm_cortexa8/omap3/clock.c +7
-3struct prm *prm_base = (struct prm *)PRM_BASE ;struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1 ;@@ -48,9 +48,13 @@ u32 get_osc_clk_speed(void) val =readl (&prm_base->clksrc_ctrl); -/* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~SYSCLKDIV_2 )) |SYSCLKDIV_1 ; -writel (val, &prm_base->clksrc_ctrl); +if (val &SYSCLKDIV_2 ) + cdiv =2 ; +else if (val &SYSCLKDIV_1 ) + cdiv =1 ; +else +/*Should never reach here! (Assume divider as 1) */ + cdiv =1 ;/* enable timer2 */ val =readl (&prcm_base->clksel_wkup) |CLKSEL_GPT1 ;@@ -83,6 +87,9 @@ u32 get_osc_clk_speed(void) cend =readl (&gpt1_base->tcrr);/* get end
sys_clkcount */cpu/arm_cortexa8/omap3/clock.c +3
-0cdiff = cend - cstart;/* get elapsed ticks */ +if (cdiv ==2 ) + cdiff *=2 ; +/* based on number of ticks assign speed */ if (cdiff >19000 )return S38_4M ;Signature · 1 line
1.6.2.2
Tom, Sandeep,
Just wanted to check the status of this patch.
Best regards,
Sanjeev
PATCH v2 1/1 OMAP3: Avoid re-write to PRM_CLKSRC_CTRL
Quoted 82 lines · Sanjeev
Quoted 79 lines
-----Original Message-----
From: Premi, Sanjeev
Sent: Friday, January 29, 2010 6:44 PM
To: u-boot at lists.denx.de
Cc: Premi, Sanjeev; Hiremath, Vaibhav
Subject: [PATCHv2] OMAP3: Avoid re-write toPRM_CLKSRC_CTRLThe function
get_osc_clk_speed()is used to determine the master clock. IfSYS_CLKis being divided by 2, the divider is changed to 1 - without following any sequence.Before reaching this function, some of the clocks have already been set (by x-loader or equiv) OR power-on defaults are in use. This change is too sudden, leading to instability beyond certain tolerance zone.
The problem was observed with DM3730 (silimar to OMAP3630), on the OMAP3EVM.
This patch removes the step to change clock divider. Instead, uses a multiplication factor (if needed). Mathematically, the formula is unchanged.
Tested on OMAP3EVM with OMAP3530 and DM3730.
Signed-off-by Sanjeev Premi <[email protected]>Signed-off-by Hiremath Vaibhav <[email protected]>--- cpu/arm_cortexa8/omap3/clock.c | 15 +++++++++++---- 1 files changed, 11 insertions(+), 4 deletions(-)cpu/arm_cortexa8/omap3/clock.c +1
-1@@ -40,7 +40,7 @@************************************************************** ***************/ u32 get_osc_clk_speed (void ) { -u32 start, cstart, cend, cdiff, val; +u32 start, cstart, cend, cdiff, cdiv, val;struct prcm *prcm_base = (struct prcm *)PRCM_BASE ;cpu/arm_cortexa8/omap3/clock.c +7
-3struct prm *prm_base = (struct prm *)PRM_BASE ;struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1 ;@@ -48,9 +48,13 @@ u32 get_osc_clk_speed(void) val =readl (&prm_base->clksrc_ctrl); -/* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~SYSCLKDIV_2 )) |SYSCLKDIV_1 ; -writel (val, &prm_base->clksrc_ctrl); +if (val &SYSCLKDIV_2 ) + cdiv =2 ; +else if (val &SYSCLKDIV_1 ) + cdiv =1 ; +else +/*Should never reach here! (Assume divider as 1) */ + cdiv =1 ;/* enable timer2 */ val =readl (&prcm_base->clksel_wkup) |CLKSEL_GPT1 ;@@ -83,6 +87,9 @@ u32 get_osc_clk_speed(void) cend =readl (&gpt1_base->tcrr);/* get end
sys_clkcount */cpu/arm_cortexa8/omap3/clock.c +3
-0cdiff = cend - cstart;/* get elapsed ticks */ +if (cdiv ==2 ) + cdiff *=2 ; +/* based on number of ticks assign speed */ if (cdiff >19000 )return S38_4M ;Signature · 1 line
1.6.2.2Tom, Sandeep,
Quoted 2 lines
Just wanted to check the status of this patch.
I need to review and test it..
This will happen over the weekend.
Quoted 6 lines
Best regards,
Sanjeev
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PATCH v2 1/1 OMAP3: Avoid re-write to PRM_CLKSRC_CTRL
In reply to PremiQuoted 82 lines · Sanjeev
Quoted 79 lines
-----Original Message-----
From: Premi, Sanjeev
Sent: Friday, January 29, 2010 6:44 PM
To: u-boot at lists.denx.de
Cc: Premi, Sanjeev; Hiremath, Vaibhav
Subject: [PATCHv2] OMAP3: Avoid re-write toPRM_CLKSRC_CTRLThe function
get_osc_clk_speed()is used to determine the master clock. IfSYS_CLKis being divided by 2, the divider is changed to 1 - without following any sequence.Before reaching this function, some of the clocks have already been set (by x-loader or equiv) OR power-on defaults are in use. This change is too sudden, leading to instability beyond certain tolerance zone.
The problem was observed with DM3730 (silimar to OMAP3630), on the OMAP3EVM.
This patch removes the step to change clock divider. Instead, uses a multiplication factor (if needed). Mathematically, the formula is unchanged.
Tested on OMAP3EVM with OMAP3530 and DM3730.
Signed-off-by Sanjeev Premi <[email protected]>Signed-off-by Hiremath Vaibhav <[email protected]>--- cpu/arm_cortexa8/omap3/clock.c | 15 +++++++++++---- 1 files changed, 11 insertions(+), 4 deletions(-)cpu/arm_cortexa8/omap3/clock.c +1
-1@@ -40,7 +40,7 @@************************************************************** ***************/ u32 get_osc_clk_speed (void ) { -u32 start, cstart, cend, cdiff, val; +u32 start, cstart, cend, cdiff, cdiv, val;struct prcm *prcm_base = (struct prcm *)PRCM_BASE ;cpu/arm_cortexa8/omap3/clock.c +7
-3struct prm *prm_base = (struct prm *)PRM_BASE ;struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1 ;@@ -48,9 +48,13 @@ u32 get_osc_clk_speed(void) val =readl (&prm_base->clksrc_ctrl); -/* If SYS_CLK is being divided by 2, remove for now */ - val = (val & (~SYSCLKDIV_2 )) |SYSCLKDIV_1 ; -writel (val, &prm_base->clksrc_ctrl); +if (val &SYSCLKDIV_2 ) + cdiv =2 ; +else if (val &SYSCLKDIV_1 ) + cdiv =1 ; +else +/*Should never reach here! (Assume divider as 1) */ + cdiv =1 ;/* enable timer2 */ val =readl (&prcm_base->clksel_wkup) |CLKSEL_GPT1 ;@@ -83,6 +87,9 @@ u32 get_osc_clk_speed(void) cend =readl (&gpt1_base->tcrr);/* get end
sys_clkcount */cpu/arm_cortexa8/omap3/clock.c +3
-0cdiff = cend - cstart;/* get elapsed ticks */ +if (cdiv ==2 ) + cdiff *=2 ; +/* based on number of ticks assign speed */ if (cdiff >19000 )return S38_4M ;Signature · 1 line
1.6.2.2Tom, Sandeep,
Quoted 2 lines
Just wanted to check the status of this patch.
Ack-ed
This looks fine.
Thanks
Tom
Quoted 6 lines
Best regards,
Sanjeev
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