OMAP: GPIO: Split OMAP1 and OMAP2PLUS

index e737706..c4945d7 100644
@@ -3,3 +3,91 @@
  */
 
 #include <plat/gpio.h>
+
+/*
+ * OMAP1510 GPIO registers
+ */
+#define OMAP1510_GPIO_BASE		0xfffce000
+#define OMAP1510_GPIO_DATA_INPUT	0x00
+#define OMAP1510_GPIO_DATA_OUTPUT	0x04
+#define OMAP1510_GPIO_DIR_CONTROL	0x08
+#define OMAP1510_GPIO_INT_CONTROL	0x0c
+#define OMAP1510_GPIO_INT_MASK		0x10
+#define OMAP1510_GPIO_INT_STATUS	0x14
+#define OMAP1510_GPIO_PIN_CONTROL	0x18
+
+#define OMAP1510_IH_GPIO_BASE		64
+
+/*
+ * OMAP1610 specific GPIO registers
+ */
+#define OMAP1610_GPIO1_BASE		0xfffbe400
+#define OMAP1610_GPIO2_BASE		0xfffbec00
+#define OMAP1610_GPIO3_BASE		0xfffbb400
+#define OMAP1610_GPIO4_BASE		0xfffbbc00
+#define OMAP1610_GPIO_REVISION		0x0000
+#define OMAP1610_GPIO_SYSCONFIG		0x0010
+#define OMAP1610_GPIO_SYSSTATUS		0x0014
+#define OMAP1610_GPIO_IRQSTATUS1	0x0018
+#define OMAP1610_GPIO_IRQENABLE1	0x001c
+#define OMAP1610_GPIO_WAKEUPENABLE	0x0028
+#define OMAP1610_GPIO_DATAIN		0x002c
+#define OMAP1610_GPIO_DATAOUT		0x0030
+#define OMAP1610_GPIO_DIRECTION		0x0034
+#define OMAP1610_GPIO_EDGE_CTRL1	0x0038
+#define OMAP1610_GPIO_EDGE_CTRL2	0x003c
+#define OMAP1610_GPIO_CLEAR_IRQENABLE1	0x009c
+#define OMAP1610_GPIO_CLEAR_WAKEUPENA	0x00a8
+#define OMAP1610_GPIO_CLEAR_DATAOUT	0x00b0
+#define OMAP1610_GPIO_SET_IRQENABLE1	0x00dc
+#define OMAP1610_GPIO_SET_WAKEUPENA	0x00e8
+#define OMAP1610_GPIO_SET_DATAOUT	0x00f0
+
+/*
+ * OMAP7XX specific GPIO registers
+ */
+#define OMAP7XX_GPIO1_BASE		0xfffbc000
+#define OMAP7XX_GPIO2_BASE		0xfffbc800
+#define OMAP7XX_GPIO3_BASE		0xfffbd000
+#define OMAP7XX_GPIO4_BASE		0xfffbd800
+#define OMAP7XX_GPIO5_BASE		0xfffbe000
+#define OMAP7XX_GPIO6_BASE		0xfffbe800
+#define OMAP7XX_GPIO_DATA_INPUT		0x00
+#define OMAP7XX_GPIO_DATA_OUTPUT	0x04
+#define OMAP7XX_GPIO_DIR_CONTROL	0x08
+#define OMAP7XX_GPIO_INT_CONTROL	0x0c
+#define OMAP7XX_GPIO_INT_MASK		0x10
+#define OMAP7XX_GPIO_INT_STATUS		0x14
+
+#define OMAP1_MPUIO_VBASE		OMAP1_MPUIO_BASE
+#define OMAP1_MPUIO_BASE		0xfffb5000
+
+#if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850))
+#define OMAP_MPUIO_INPUT_LATCH		0x00
+#define OMAP_MPUIO_OUTPUT		0x02
+#define OMAP_MPUIO_IO_CNTL		0x04
+#define OMAP_MPUIO_KBR_LATCH		0x08
+#define OMAP_MPUIO_KBC			0x0a
+#define OMAP_MPUIO_GPIO_EVENT_MODE	0x0c
+#define OMAP_MPUIO_GPIO_INT_EDGE	0x0e
+#define OMAP_MPUIO_KBD_INT		0x10
+#define OMAP_MPUIO_GPIO_INT		0x12
+#define OMAP_MPUIO_KBD_MASKIT		0x14
+#define OMAP_MPUIO_GPIO_MASKIT		0x16
+#define OMAP_MPUIO_GPIO_DEBOUNCING	0x18
+#define OMAP_MPUIO_LATCH		0x1a
+#else
+#define OMAP_MPUIO_INPUT_LATCH		0x00
+#define OMAP_MPUIO_OUTPUT		0x04
+#define OMAP_MPUIO_IO_CNTL		0x08
+#define OMAP_MPUIO_KBR_LATCH		0x10
+#define OMAP_MPUIO_KBC			0x14
+#define OMAP_MPUIO_GPIO_EVENT_MODE	0x18
+#define OMAP_MPUIO_GPIO_INT_EDGE	0x1c
+#define OMAP_MPUIO_KBD_INT		0x20
+#define OMAP_MPUIO_GPIO_INT		0x24
+#define OMAP_MPUIO_KBD_MASKIT		0x28
+#define OMAP_MPUIO_GPIO_MASKIT		0x2c
+#define OMAP_MPUIO_GPIO_DEBOUNCING	0x30
+#define OMAP_MPUIO_LATCH		0x34
+#endif

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new file mode 100644
index 0000000..8f404e7
@@ -0,0 +1,351 @@
+/*
+ * gpio3xxx.c - OMAP3-specific gpio code
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Author:
+ *	Charulatha V <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/gpio.h>
+
+/*
+ * OMAP3 GPIO reg offsets
+ */
+static struct gpio_reg_offset omap3_gpio_reg = {
+	.data_in	= OMAP24XX_GPIO_DATAIN,
+	.data_out	= OMAP24XX_GPIO_DATAOUT,
+	.data_out_set	= OMAP24XX_GPIO_SETDATAOUT,
+	.data_out_clear	= OMAP24XX_GPIO_CLEARDATAOUT,
+	.dir_ctrl	= OMAP24XX_GPIO_OE,
+	.irq_status0	= OMAP24XX_GPIO_IRQSTATUS1,
+	.irq_status1	= OMAP24XX_GPIO_IRQSTATUS2,
+	.irq_mask	= OMAP24XX_GPIO_IRQENABLE1,
+	.irq_set	= OMAP24XX_GPIO_SETIRQENABLE1,
+	.irq_clear	= OMAP24XX_GPIO_CLEARIRQENABLE1,
+	.irq_mask_bits	= 0xffffffff,
+	.irq_inv	= 0,
+	.wkup_enable	= OMAP24XX_GPIO_WAKE_EN,
+	.wkup_clear	= OMAP24XX_GPIO_CLEARWKUENA,
+	.wkup_set	= OMAP24XX_GPIO_SETWKUENA,
+	.debounce_ena	= OMAP24XX_GPIO_DEBOUNCE_EN,
+	.debounce_val	= OMAP24XX_GPIO_DEBOUNCE_VAL,
+	.ctrl		= OMAP24XX_GPIO_CTRL,
+	.syscfg		= OMAP24XX_GPIO_SYSCONFIG,
+	.leveldetect0	= OMAP24XX_GPIO_LEVELDETECT0,
+	.leveldetect1	= OMAP24XX_GPIO_LEVELDETECT1,
+	.rise_detect	= OMAP24XX_GPIO_RISINGDETECT,
+	.fall_detect	= OMAP24XX_GPIO_FALLINGDETECT,
+	.rev_reg	= OMAP24XX_GPIO_REVISION,
+};
+
+/*
+ * OMAP3 GPIO1 interface data
+ */
+static struct __initdata resource omap3_gpio1_resources[] = {
+	{
+		.start	= OMAP34XX_GPIO1_BASE,
+		.end	= OMAP34XX_GPIO1_BASE + OMAP3_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_34XX_GPIO_BANK1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap3_gpio1_config = {
+	.ick_name = "gpio1_ick",
+	.dbck_name = "gpio1_dbck",
+	.virtual_irq_start = IH_GPIO_BASE,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap3_gpio1 = {
+	.name           = "omap-gpio",
+	.id             = 0,
+	.dev            = {
+		.platform_data = &omap3_gpio1_config,
+	},
+	.num_resources = ARRAY_SIZE(omap3_gpio1_resources),
+	.resource = omap3_gpio1_resources,
+};
+
+/*
+ * OMAP3 GPIO2 interface data
+ */
+static struct __initdata resource omap3_gpio2_resources[] = {
+	{
+		.start	= OMAP34XX_GPIO2_BASE,
+		.end	= OMAP34XX_GPIO2_BASE + OMAP3_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_34XX_GPIO_BANK2,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap3_gpio2_config = {
+	.ick_name = "gpio2_ick",
+	.dbck_name = "gpio2_dbck",
+	.virtual_irq_start = IH_GPIO_BASE + 32,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap3_gpio2 = {
+	.name           = "omap-gpio",
+	.id             = 1,
+	.dev            = {
+		.platform_data = &omap3_gpio2_config,
+	},
+	.num_resources = ARRAY_SIZE(omap3_gpio2_resources),
+	.resource = omap3_gpio2_resources,
+};
+
+/*
+ * OMAP3 GPIO3 interface data
+ */
+static struct __initdata resource omap3_gpio3_resources[] = {
+	{
+		.start	= OMAP34XX_GPIO3_BASE,
+		.end	= OMAP34XX_GPIO3_BASE + OMAP3_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_34XX_GPIO_BANK3,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap3_gpio3_config = {
+	.ick_name = "gpio3_ick",
+	.dbck_name = "gpio3_dbck",
+	.virtual_irq_start = IH_GPIO_BASE + 64,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap3_gpio3 = {
+	.name           = "omap-gpio",
+	.id             = 2,
+	.dev            = {
+		.platform_data = &omap3_gpio3_config,
+	},
+	.num_resources = ARRAY_SIZE(omap3_gpio3_resources),
+	.resource = omap3_gpio3_resources,
+};
+
+/*
+ * OMAP3 GPIO4 interface data
+ */
+static struct __initdata resource omap3_gpio4_resources[] = {
+	{
+		.start	= OMAP34XX_GPIO4_BASE,
+		.end	= OMAP34XX_GPIO4_BASE + OMAP3_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_34XX_GPIO_BANK4,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap3_gpio4_config = {
+	.ick_name = "gpio4_ick",
+	.dbck_name = "gpio4_dbck",
+	.virtual_irq_start = IH_GPIO_BASE + 96,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap3_gpio4 = {
+	.name           = "omap-gpio",
+	.id             = 3,
+	.dev            = {
+		.platform_data = &omap3_gpio4_config,
+	},
+	.num_resources = ARRAY_SIZE(omap3_gpio4_resources),
+	.resource = omap3_gpio4_resources,
+};
+
+/*
+ * OMAP3 GPIO5 interface data
+ */
+static struct __initdata resource omap3_gpio5_resources[] = {
+	{
+		.start	= OMAP34XX_GPIO5_BASE,
+		.end	= OMAP34XX_GPIO5_BASE + OMAP3_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_34XX_GPIO_BANK5,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap3_gpio5_config = {
+	.ick_name = "gpio5_ick",
+	.dbck_name = "gpio5_dbck",
+	.virtual_irq_start = IH_GPIO_BASE + 128,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap3_gpio5 = {
+	.name           = "omap-gpio",
+	.id             = 4,
+	.dev            = {
+		.platform_data = &omap3_gpio5_config,
+	},
+	.num_resources = ARRAY_SIZE(omap3_gpio5_resources),
+	.resource = omap3_gpio5_resources,
+};
+
+/*
+ * OMAP3 GPIO6 interface data
+ */
+static struct __initdata resource omap3_gpio6_resources[] = {
+	{
+		.start	= OMAP34XX_GPIO6_BASE,
+		.end	= OMAP34XX_GPIO6_BASE + OMAP3_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_34XX_GPIO_BANK6,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap3_gpio6_config = {
+	.ick_name = "gpio6_ick",
+	.dbck_name = "gpio6_dbck",
+	.virtual_irq_start = IH_GPIO_BASE + 160,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap3_gpio6 = {
+	.name           = "omap-gpio",
+	.id             = 5,
+	.dev            = {
+		.platform_data = &omap3_gpio6_config,
+	},
+	.num_resources = ARRAY_SIZE(omap3_gpio6_resources),
+	.resource = omap3_gpio6_resources,
+};
+
+static struct __initdata platform_device * omap3_gpio_early_dev[] = {
+	&omap3_gpio1,
+	&omap3_gpio2,
+	&omap3_gpio3,
+	&omap3_gpio4,
+	&omap3_gpio5,
+	&omap3_gpio6
+};
+
+static struct gpio_bank *omap3_get_gpio_bank(int gpio,
+				struct gpio_bank *gpio_bank)
+{
+	if (cpu_is_omap34xx())
+		return &gpio_bank[gpio >> 5];
+	BUG();
+	return NULL;
+}
+
+static int set_omap3_gpio_triggering(struct gpio_bank *bank, int gpio,
+						int trigger)
+{
+	void __iomem *base = bank->base;
+	u32 gpio_bit = 1 << gpio;
+
+	if (!cpu_is_omap34xx())
+		return -EINVAL;
+
+	MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
+				trigger & IRQ_TYPE_LEVEL_LOW);
+	MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
+				trigger & IRQ_TYPE_LEVEL_HIGH);
+	MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
+				trigger & IRQ_TYPE_EDGE_RISING);
+	MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
+				trigger & IRQ_TYPE_EDGE_FALLING);
+	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
+		if (trigger != 0)
+			__raw_writel(1 << gpio, bank->base
+					+ OMAP24XX_GPIO_SETWKUENA);
+		else
+			__raw_writel(1 << gpio, bank->base
+					+ OMAP24XX_GPIO_CLEARWKUENA);
+	} else {
+		if (trigger != 0)
+			bank->enabled_non_wakeup_gpios |= gpio_bit;
+		else
+			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
+	}
+
+	bank->level_mask =
+			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
+			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+
+	return 0;
+}
+
+void __init omap3_gpio_mod_init(struct gpio_bank *bank, int i)
+{
+	static const u32 non_wakeup_gpios[] = {
+		0xe203ffc0, 0x08700040
+	};
+
+	/*
+	 * Initialize interface clock ungated,
+	 * module enabled
+	 */
+	__raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
+	__raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
+	__raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
+	__raw_writew(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
+	__raw_writew(0x0, bank->base + OMAP24XX_GPIO_CTRL);
+
+	if (i < ARRAY_SIZE(non_wakeup_gpios))
+		bank->non_wakeup_gpios = non_wakeup_gpios[i];
+}
+
+/*
+ * OMAP3 GPIO function pointers, reg offsets pointer and other info
+ */
+static struct omap_gpio_info omap3_gpio_data = {
+	.reg_off		= &omap3_gpio_reg,
+	.index_mask		= 0x1f,
+	.no_of_gpio		= 192,
+	.bank_count		= OMAP34XX_NR_GPIOS,
+	.bank_bits		= 32,
+	.get_gpio_bank		= omap3_get_gpio_bank,
+	.gpio_mod_init		= omap3_gpio_mod_init,
+	.set_gpio_triggering	= set_omap3_gpio_triggering,
+};
+
+void __init omap3_gpio_init_data(void)
+{
+	gpio_init(&omap3_gpio_data);
+}
+
+int __init omap3_early_init_gpio(struct platform_device ***pdev)
+{
+	*pdev = omap3_gpio_early_dev;
+	return OMAP34XX_NR_GPIOS;
+}
+
+int __init omap3_gpio_dev_reg(void)
+{
+	if (cpu_is_omap34xx()) {
+		platform_device_register(&omap3_gpio1);
+		platform_device_register(&omap3_gpio2);
+		platform_device_register(&omap3_gpio3);
+		platform_device_register(&omap3_gpio4);
+		platform_device_register(&omap3_gpio5);
+		platform_device_register(&omap3_gpio6);
+	}
+	return 0;
+}
+arch_initcall(omap3_gpio_dev_reg);

index 0b90a72..07bfa0f 100644
@@ -1,6 +1,8 @@
 /*
  * arch/arm/mach-omap2/include/mach/gpio.h
  */
+#ifndef __ASM_ARCH_OMAP2PLUS_GPIO_H
+#define __ASM_ARCH_OMAP2PLUS_GPIO_H
 
 #include <plat/gpio.h>
 

@@ -18,6 +20,8 @@
 #define OMAP243X_GPIO4_BASE		0x49012000
 #define OMAP243X_GPIO5_BASE		0x480B6000
 
+#define OMAP2_GPIO_AS_LEN		4096
+
 /*
  * omap34xx specific GPIO registers
  */

@@ -29,7 +33,7 @@
 #define OMAP34XX_GPIO6_BASE		0x49058000
 
 #define OMAP34XX_NR_GPIOS		6
-
+#define OMAP3_GPIO_AS_LEN		4096
 /*
  * OMAP44XX  specific GPIO registers
  */

@@ -40,6 +44,9 @@
 #define OMAP44XX_GPIO5_BASE             0x4805B000
 #define OMAP44XX_GPIO6_BASE             0x4805D000
 
+#define OMAP4_GPIO_AS_LEN		4096
+#define OMAP4_NR_GPIOS			6
+
 /*
  * GPIO register offsets
  */

@@ -102,3 +109,7 @@
 #define OMAP4_GPIO_SETWKUENA		0x0184
 #define OMAP4_GPIO_CLEARDATAOUT		0x0190
 #define OMAP4_GPIO_SETDATAOUT		0x0194
+
+extern void omap3_gpio_init_data(void);
+extern int omap3_early_init_gpio(struct platform_device ***pdev);
+#endif

new file mode 100644
index 0000000..830bb55
@@ -0,0 +1,472 @@
+/*
+ * gpio2xxx.c - OMAP2-specific gpio code
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Author:
+ *	Charulatha V <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/gpio.h>
+
+/*
+ * OMAP24XX GPIO reg offsets
+ */
+static struct gpio_reg_offset omap2_gpio_reg = {
+	.data_in	= OMAP24XX_GPIO_DATAIN,
+	.data_out	= OMAP24XX_GPIO_DATAOUT,
+	.data_out_set	= OMAP24XX_GPIO_SETDATAOUT,
+	.data_out_clear	= OMAP24XX_GPIO_CLEARDATAOUT,
+	.dir_ctrl	= OMAP24XX_GPIO_OE,
+	.irq_status0	= OMAP24XX_GPIO_IRQSTATUS1,
+	.irq_status1	= OMAP24XX_GPIO_IRQSTATUS2,
+	.irq_mask	= OMAP24XX_GPIO_IRQENABLE1,
+	.irq_ena2	= OMAP24XX_GPIO_IRQENABLE2,
+	.irq_set	= OMAP24XX_GPIO_SETIRQENABLE1,
+	.irq_clear	= OMAP24XX_GPIO_CLEARIRQENABLE1,
+	.irq_mask_bits	= 0xffffffff,
+	.irq_inv	= 0,
+	.wkup_enable	= OMAP24XX_GPIO_WAKE_EN,
+	.wkup_clear	= OMAP24XX_GPIO_CLEARWKUENA,
+	.wkup_set	= OMAP24XX_GPIO_SETWKUENA,
+	.debounce_ena	= OMAP24XX_GPIO_DEBOUNCE_EN,
+	.debounce_val	= OMAP24XX_GPIO_DEBOUNCE_VAL,
+	.ctrl		= OMAP24XX_GPIO_CTRL,
+	.syscfg		= OMAP24XX_GPIO_SYSCONFIG,
+	.leveldetect0	= OMAP24XX_GPIO_LEVELDETECT0,
+	.leveldetect1	= OMAP24XX_GPIO_LEVELDETECT1,
+	.rise_detect	= OMAP24XX_GPIO_RISINGDETECT,
+	.fall_detect	= OMAP24XX_GPIO_FALLINGDETECT,
+	.rev_reg	= OMAP24XX_GPIO_REVISION,
+};
+
+/*
+ * OMAP242X GPIO1 interface data
+ */
+static struct __initdata resource omap242x_gpio1_resources[] = {
+	{
+		.start	= OMAP242X_GPIO1_BASE,
+		.end	= OMAP242X_GPIO1_BASE + OMAP2_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_24XX_GPIO_BANK1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap242x_gpio1_config = {
+	.ick_name = "gpios_ick",
+	.fck_name = "gpios_fck",
+	.virtual_irq_start = IH_GPIO_BASE,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap242x_gpio1 = {
+	.name           = "omap-gpio",
+	.id             = 0,
+	.dev            = {
+		.platform_data = &omap242x_gpio1_config,
+	},
+	.num_resources = ARRAY_SIZE(omap242x_gpio1_resources),
+	.resource = omap242x_gpio1_resources,
+};
+
+/*
+ * OMAP242X GPIO2 interface data
+ */
+static struct __initdata resource omap242x_gpio2_resources[] = {
+	{
+		.start	= OMAP242X_GPIO2_BASE,
+		.end	= OMAP242X_GPIO2_BASE + OMAP2_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_24XX_GPIO_BANK2,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap242x_gpio2_config = {
+	.ick_name = "gpios_ick",
+	.fck_name = "gpios_fck",
+	.virtual_irq_start = IH_GPIO_BASE + 32,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap242x_gpio2 = {
+	.name           = "omap-gpio",
+	.id             = 1,
+	.dev            = {
+		.platform_data = &omap242x_gpio2_config,
+	},
+	.num_resources = ARRAY_SIZE(omap242x_gpio2_resources),
+	.resource = omap242x_gpio2_resources,
+};
+
+/*
+ * OMAP242X GPIO3 interface data
+ */
+static struct __initdata resource omap242x_gpio3_resources[] = {
+	{
+		.start	= OMAP242X_GPIO3_BASE,
+		.end	= OMAP242X_GPIO3_BASE + OMAP2_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_24XX_GPIO_BANK3,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap242x_gpio3_config = {
+	.ick_name = "gpios_ick",
+	.fck_name = "gpios_fck",
+	.virtual_irq_start = IH_GPIO_BASE + 64,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap242x_gpio3 = {
+	.name           = "omap-gpio",
+	.id             = 2,
+	.dev            = {
+		.platform_data = &omap242x_gpio3_config,
+	},
+	.num_resources = ARRAY_SIZE(omap242x_gpio3_resources),
+	.resource = omap242x_gpio3_resources,
+};
+
+/*
+ * OMAP242X GPIO4 interface data
+ */
+static struct __initdata resource omap242x_gpio4_resources[] = {
+	{
+		.start	= OMAP242X_GPIO4_BASE,
+		.end	= OMAP242X_GPIO4_BASE + OMAP2_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_24XX_GPIO_BANK4,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap242x_gpio4_config = {
+	.ick_name = "gpios_ick",
+	.fck_name = "gpios_fck",
+	.virtual_irq_start = IH_GPIO_BASE + 96,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap242x_gpio4 = {
+	.name           = "omap-gpio",
+	.id             = 3,
+	.dev            = {
+		.platform_data = &omap242x_gpio4_config,
+	},
+	.num_resources = ARRAY_SIZE(omap242x_gpio4_resources),
+	.resource = omap242x_gpio4_resources,
+};
+
+/*
+ * OMAP243X GPIO1 interface data
+ */
+static struct __initdata resource omap243x_gpio1_resources[] = {
+	{
+		.start	= OMAP243X_GPIO1_BASE,
+		.end	= OMAP243X_GPIO1_BASE + OMAP2_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_24XX_GPIO_BANK1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap243x_gpio1_config = {
+	.ick_name = "gpios_ick",
+	.fck_name = "gpios_fck",
+	.virtual_irq_start = IH_GPIO_BASE,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap243x_gpio1 = {
+	.name           = "omap-gpio",
+	.id             = 0,
+	.dev            = {
+		.platform_data = &omap243x_gpio1_config,
+	},
+	.num_resources = ARRAY_SIZE(omap243x_gpio1_resources),
+	.resource = omap243x_gpio1_resources,
+};
+
+/*
+ * OMAP243X GPIO2 interface data
+ */
+static struct __initdata resource omap243x_gpio2_resources[] = {
+	{
+		.start	= OMAP243X_GPIO2_BASE,
+		.end	= OMAP243X_GPIO2_BASE + OMAP2_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_24XX_GPIO_BANK2,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap243x_gpio2_config = {
+	.ick_name = "gpios_ick",
+	.fck_name = "gpios_fck",
+	.virtual_irq_start = IH_GPIO_BASE + 32,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap243x_gpio2 = {
+	.name           = "omap-gpio",
+	.id             = 1,
+	.dev            = {
+		.platform_data = &omap243x_gpio2_config,
+	},
+	.num_resources = ARRAY_SIZE(omap243x_gpio2_resources),
+	.resource = omap243x_gpio2_resources,
+};
+
+/*
+ * OMAP243X GPIO3 interface data
+ */
+static struct __initdata resource omap243x_gpio3_resources[] = {
+	{
+		.start	= OMAP243X_GPIO3_BASE,
+		.end	= OMAP243X_GPIO3_BASE + OMAP2_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_24XX_GPIO_BANK3,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap243x_gpio3_config = {
+	.ick_name = "gpios_ick",
+	.fck_name = "gpios_fck",
+	.virtual_irq_start = IH_GPIO_BASE + 64,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap243x_gpio3 = {
+	.name           = "omap-gpio",
+	.id             = 2,
+	.dev            = {
+		.platform_data = &omap243x_gpio3_config,
+	},
+	.num_resources = ARRAY_SIZE(omap243x_gpio3_resources),
+	.resource = omap243x_gpio3_resources,
+};
+
+/*
+ * OMAP243X GPIO4 interface data
+ */
+static struct __initdata resource omap243x_gpio4_resources[] = {
+	{
+		.start	= OMAP243X_GPIO4_BASE,
+		.end	= OMAP243X_GPIO4_BASE + OMAP2_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_24XX_GPIO_BANK4,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap243x_gpio4_config = {
+	.ick_name = "gpios_ick",
+	.fck_name = "gpios_fck",
+	.virtual_irq_start = IH_GPIO_BASE + 96,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap243x_gpio4 = {
+	.name           = "omap-gpio",
+	.id             = 3,
+	.dev            = {
+		.platform_data = &omap243x_gpio4_config,
+	},
+	.num_resources = ARRAY_SIZE(omap243x_gpio4_resources),
+	.resource = omap243x_gpio4_resources,
+};
+
+/*
+ * OMAP243X GPIO5 interface data
+ */
+static struct __initdata resource omap243x_gpio5_resources[] = {
+	{
+		.start	= OMAP243X_GPIO5_BASE,
+		.end	= OMAP243X_GPIO5_BASE + OMAP2_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_24XX_GPIO_BANK5,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap243x_gpio5_config = {
+	.ick_name = "gpio5_ick",
+	.fck_name = "gpio5_fck",
+	.virtual_irq_start = IH_GPIO_BASE + 128,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap243x_gpio5 = {
+	.name           = "omap-gpio",
+	.id             = 4,
+	.dev            = {
+		.platform_data = &omap243x_gpio5_config,
+	},
+	.num_resources = ARRAY_SIZE(omap243x_gpio5_resources),
+	.resource = omap243x_gpio5_resources,
+};
+
+static struct __initdata platform_device * omap242x_gpio_early_dev[] = {
+	&omap242x_gpio1,
+	&omap242x_gpio2,
+	&omap242x_gpio3,
+	&omap242x_gpio4
+};
+
+static struct __initdata platform_device * omap243x_gpio_early_dev[] = {
+	&omap243x_gpio1,
+	&omap243x_gpio2,
+	&omap243x_gpio3,
+	&omap243x_gpio4,
+	&omap243x_gpio5
+};
+
+static inline struct gpio_bank *omap2_get_gpio_bank(int gpio,
+					struct gpio_bank *gpio_bank)
+{
+	if (cpu_is_omap24xx())
+		return &gpio_bank[gpio >> 5];
+	BUG();
+	return NULL;
+};
+
+static int set_omap2_gpio_triggering(struct gpio_bank *bank, int gpio,
+						int trigger)
+{
+	void __iomem *base = bank->base;
+	u32 gpio_bit = 1 << gpio;
+
+	if (!cpu_is_omap24xx())
+		return -EINVAL;
+
+	MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
+				trigger & IRQ_TYPE_LEVEL_LOW);
+	MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
+				trigger & IRQ_TYPE_LEVEL_HIGH);
+	MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
+				trigger & IRQ_TYPE_EDGE_RISING);
+	MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
+				trigger & IRQ_TYPE_EDGE_FALLING);
+	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
+		if (trigger != 0)
+			__raw_writel(1 << gpio, bank->base
+					+ OMAP24XX_GPIO_SETWKUENA);
+		else
+			__raw_writel(1 << gpio, bank->base
+					+ OMAP24XX_GPIO_CLEARWKUENA);
+	} else {
+		if (trigger != 0)
+			bank->enabled_non_wakeup_gpios |= gpio_bit;
+		else
+			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
+	}
+
+	bank->level_mask =
+			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
+			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+
+	return 0;
+}
+
+void __init omap2_gpio_mod_init(struct gpio_bank *bank, int i)
+{
+	static const u32 non_wakeup_gpios[] = {
+		0xe203ffc0, 0x08700040
+	};
+
+	/*
+	 * Initialize interface clock ungated,
+	 * module enabled
+	 */
+	__raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
+	__raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
+	__raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
+	__raw_writew(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
+	__raw_writew(0x0, bank->base + OMAP24XX_GPIO_CTRL);
+
+	if (i < ARRAY_SIZE(non_wakeup_gpios))
+		bank->non_wakeup_gpios = non_wakeup_gpios[i];
+}
+
+/*
+ * OMAP2 GPIO function pointers, reg offset pointer and other info
+ */
+static struct omap_gpio_info omap2_gpio_data = {
+	.reg_off		= &omap2_gpio_reg,
+	.index_mask		= 0x1f,
+	.no_of_gpio		= 128,
+	.bank_bits		= 32,
+	.gpio_mod_init		= omap2_gpio_mod_init,
+	.get_gpio_bank		= omap2_get_gpio_bank,
+	.set_gpio_triggering	= set_omap2_gpio_triggering,
+};
+
+void __init omap2_gpio_init_data(void)
+{
+	if (cpu_is_omap242x())
+		omap2_gpio_data.bank_count = 4;
+	else if (cpu_is_omap243x())
+		omap2_gpio_data.bank_count = 5;
+
+	gpio_init(&omap2_gpio_data);
+}
+
+int __init omap2_early_init_gpio(struct platform_device ***pdev)
+{
+	int no_of_dev = 0;
+
+	if (cpu_is_omap242x()) {
+		*pdev = omap242x_gpio_early_dev;
+		no_of_dev = 4;
+	} else if (cpu_is_omap243x()) {
+		*pdev = omap243x_gpio_early_dev;
+		no_of_dev = 5;
+	}
+
+	return no_of_dev;
+}
+
+int __init omap2_gpio_dev_reg(void)
+{
+	if (cpu_is_omap242x()) {
+		platform_device_register(&omap242x_gpio1);
+		platform_device_register(&omap242x_gpio2);
+		platform_device_register(&omap242x_gpio3);
+		platform_device_register(&omap242x_gpio4);
+	} else if (cpu_is_omap243x()) {
+		platform_device_register(&omap243x_gpio1);
+		platform_device_register(&omap243x_gpio2);
+		platform_device_register(&omap243x_gpio3);
+		platform_device_register(&omap243x_gpio4);
+		platform_device_register(&omap243x_gpio5);
+	}
+
+	return 0;
+}
+arch_initcall(omap2_gpio_dev_reg);

index 07bfa0f..e822a41 100644
@@ -110,6 +110,8 @@
 #define OMAP4_GPIO_CLEARDATAOUT		0x0190
 #define OMAP4_GPIO_SETDATAOUT		0x0194
 
+extern void omap2_gpio_init_data(void);
 extern void omap3_gpio_init_data(void);
+extern int omap2_early_init_gpio(struct platform_device ***pdev);
 extern int omap3_early_init_gpio(struct platform_device ***pdev);
 #endif

new file mode 100644
index 0000000..6133251
@@ -0,0 +1,350 @@
+/*
+ * gpio44xx.c - OMAP4-specific gpio code
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Author:
+ *	Charulatha V <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/gpio.h>
+
+/*
+ * OMAP4 GPIO reg offsets
+ */
+static struct gpio_reg_offset omap4_gpio_reg = {
+	.data_in	= OMAP4_GPIO_DATAIN,
+	.data_out	= OMAP4_GPIO_DATAOUT,
+	.data_out_set	= OMAP4_GPIO_SETDATAOUT,
+	.data_out_clear	= OMAP4_GPIO_CLEARDATAOUT,
+	.dir_ctrl	= OMAP4_GPIO_OE,
+	.irq_status0	= OMAP4_GPIO_IRQSTATUS0,
+	.irq_status1	= OMAP4_GPIO_IRQSTATUS1,
+	.irq_mask	= OMAP4_GPIO_IRQSTATUSSET0,
+	.irq_set	= OMAP4_GPIO_IRQSTATUSSET0,
+	.irq_clear	= OMAP4_GPIO_IRQSTATUSCLR0,
+	.irq_mask_bits	= 0xffffffff,
+	.irq_inv	= 0,
+	.wkup_enable	= OMAP4_GPIO_IRQWAKEN0,
+	.wkup_clear	= OMAP4_GPIO_IRQWAKEN0,
+	.wkup_set	= OMAP4_GPIO_IRQWAKEN0,
+	.debounce_ena	= OMAP4_GPIO_DEBOUNCENABLE,
+	.debounce_val	= OMAP4_GPIO_DEBOUNCINGTIME,
+	.ctrl		= OMAP4_GPIO_CTRL,
+	.syscfg		= OMAP4_GPIO_SYSCONFIG,
+	.leveldetect0	= OMAP4_GPIO_LEVELDETECT0,
+	.leveldetect1	= OMAP4_GPIO_LEVELDETECT1,
+	.rise_detect	= OMAP4_GPIO_RISINGDETECT,
+	.fall_detect	= OMAP4_GPIO_FALLINGDETECT,
+	.rev_reg	= OMAP4_GPIO_REVISION,
+};
+
+/*
+ * OMAP4 GPIO1 interface data
+ */
+static struct __initdata resource omap4_gpio1_resources[] = {
+	{
+		.start	= OMAP44XX_GPIO1_BASE,
+		.end	= OMAP44XX_GPIO1_BASE + OMAP4_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= OMAP44XX_IRQ_GPIO1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap4_gpio1_config = {
+	.ick_name = "gpio1_ick",
+	.dbck_name = "gpio1_dbck",
+	.virtual_irq_start = IH_GPIO_BASE,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap4_gpio1 = {
+	.name           = "omap-gpio",
+	.id             = 0,
+	.dev            = {
+		.platform_data = &omap4_gpio1_config,
+	},
+	.num_resources = ARRAY_SIZE(omap4_gpio1_resources),
+	.resource = omap4_gpio1_resources,
+};
+
+/*
+ * OMAP4 GPIO2 interface data
+ */
+static struct __initdata resource omap4_gpio2_resources[] = {
+	{
+		.start	= OMAP44XX_GPIO2_BASE,
+		.end	= OMAP44XX_GPIO2_BASE + OMAP4_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= OMAP44XX_IRQ_GPIO2,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap4_gpio2_config = {
+	.ick_name = "gpio2_ick",
+	.dbck_name = "gpio2_dbck",
+	.virtual_irq_start = IH_GPIO_BASE + 32,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap4_gpio2 = {
+	.name           = "omap-gpio",
+	.id             = 1,
+	.dev            = {
+		.platform_data = &omap4_gpio2_config,
+	},
+	.num_resources = ARRAY_SIZE(omap4_gpio2_resources),
+	.resource = omap4_gpio2_resources,
+};
+
+/*
+ * OMAP4 GPIO3 interface data
+ */
+static struct __initdata resource omap4_gpio3_resources[] = {
+	{
+		.start	= OMAP44XX_GPIO3_BASE,
+		.end	= OMAP44XX_GPIO3_BASE + OMAP4_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= OMAP44XX_IRQ_GPIO3,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap4_gpio3_config = {
+	.ick_name = "gpio3_ick",
+	.dbck_name = "gpio3_dbck",
+	.virtual_irq_start = IH_GPIO_BASE + 64,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap4_gpio3 = {
+	.name           = "omap-gpio",
+	.id             = 2,
+	.dev            = {
+		.platform_data = &omap4_gpio3_config,
+	},
+	.num_resources = ARRAY_SIZE(omap4_gpio3_resources),
+	.resource = omap4_gpio3_resources,
+};
+
+/*
+ * OMAP4 GPIO4 interface data
+ */
+static struct __initdata resource omap4_gpio4_resources[] = {
+	{
+		.start	= OMAP44XX_GPIO4_BASE,
+		.end	= OMAP44XX_GPIO4_BASE + OMAP4_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= OMAP44XX_IRQ_GPIO4,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap4_gpio4_config = {
+	.ick_name = "gpio4_ick",
+	.dbck_name = "gpio4_dbck",
+	.virtual_irq_start = IH_GPIO_BASE + 96,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap4_gpio4 = {
+	.name           = "omap-gpio",
+	.id             = 3,
+	.dev            = {
+		.platform_data = &omap4_gpio4_config,
+	},
+	.num_resources = ARRAY_SIZE(omap4_gpio4_resources),
+	.resource = omap4_gpio4_resources,
+};
+
+/*
+ * OMAP4 GPIO5 interface data
+  */
+static struct __initdata resource omap4_gpio5_resources[] = {
+	{
+		.start	= OMAP44XX_GPIO5_BASE,
+		.end	= OMAP44XX_GPIO5_BASE + OMAP4_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= OMAP44XX_IRQ_GPIO5,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap4_gpio5_config = {
+	.ick_name = "gpio5_ick",
+	.dbck_name = "gpio5_dbck",
+	.virtual_irq_start = IH_GPIO_BASE + 128,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap4_gpio5 = {
+	.name           = "omap-gpio",
+	.id             = 4,
+	.dev            = {
+		.platform_data = &omap4_gpio5_config,
+	},
+	.num_resources = ARRAY_SIZE(omap4_gpio5_resources),
+	.resource = omap4_gpio5_resources,
+};
+
+/*
+ * OMAP4 GPIO6 interface data
+  */
+static struct __initdata resource omap4_gpio6_resources[] = {
+	{
+		.start	= OMAP44XX_GPIO6_BASE,
+		.end	= OMAP44XX_GPIO6_BASE + OMAP4_GPIO_AS_LEN - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= OMAP44XX_IRQ_GPIO6,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct __initdata omap_gpio_platform_data omap4_gpio6_config = {
+	.ick_name = "gpio6_ick",
+	.dbck_name = "gpio6_dbck",
+	.virtual_irq_start = IH_GPIO_BASE + 160,
+	.method	= METHOD_GPIO_OMAP2PLUS,
+};
+
+static struct __initdata platform_device omap4_gpio6 = {
+	.name           = "omap-gpio",
+	.id             = 5,
+	.dev            = {
+		.platform_data = &omap4_gpio6_config,
+	},
+	.num_resources = ARRAY_SIZE(omap4_gpio6_resources),
+	.resource = omap4_gpio6_resources,
+};
+
+static struct __initdata platform_device * omap4_gpio_early_dev[] = {
+	&omap4_gpio1,
+	&omap4_gpio2,
+	&omap4_gpio3,
+	&omap4_gpio4,
+	&omap4_gpio5,
+	&omap4_gpio6
+};
+
+static struct gpio_bank *omap4_get_gpio_bank(int gpio,
+				struct gpio_bank *gpio_bank)
+{
+	if (cpu_is_omap44xx())
+		return &gpio_bank[gpio >> 5];
+	BUG();
+	return NULL;
+}
+
+static int set_omap4_gpio_triggering(struct gpio_bank *bank, int gpio,
+						int trigger)
+{
+	void __iomem *base = bank->base;
+	u32 gpio_bit = 1 << gpio;
+	u32 val;
+
+	if (!cpu_is_omap44xx())
+		return -EINVAL;
+
+	MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
+				trigger & IRQ_TYPE_LEVEL_LOW);
+	MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
+				trigger & IRQ_TYPE_LEVEL_HIGH);
+	MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
+				trigger & IRQ_TYPE_EDGE_RISING);
+	MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
+				trigger & IRQ_TYPE_EDGE_FALLING);
+	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
+		if (trigger != 0)
+			__raw_writel(1 << gpio, bank->base +
+						OMAP4_GPIO_IRQWAKEN0);
+		else {
+			val = __raw_readl(bank->base + OMAP4_GPIO_IRQWAKEN0);
+			__raw_writel(val & (~(1 << gpio)), bank->base +
+						 OMAP4_GPIO_IRQWAKEN0);
+		}
+	} else {
+		if (trigger != 0)
+			bank->enabled_non_wakeup_gpios |= gpio_bit;
+		else
+			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
+	}
+
+	bank->level_mask = __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
+				__raw_readl(bank->base +
+						OMAP4_GPIO_LEVELDETECT1);
+
+	return 0;
+}
+
+void __init omap4_gpio_mod_init(struct gpio_bank *bank, int i)
+{
+	static const u32 non_wakeup_gpios[] = {
+		0xe203ffc0, 0x08700040
+	};
+
+	__raw_writel(0xffffffff, bank->base + OMAP4_GPIO_IRQSTATUSCLR0);
+	__raw_writew(0x0015, bank->base + OMAP4_GPIO_SYSCONFIG);
+	__raw_writel(0x00000000, bank->base + OMAP4_GPIO_DEBOUNCENABLE);
+	/* Initialize interface clock ungated, module enabled */
+	__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
+
+	if (i < ARRAY_SIZE(non_wakeup_gpios))
+		bank->non_wakeup_gpios = non_wakeup_gpios[i];
+}
+
+/*
+ * OMAP4 GPIO function pointers, reg offset pointer and other info
+ */
+static struct omap_gpio_info omap4_gpio_data = {
+	.reg_off		= &omap4_gpio_reg,
+	.index_mask		= 0x1f,
+	.no_of_gpio		= 192,
+	.bank_count		= OMAP4_NR_GPIOS,
+	.bank_bits		= 32,
+	.get_gpio_bank		= omap4_get_gpio_bank,
+	.gpio_mod_init		= omap4_gpio_mod_init,
+	.set_gpio_triggering	= set_omap4_gpio_triggering,
+};
+
+void __init omap4_gpio_init_data(void)
+{
+	gpio_init(&omap4_gpio_data);
+}
+
+int __init omap4_early_init_gpio(struct platform_device ***pdev)
+{
+	*pdev = omap4_gpio_early_dev;
+	return OMAP4_NR_GPIOS;
+}
+
+int __init omap4_gpio_dev_reg(void)
+{
+	if (cpu_is_omap44xx()) {
+		platform_device_register(&omap4_gpio1);
+		platform_device_register(&omap4_gpio2);
+		platform_device_register(&omap4_gpio3);
+		platform_device_register(&omap4_gpio4);
+		platform_device_register(&omap4_gpio5);
+		platform_device_register(&omap4_gpio6);
+	}
+	return 0;
+}
+arch_initcall(omap4_gpio_dev_reg);

index e822a41..d2d9d17 100644
@@ -89,7 +89,6 @@
 #define OMAP4_GPIO_IRQWAKEN0		0x0044
 #define OMAP4_GPIO_IRQWAKEN1		0x0048
 #define OMAP4_GPIO_SYSSTATUS		0x0114
-#define OMAP4_GPIO_SYSSTATUS		0x0114
 #define OMAP4_GPIO_IRQENABLE1		0x011c
 #define OMAP4_GPIO_WAKE_EN		0x0120
 #define OMAP4_GPIO_IRQSTATUS2		0x0128

@@ -112,6 +111,8 @@
 
 extern void omap2_gpio_init_data(void);
 extern void omap3_gpio_init_data(void);
+extern void omap4_gpio_init_data(void);
 extern int omap2_early_init_gpio(struct platform_device ***pdev);
 extern int omap3_early_init_gpio(struct platform_device ***pdev);
+extern int omap4_early_init_gpio(struct platform_device ***pdev);
 #endif

new file mode 100644
index 0000000..341cdd5
@@ -0,0 +1,36 @@
+/*
+ * gpio.c - OMAP2PLUS architecture specific common gpio code
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Author:
+ *	Charulatha V <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/gpio.h>
+
+void __init omap_gpio_early_init(void)
+{
+	struct platform_device **pdev;
+	int no_of_dev;
+
+	if (cpu_is_omap24xx()) {
+		omap2_gpio_init_data();
+		no_of_dev = omap2_early_init_gpio(&pdev);
+	} else if (cpu_is_omap34xx()) {
+		omap3_gpio_init_data();
+		no_of_dev = omap3_early_init_gpio(&pdev);
+	} else if (cpu_is_omap44xx()) {
+		omap4_gpio_init_data();
+		no_of_dev = omap4_early_init_gpio(&pdev);
+	} else
+		return;
+
+	early_platform_add_devices(pdev, no_of_dev);
+	early_platform_driver_register_all("earlygpio");
+	early_platform_driver_probe("earlygpio", no_of_dev, 0);
+}

index d2d9d17..3a0fcb1 100644
@@ -115,4 +115,5 @@ extern void omap4_gpio_init_data(void);
 extern int omap2_early_init_gpio(struct platform_device ***pdev);
 extern int omap3_early_init_gpio(struct platform_device ***pdev);
 extern int omap4_early_init_gpio(struct platform_device ***pdev);
+extern void __init omap_gpio_early_init(void);
 #endif

new file mode 100644
index 0000000..e54ce07
@@ -0,0 +1,404 @@
+/*
+ * gpio.c - OMAP1 architecture specific common gpio code
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * Author:
+ *	Charulatha V <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/gpio.h>
+
+static struct gpio_bank omap1610_gpio_bank[5] = {
+	{ OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
+		METHOD_MPUIO },
+	{ OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
+		METHOD_GPIO_1610 },
+	{ OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
+		METHOD_GPIO_1610 },
+	{ OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
+		METHOD_GPIO_1610 },
+	{ OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
+		METHOD_GPIO_1610 },
+};
+
+static struct gpio_bank omap1510_gpio_bank[2] = {
+	{ OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
+		METHOD_MPUIO },
+	{ OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
+		METHOD_GPIO_1510 }
+};
+
+static struct gpio_bank omap7xx_gpio_bank[7] = {
+	{ OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
+		METHOD_MPUIO },
+	{ OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
+		METHOD_GPIO_7XX },
+	{ OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
+		METHOD_GPIO_7XX },
+	{ OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
+		METHOD_GPIO_7XX },
+	{ OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4,  IH_GPIO_BASE + 96,
+		METHOD_GPIO_7XX },
+	{ OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5,  IH_GPIO_BASE + 128,
+		METHOD_GPIO_7XX },
+	{ OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6,  IH_GPIO_BASE + 160,
+		METHOD_GPIO_7XX },
+};
+
+static struct gpio_reg_offset omap1610_gpio_reg = {
+	.data_in	= OMAP1610_GPIO_DATAIN,
+	.data_out	= OMAP1610_GPIO_DATAOUT,
+	.data_out_set	= OMAP1610_GPIO_SET_DATAOUT,
+	.data_out_clear	= OMAP1610_GPIO_CLEAR_DATAOUT,
+	.dir_ctrl	= OMAP1610_GPIO_DIRECTION,
+	.irq_status0	= OMAP1610_GPIO_IRQSTATUS1,
+	.irq_mask	= OMAP1610_GPIO_IRQENABLE1,
+	.irq_set	= OMAP1610_GPIO_SET_IRQENABLE1,
+	.irq_clear	= OMAP1610_GPIO_CLEAR_IRQENABLE1,
+	.irq_mask_bits	= 0xffff,
+	.irq_inv	= 0,
+	.wkup_enable	= OMAP1610_GPIO_WAKEUPENABLE,
+	.wkup_clear	= OMAP1610_GPIO_CLEAR_WAKEUPENA,
+	.wkup_set	= OMAP1610_GPIO_SET_WAKEUPENA,
+	.syscfg		= OMAP1610_GPIO_SYSCONFIG,
+};
+
+static struct gpio_reg_offset omap1510_gpio_reg = {
+	.data_in	= OMAP1510_GPIO_DATA_INPUT,
+	.data_out	= OMAP1510_GPIO_DATA_OUTPUT,
+	.dir_ctrl	= OMAP1510_GPIO_DIR_CONTROL,
+	.irq_status0	= OMAP1510_GPIO_INT_STATUS,
+	.irq_mask	= OMAP1510_GPIO_INT_MASK,
+	.irq_mask_bits	= 0xffff,
+	.irq_inv	= 1,
+	.ctrl		= OMAP1510_GPIO_PIN_CONTROL,
+};
+
+static struct gpio_reg_offset omap7xx_gpio_reg = {
+	.data_in	= OMAP7XX_GPIO_DATA_INPUT,
+	.data_out	= OMAP7XX_GPIO_DATA_OUTPUT,
+	.dir_ctrl	= OMAP7XX_GPIO_DIR_CONTROL,
+	.irq_status0	= OMAP7XX_GPIO_INT_STATUS,
+	.irq_mask	= OMAP7XX_GPIO_INT_MASK,
+	.irq_mask_bits	= 0xffffffff,
+	.irq_inv	= 1,
+};
+
+static struct mpu_gpio_reg_off omap1_gpio_mpureg = {
+	.mpu_io_ctrl		= OMAP_MPUIO_IO_CNTL,
+	.mpu_data_out		= OMAP_MPUIO_OUTPUT,
+	.mpu_data_in		= OMAP_MPUIO_INPUT_LATCH,
+	.mpu_isr		= OMAP_MPUIO_GPIO_INT,
+	.mpu_irq_mask		= OMAP_MPUIO_GPIO_MASKIT,
+	.mpu_irq_mask_bits	= 0xffff,
+	.mpu_irq_inv		= 1,
+};
+
+static struct gpio_bank *omap1_get_gpio_bank(int gpio,
+				struct gpio_bank *gpio_bank)
+{
+	if (cpu_is_omap15xx()) {
+		if (OMAP_GPIO_IS_MPUIO(gpio))
+			return &gpio_bank[0];
+		return &gpio_bank[1];
+	} else if (cpu_is_omap16xx()) {
+		if (OMAP_GPIO_IS_MPUIO(gpio))
+			return &gpio_bank[0];
+		return &gpio_bank[1 + (gpio >> 4)];
+	} else if (cpu_is_omap7xx()) {
+		if (OMAP_GPIO_IS_MPUIO(gpio))
+			return &gpio_bank[0];
+		return &gpio_bank[1 + (gpio >> 5)];
+	}
+	BUG();
+	return NULL;
+}
+
+/*
+ * This only applies to chips that can't do both rising and falling edge
+ * detection at once.  For all other chips, this function is a noop.
+ */
+static void omap1_toggle_edge_triggering(struct gpio_bank *bank, int gpio)
+{
+	void __iomem *reg = bank->base;
+	u32 l = 0;
+
+	switch (bank->method) {
+	case METHOD_MPUIO:
+		reg += OMAP_MPUIO_GPIO_INT_EDGE;
+		break;
+	case METHOD_GPIO_1510:
+		reg += OMAP1510_GPIO_INT_CONTROL;
+		break;
+	case METHOD_GPIO_7XX:
+		reg += OMAP7XX_GPIO_INT_CONTROL;
+		break;
+	default:
+		return;
+	}
+
+	l = __raw_readl(reg);
+	if ((l >> gpio) & 1)
+		l &= ~(1 << gpio);
+	else
+		l |= 1 << gpio;
+
+	__raw_writel(l, reg);
+}
+
+static int set_omap1_gpio_triggering(struct gpio_bank *bank, int gpio,
+						int trigger)
+{
+	void __iomem *reg = bank->base;
+	u32 l = 0;
+
+	switch (bank->method) {
+	case METHOD_MPUIO:
+		reg += OMAP_MPUIO_GPIO_INT_EDGE;
+		l = __raw_readl(reg);
+		if (trigger & IRQ_TYPE_EDGE_BOTH)
+			bank->toggle_mask |= 1 << gpio;
+		if (trigger & IRQ_TYPE_EDGE_RISING)
+			l |= 1 << gpio;
+		else if (trigger & IRQ_TYPE_EDGE_FALLING)
+			l &= ~(1 << gpio);
+		else
+			goto bad;
+		break;
+	case METHOD_GPIO_1510:
+		reg += OMAP1510_GPIO_INT_CONTROL;
+		l = __raw_readl(reg);
+		if (trigger & IRQ_TYPE_EDGE_BOTH)
+			bank->toggle_mask |= 1 << gpio;
+		if (trigger & IRQ_TYPE_EDGE_RISING)
+			l |= 1 << gpio;
+		else if (trigger & IRQ_TYPE_EDGE_FALLING)
+			l &= ~(1 << gpio);
+		else
+			goto bad;
+		break;
+	case METHOD_GPIO_1610:
+		if (gpio & 0x08)
+			reg += OMAP1610_GPIO_EDGE_CTRL2;
+		else
+			reg += OMAP1610_GPIO_EDGE_CTRL1;
+		gpio &= 0x07;
+		l = __raw_readl(reg);
+		l &= ~(3 << (gpio << 1));
+		if (trigger & IRQ_TYPE_EDGE_RISING)
+			l |= 2 << (gpio << 1);
+		if (trigger & IRQ_TYPE_EDGE_FALLING)
+			l |= 1 << (gpio << 1);
+		if (trigger)
+			/* Enable wake-up during idle for dynamic tick */
+			__raw_writel(1 << gpio, bank->base +
+						OMAP1610_GPIO_SET_WAKEUPENA);
+		else
+			__raw_writel(1 << gpio, bank->base +
+						OMAP1610_GPIO_CLEAR_WAKEUPENA);
+		break;
+	case METHOD_GPIO_7XX:
+		reg += OMAP7XX_GPIO_INT_CONTROL;
+		l = __raw_readl(reg);
+		if (trigger & IRQ_TYPE_EDGE_BOTH)
+			bank->toggle_mask |= 1 << gpio;
+		if (trigger & IRQ_TYPE_EDGE_RISING)
+			l |= 1 << gpio;
+		else if (trigger & IRQ_TYPE_EDGE_FALLING)
+			l &= ~(1 << gpio);
+		else
+			goto bad;
+		break;
+	default:
+		goto bad;
+	}
+	__raw_writel(l, reg);
+	return 0;
+bad:
+	return -EINVAL;
+}
+
+#ifdef CONFIG_ARCH_OMAP16XX
+static int omap_mpuio_suspend_noirq(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct gpio_bank	*bank = platform_get_drvdata(pdev);
+	void __iomem		*mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
+	unsigned long		flags;
+
+	spin_lock_irqsave(&bank->lock, flags);
+	bank->saved_wakeup = __raw_readl(mask_reg);
+	__raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
+	spin_unlock_irqrestore(&bank->lock, flags);
+
+	return 0;
+}
+
+static int omap_mpuio_resume_noirq(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct gpio_bank	*bank = platform_get_drvdata(pdev);
+	void __iomem		*mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
+	unsigned long		flags;
+
+	spin_lock_irqsave(&bank->lock, flags);
+	__raw_writel(bank->saved_wakeup, mask_reg);
+	spin_unlock_irqrestore(&bank->lock, flags);
+
+	return 0;
+}
+
+static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
+	.suspend_noirq = omap_mpuio_suspend_noirq,
+	.resume_noirq = omap_mpuio_resume_noirq,
+};
+
+/* use platform_driver for this, now that there's no longer any
+ * point to sys_device (other than not disturbing old code).
+ */
+static struct platform_driver omap_mpuio_driver = {
+	.driver		= {
+		.name	= "mpuio",
+		.pm	= &omap_mpuio_dev_pm_ops,
+	},
+};
+
+static struct platform_device omap_mpuio_device = {
+	.name		= "mpuio",
+	.id		= -1,
+	.dev = {
+		.driver = &omap_mpuio_driver.driver,
+	}
+	/* could list the /proc/iomem resources */
+};
+
+void mpuio_init(void)
+{
+	platform_set_drvdata(&omap_mpuio_device, &omap1610_gpio_bank[0]);
+
+	if (platform_driver_register(&omap_mpuio_driver) == 0)
+		(void) platform_device_register(&omap_mpuio_device);
+}
+#else
+static struct platform_device omap_mpuio_device;
+void mpuio_init(void) {}
+#endif
+
+/*
+ * OMAP1 GPIO function pointers, reg offset pointer and other info
+ */
+static struct omap_gpio_info omap1_gpio_data = {
+	.get_gpio_bank		= omap1_get_gpio_bank,
+	.set_gpio_triggering	= set_omap1_gpio_triggering,
+	.toggle_edge_triggering = omap1_toggle_edge_triggering,
+	.mpu_reg		= &omap1_gpio_mpureg,
+};
+
+static void __init omap1_init_gpio(struct gpio_bank *gpio_bank)
+{
+	int i;
+	struct gpio_bank *bank;
+
+	if (cpu_is_omap15xx()) {
+		struct clk *gpio_ick;
+		gpio_ick = clk_get(NULL, "arm_gpio_ck");
+		if (IS_ERR(gpio_ick))
+			printk(KERN_ERR "Could not get arm_gpio_ck\n");
+		else
+			clk_enable(gpio_ick);
+	}
+
+	for (i = 0; i < omap1_gpio_data.bank_count; i++) {
+		bank = &gpio_bank[i];
+		spin_lock_init(&bank->lock);
+
+		/* Static mapping, never released */
+		bank->base = ioremap(bank->pbase, SZ_2K);
+		if (!bank->base) {
+			printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
+			continue;
+		}
+	}
+
+	if (bank_is_mpuio(bank))
+		__raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
+	else if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
+		__raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
+		__raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
+	} else if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
+		__raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
+		__raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
+		__raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
+	} else if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
+		__raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
+		__raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
+	}
+
+	if (cpu_is_omap16xx()) {
+		u32 rev;
+		/* Enable system clock for GPIO module.
+		 * The CAM_CLK_CTRL *is* really the right place.
+		 */
+		bank->chip.dev = &omap_mpuio_device.dev;
+		if (bank_is_mpuio(bank))
+			omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) |
+						0x04, ULPD_CAM_CLK_CTRL);
+		rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
+		printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
+					(rev >> 4) & 0x0f, rev & 0x0f);
+	}
+}
+
+static void __init omap1_gpio_init(void)
+{
+	if (cpu_is_omap16xx()) {
+		omap1_gpio_data.reg_off	= &omap1610_gpio_reg;
+		omap1_gpio_data.index_mask = 0x0f;
+		omap1_gpio_data.no_of_gpio = 64;
+		omap1_gpio_data.bank_count = 5;
+		omap1_gpio_data.bank_bits = 16;
+		omap1_gpio_data.gpio_bank = omap1610_gpio_bank;
+	} else if (cpu_is_omap15xx()) {
+		omap1_gpio_data.reg_off	= &omap1510_gpio_reg;
+		omap1_gpio_data.index_mask = 0x0f;
+		omap1_gpio_data.no_of_gpio = 16;
+		omap1_gpio_data.bank_count = 2;
+		omap1_gpio_data.bank_bits = 16;
+		omap1_gpio_data.gpio_bank = omap1510_gpio_bank;
+	} else if (cpu_is_omap7xx()) {
+		omap1_gpio_data.reg_off	= &omap7xx_gpio_reg;
+		omap1_gpio_data.index_mask = 0x1f;
+		omap1_gpio_data.no_of_gpio = 192;
+		omap1_gpio_data.bank_count = 7;
+		omap1_gpio_data.bank_bits = 32;
+		omap1_gpio_data.gpio_bank = omap7xx_gpio_bank;
+	}
+	omap1_init_gpio(omap1_gpio_data.gpio_bank);
+	gpio_init(&omap1_gpio_data);
+}
+
+/*
+ * This may get called early from board specific init
+ * for boards that have interrupts routed via FPGA.
+ */
+int __init omap_gpio_init(void)
+{
+	int i;
+	static int initialized;
+
+	if ((!initialized) && cpu_class_is_omap1()) {
+			omap1_gpio_init();
+			for (i = 0; i < omap1_gpio_data.bank_count; i++)
+				init_gpio_chip_irq(omap1_gpio_data.gpio_bank);
+
+			mpuio_init();
+	}
+	initialized = 1;
+
+	return 0;
+}

index 01d113f..7f55fcf 100644
@@ -146,9 +146,8 @@ static void __init omap_2430sdp_init_irq(void)
 {
 	omap_board_config = sdp2430_config;
 	omap_board_config_size = ARRAY_SIZE(sdp2430_config);
-	omap2_init_common_hw(NULL, NULL);
 	omap_init_irq();
-	omap_gpio_init();
+	omap2_init_common_hw(NULL, NULL);
 }
 
 static struct twl4030_gpio_platform_data sdp2430_gpio_data = {

index 5822bcf..6cd640c 100644
@@ -327,9 +327,8 @@ static void __init omap_3430sdp_init_irq(void)
 	omap_board_config = sdp3430_config;
 	omap_board_config_size = ARRAY_SIZE(sdp3430_config);
 	omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
-	omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
 	omap_init_irq();
-	omap_gpio_init();
+	omap2_init_common_hw(hyb18m512160af6_sdrc_params, NULL);
 }
 
 static int sdp3430_batt_table[] = {

index 504d2bd..843a729 100644
@@ -79,10 +79,9 @@ static void __init omap_sdp_init_irq(void)
 {
 	omap_board_config = sdp_config;
 	omap_board_config_size = ARRAY_SIZE(sdp_config);
+	omap_init_irq();
 	omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
 			h8mbx00u0mer0em_sdrc_params);
-	omap_init_irq();
-	omap_gpio_init();
 }
 
 #ifdef CONFIG_OMAP_MUX

index b88f28c..baf5955 100644
@@ -97,12 +97,11 @@ static void __init omap_4430sdp_init_irq(void)
 {
 	omap_board_config = sdp4430_config;
 	omap_board_config_size = ARRAY_SIZE(sdp4430_config);
+	gic_init_irq();
 	omap2_init_common_hw(NULL, NULL);
 #ifdef CONFIG_OMAP_32K_TIMER
 	omap2_gp_clockevent_set_gptimer(1);
 #endif
-	gic_init_irq();
-	omap_gpio_init();
 }
 
 static struct omap_musb_board_data musb_board_data = {

index 6ae8805..ea52dc9 100644
@@ -268,9 +268,8 @@ static void __init am3517_evm_init_irq(void)
 	omap_board_config = am3517_evm_config;
 	omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
 
-	omap2_init_common_hw(NULL, NULL);
 	omap_init_irq();
-	omap_gpio_init();
+	omap2_init_common_hw(NULL, NULL);
 }
 
 static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {

index aa69fb9..3fe86df 100644
@@ -277,9 +277,8 @@ static void __init omap_apollon_init_irq(void)
 {
 	omap_board_config = apollon_config;
 	omap_board_config_size = ARRAY_SIZE(apollon_config);
-	omap2_init_common_hw(NULL, NULL);
 	omap_init_irq();
-	omap_gpio_init();
+	omap2_init_common_hw(NULL, NULL);
 	apollon_init_smc91x();
 }
 

index 2de4f79..596acba 100644
@@ -701,10 +701,9 @@ static void __init cm_t35_init_irq(void)
 	omap_board_config = cm_t35_config;
 	omap_board_config_size = ARRAY_SIZE(cm_t35_config);
 
+	omap_init_irq();
 	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
 			     mt46h32m32lf6_sdrc_params);
-	omap_init_irq();
-	omap_gpio_init();
 }
 
 static void __init cm_t35_map_io(void)

index 5bfc13b..0e8d38c 100644
@@ -481,13 +481,12 @@ static void __init devkit8000_init_irq(void)
 {
 	omap_board_config = devkit8000_config;
 	omap_board_config_size = ARRAY_SIZE(devkit8000_config);
+	omap_init_irq();
 	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
 			     mt46h32m32lf6_sdrc_params);
-	omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
 	omap2_gp_clockevent_set_gptimer(12);
 #endif
-	omap_gpio_init();
 }
 
 static void __init devkit8000_ads7846_init(void)

index 16cc068..9ba0777 100644
@@ -38,8 +38,8 @@ static void __init omap_generic_init_irq(void)
 {
 	omap_board_config = generic_config;
 	omap_board_config_size = ARRAY_SIZE(generic_config);
-	omap2_init_common_hw(NULL, NULL);
 	omap_init_irq();
+	omap2_init_common_hw(NULL, NULL);
 }
 
 static void __init omap_generic_init(void)

index 0665f2c..a143e64 100644
@@ -312,9 +312,8 @@ static void __init omap_h4_init_irq(void)
 {
 	omap_board_config = h4_config;
 	omap_board_config_size = ARRAY_SIZE(h4_config);
-	omap2_init_common_hw(NULL, NULL);
 	omap_init_irq();
-	omap_gpio_init();
+	omap2_init_common_hw(NULL, NULL);
 	h4_init_flash();
 }
 

index 3c7789d..885313e 100644
@@ -404,9 +404,8 @@ static void __init igep2_init_irq(void)
 {
 	omap_board_config = igep2_config;
 	omap_board_config_size = ARRAY_SIZE(igep2_config);
-	omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
 	omap_init_irq();
-	omap_gpio_init();
+	omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params);
 }
 
 static struct twl4030_codec_audio_data igep2_audio_data = {

index 5fcb52e..f0d6ad9 100644
@@ -290,9 +290,8 @@ static void __init omap_ldp_init_irq(void)
 {
 	omap_board_config = ldp_config;
 	omap_board_config_size = ARRAY_SIZE(ldp_config);
-	omap2_init_common_hw(NULL, NULL);
 	omap_init_irq();
-	omap_gpio_init();
+	omap2_init_common_hw(NULL, NULL);
 	ldp_init_smsc911x();
 }
 

index 131ce3c..396ef39 100644
@@ -673,9 +673,8 @@ static void __init n8x0_map_io(void)
 
 static void __init n8x0_init_irq(void)
 {
-	omap2_init_common_hw(NULL, NULL);
 	omap_init_irq();
-	omap_gpio_init();
+	omap2_init_common_hw(NULL, NULL);
 }
 
 static void __init n8x0_init_machine(void)

index 962d377..96d44f4 100644
@@ -357,13 +357,12 @@ static void __init omap3_beagle_init_irq(void)
 {
 	omap_board_config = omap3_beagle_config;
 	omap_board_config_size = ARRAY_SIZE(omap3_beagle_config);
+	omap_init_irq();
 	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
 			     mt46h32m32lf6_sdrc_params);
-	omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
 	omap2_gp_clockevent_set_gptimer(12);
 #endif
-	omap_gpio_init();
 }
 
 static struct platform_device *omap3_beagle_devices[] __initdata = {

index 017bb2f..a592773 100644
@@ -626,9 +626,8 @@ static void __init omap3_evm_init_irq(void)
 {
 	omap_board_config = omap3_evm_config;
 	omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
-	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
 	omap_init_irq();
-	omap_gpio_init();
+	omap2_init_common_hw(mt46h32m32lf6_sdrc_params, NULL);
 }
 
 static struct platform_device *omap3_evm_devices[] __initdata = {

index 395d049..7606170 100644
@@ -533,10 +533,9 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
 
 static void __init omap3pandora_init_irq(void)
 {
+	omap_init_irq();
 	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
 			     mt46h32m32lf6_sdrc_params);
-	omap_init_irq();
-	omap_gpio_init();
 }
 
 static struct platform_device *omap3pandora_devices[] __initdata = {

index 2504d41..fa35ffe 100644
@@ -439,13 +439,12 @@ static void __init omap3_touchbook_init_irq(void)
 	omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 	omap_board_config = omap3_touchbook_config;
 	omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
+	omap_init_irq();
 	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
 			     mt46h32m32lf6_sdrc_params);
-	omap_init_irq();
 #ifdef CONFIG_OMAP_32K_TIMER
 	omap2_gp_clockevent_set_gptimer(12);
 #endif
-	omap_gpio_init();
 }
 
 static struct platform_device *omap3_touchbook_devices[] __initdata = {

index 8848c7c..830515e 100644
@@ -384,10 +384,9 @@ static void __init overo_init_irq(void)
 {
 	omap_board_config = overo_config;
 	omap_board_config_size = ARRAY_SIZE(overo_config);
+	omap_init_irq();
 	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
 			     mt46h32m32lf6_sdrc_params);
-	omap_init_irq();
-	omap_gpio_init();
 }
 
 static struct platform_device *overo_devices[] __initdata = {

index b155c36..dbaaf56 100644
@@ -105,9 +105,8 @@ static void __init rx51_init_irq(void)
 	omap_board_config_size = ARRAY_SIZE(rx51_config);
 	omap3_pm_init_cpuidle(rx51_cpuidle_params);
 	sdrc_params = rx51_get_sdram_timings();
-	omap2_init_common_hw(sdrc_params, sdrc_params);
 	omap_init_irq();
-	omap_gpio_init();
+	omap2_init_common_hw(sdrc_params, sdrc_params);
 }
 
 extern void __init rx51_peripherals_init(void);

index 9a26f84..6238338 100644
@@ -28,10 +28,9 @@
 
 static void __init omap_zoom2_init_irq(void)
 {
+	omap_init_irq();
 	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
 				 mt46h32m32lf6_sdrc_params);
-	omap_init_irq();
-	omap_gpio_init();
 }
 
 /* REVISIT: These audio entries can be removed once MFD code is merged */

index cd3e40c..ff2fb22 100644
@@ -38,10 +38,9 @@ static void __init omap_zoom_init_irq(void)
 {
 	omap_board_config = zoom_config;
 	omap_board_config_size = ARRAY_SIZE(zoom_config);
+	omap_init_irq();
 	omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params,
 			h8mbx00u0mer0em_sdrc_params);
-	omap_init_irq();
-	omap_gpio_init();
 }
 
 #ifdef CONFIG_OMAP_MUX

index 87f676a..e6e5834 100644
@@ -34,6 +34,7 @@
 #include <plat/gpmc.h>
 #include <plat/serial.h>
 #include <plat/vram.h>
+#include <plat/gpio.h>
 
 #include "clock2xxx.h"
 #include "clock3xxx.h"

@@ -339,4 +340,5 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
 		_omap2_init_reprogram_sdrc();
 	}
 	gpmc_init();
+	omap_gpio_init();
 }

index e6e5834..2b9efda 100644
@@ -340,5 +340,5 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
 		_omap2_init_reprogram_sdrc();
 	}
 	gpmc_init();
-	omap_gpio_init();
+	omap_gpio_early_init();
 }

2,055 lines not on this page · raw message

index d154897..98e0088 100644
@@ -47,15 +47,25 @@
 #define METHOD_GPIO_1510	1
 #define METHOD_GPIO_1610	2
 #define METHOD_GPIO_7XX		3
-#define METHOD_GPIO_24XX	4
-#define METHOD_GPIO_44XX	5
+#define METHOD_GPIO_OMAP2PLUS	4
 
+#define bank_is_mpuio(bank)	((bank)->method == METHOD_MPUIO)
 #define OMAP_MPUIO(nr)		(OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr)	((nr) >= OMAP_MAX_GPIO_LINES)
 #define OMAP_GPIO_IRQ(nr)	(OMAP_GPIO_IS_MPUIO(nr) ? \
 				 IH_MPUIO_BASE + ((nr) & 0x0f) : \
 				 IH_GPIO_BASE + (nr))
 
+#define MOD_REG_BIT(reg, bit_mask, set)	\
+do {	\
+	int l = __raw_readl(base + reg); \
+	if (set) \
+		l |= bit_mask; \
+	else \
+		l &= ~bit_mask; \
+	__raw_writel(l, base + reg); \
+} while (0)
+
 struct omap_gpio_platform_data {
 	u16 virtual_irq_start;
 	int method;

@@ -103,7 +113,9 @@ struct mpu_gpio_reg_off {
 };
 
 struct gpio_bank {
+#ifdef CONFIG_ARCH_OMAP1
 	unsigned long pbase;
+#endif
 	void __iomem *base;
 	u16 irq;
 	u16 virtual_irq_start;

@@ -159,14 +171,21 @@ struct omap_gpio_info {
 	void	(*gpio_mod_init) (struct gpio_bank *bank, int i);
 };
 
+extern int gpio_init(struct omap_gpio_info *custom_gpio);
+#ifdef CONFIG_ARCH_OMAP1
+extern int omap_gpio_init(void); /* Call from board init only */
+extern void init_gpio_chip_irq(struct gpio_bank *bank);
+#endif
 
-extern int omap_gpio_init(void);	/* Call from board init only */
+#ifdef CONFIG_ARCH_OMAP2PLUS
 extern void omap2_gpio_prepare_for_retention(void);
 extern void omap2_gpio_resume_after_retention(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
 extern void omap_gpio_save_context(void);
 extern void omap_gpio_restore_context(void);
+#endif
+
 /*-------------------------------------------------------------------------*/
 
 /* Wrappers for "new style" GPIO calls, using the new infrastructure