Initial support.

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@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2010 Texas Instruments
+ *
+ * Aldo Cedillo <[email protected]>
+ *
+ * Derived from: board/omap3/zoom2/zoom2.h
+ * Tom Rix <[email protected]>
+ *
+ * Derived from: board/omap3/zoom1/zoom1.h
+ * Nishanth Menon <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BOARD_ZOOM3_H_
+#define _BOARD_ZOOM3_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 Zoom3",
+	"NAND",
+};
+
+typedef enum {
+	ZOOM3_REVISION_UNKNOWN = 0,
+	ZOOM3_REVISION_ALPHA,
+	ZOOM3_REVISION_BETA,
+	ZOOM3_REVISION_PRODUCTION
+} zoom3_revision;
+
+zoom3_revision zoom3_get_revision(void);
+
+/*
+ * IEN	- Input Enable
+ * IDIS	- Input Disable
+ * PTD	- Pull type Down
+ * PTU	- Pull type Up
+ * DIS	- Pull type selection is inactive
+ * EN	- Pull type selection is active
+ * M0	- Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_ZOOM3() \
+ /* SDRC*/\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
+/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS1 */\
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS2 */\
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS3 */\
+	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS4 */\
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M7)) /* GPMC_nCS5 */\
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M7)) /* GPMC_nCS6 */\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M7)) /* GPMC_nCS7 */\
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+	MUX_VAL(CP(GPMC_NWP),		(IDIS | PTU | DIS | M0)) /* GPMC_nWP */\
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTD | EN  | M0)) /* GPMC_WAIT0 */\
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT1 */\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT2 */\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT3 */\
+/* IDCC modem Power On */\
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTU | EN  | M4)) /* GPIO_110 */\
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTU | EN  | M4)) /* GPIO_103 */\
+/* GPMC CS7 has LAN9211 device */\
+	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
+	MUX_VAL(CP(MCBSP1_DX),		(IEN  | PTD | DIS | M4)) /* LAN9221 */\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | EN  | M0)) /* MCSPI1_CS2 */\
+/* GPMC CS3 has Serial TL16CP754C device */\
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS3 */\
+/* Toggle Reset pin of TL16CP754C device */\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTU | EN  | M4)) /* GPIO_152 */\
+ udelay(10);\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | EN  | M4)) /* GPIO_152 */\
+	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */\
+/* LEDS */\
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | EN  | M4)) /* GPIO_173 red  */\
+	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | EN  | M4)) /* GPIO_154 blue */\
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | EN  | M4)) /* GPIO_61 blue2 */
+
+#endif /* _BOARD_ZOOM3_H_ */

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+/*
+ * Copyright (c) 2010 Texas Instruments <www.ti.com>
+ * Aldo Cedillo <[email protected]>
+ *
+ * Derived from Zoom2 code by
+ * Tom Rix <[email protected]>
+ *
+ * Derived from Zoom1 code by
+ *      Nishanth Menon <[email protected]>
+ *      Sunil Kumar <[email protected]>
+ *      Shashi Ranjan <[email protected]>
+ *      Richard Woodruff <[email protected]>
+ *      Syed Mohammed Khasim <[email protected]>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "zoom3.h"
+#include "zoom3_serial.h"
+
+
+/*
+ * This is the zoom3, board specific, gpmc configuration for the
+ * quad uart on the debug board. The more general gpmc configurations
+ * are setup at the cpu level in vim arch/arm/cpu/armv7/omap3/mem.c
+ *
+ * The details of the setting of the serial gpmc setup are not available.
+ * The values were provided by another party.
+ */
+static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = {
+	0x00011000,
+	0x001f1f01,
+	0x00080803,
+	0x1d091d09,
+	0x041f1f1f,
+	0x1d0904c4, 0
+};
+
+/* Used to track the revision of the board */
+static zoom3_revision revision = ZOOM3_REVISION_UNKNOWN;
+
+/*
+ * Routine: zoom3_get_version
+ * Description: Return the revision of the Zoom3 this code is running on.
+ */
+zoom3_revision zoom3_get_revision(void)
+{
+	return revision;
+}
+
+/*
+ * Routine: zoom3_identify
+ * Description: Detect which version of Zoom3 we are running on.
+ */
+void zoom3_identify(void)
+{
+	/*
+	 * To check for production board vs beta board,
+	 * check if gpio 94 is clear.
+	 *
+	 * No way yet to check for alpha board identity.
+	 * Alpha boards were produced in very limited quantities
+	 * and they are not commonly used. The are mentioned here
+	 * only for completeness.
+	 */
+	if (!omap_request_gpio(94)) {
+		unsigned int val;
+
+		omap_set_gpio_direction(94, 1);
+		val = omap_get_gpio_datain(94);
+		omap_free_gpio(94);
+
+		if (val)
+			revision = ZOOM3_REVISION_BETA;
+		else
+			revision = ZOOM3_REVISION_PRODUCTION;
+	}
+
+	puts("Board revision ");
+
+	switch (revision) {
+	case ZOOM3_REVISION_PRODUCTION:
+		puts("Production\n");
+		break;
+	case ZOOM3_REVISION_BETA:
+		puts("Beta\n");
+		break;
+	default:
+		puts("Unknown\n");
+		break;
+	}
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	u32 *gpmc_config;
+
+	gpmc_init();		/* in SRAM or SDRAM, finish GPMC */
+
+	/* Configure console support for zoom3 */
+	gpmc_config = gpmc_serial_TL16CP754C;
+	enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3],
+			SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
+
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM3;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP36XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure zoom board specific configurations
+ */
+int misc_init_r(void)
+{
+	zoom3_identify();
+	#if (CONFIG_TWL4030_POWER)
+	twl4030_power_init();
+	twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
+	#endif
+	dieid_num_r();
+
+	/*
+	 * Board reset
+	 * The board is reset by holding the large button
+	 * on the top right side of the main board
+	 * for eight seconds
+	 *
+	 * There are reported problems of some beta boards
+	 * continously resetting. For those boards, disable resetting.
+	 */
+	#if (CONFIG_TWL4030_POWER)
+	if (ZOOM3_REVISION_PRODUCTION <= zoom3_get_revision())
+		twl4030_power_reset_init();
+	#endif
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuratino Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	/* platform specific muxes */
+	MUX_ZOOM3();
+}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_LAN91C96
+	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
+#endif
+	return rc;
+}
+#endif

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+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef ZOOM3_SERIAL_H
+#define ZOOM3_SERIAL_H
+
+extern int zoom3_debug_board_connected(void);
+
+#define SERIAL_TL16CP754C_BASE	0x10000000	/* Zoom3 serial chip address */
+
+#define QUAD_BASE_0	SERIAL_TL16CP754C_BASE
+#define QUAD_BASE_1	(SERIAL_TL16CP754C_BASE + 0x100)
+#define QUAD_BASE_2	(SERIAL_TL16CP754C_BASE + 0x200)
+#define QUAD_BASE_3	(SERIAL_TL16CP754C_BASE + 0x300)
+
+#define S(a) #a
+#define N(a) S(quad##a)
+#define U(a) S(UART##a)
+
+#define QUAD_INIT(n)				\
+int quad_init_##n(void)				\
+{						\
+	return quad_init_dev(QUAD_BASE_##n);	\
+}						\
+void quad_setbrg_##n(void)			\
+{						\
+	quad_setbrg_dev(QUAD_BASE_##n);		\
+}						\
+void quad_putc_##n(const char c)		\
+{						\
+	quad_putc_dev(QUAD_BASE_##n, c);	\
+}						\
+void quad_puts_##n(const char *s)		\
+{						\
+	quad_puts_dev(QUAD_BASE_##n, s);	\
+}						\
+int quad_getc_##n(void)				\
+{						\
+	return quad_getc_dev(QUAD_BASE_##n);	\
+}						\
+int quad_tstc_##n(void)				\
+{						\
+	return quad_tstc_dev(QUAD_BASE_##n);	\
+}						\
+struct serial_device zoom3_serial_device##n =	\
+{						\
+	N(n),					\
+	U(n),					\
+	quad_init_##n,				\
+	NULL,					\
+	quad_setbrg_##n,			\
+	quad_getc_##n,				\
+	quad_tstc_##n,				\
+	quad_putc_##n,				\
+	quad_puts_##n,				\
+};
+
+#endif	/* ZOOM3_SERIAL_H */

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+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <[email protected]>
+ * Aldo Cedillo <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This file was adapted from arch/powerpc/cpu/mpc5xxx/serial.c
+ *
+ */
+
+#include <common.h>
+#include <serial.h>
+#include <ns16550.h>
+#include <asm/arch/cpu.h>
+#include "zoom3_serial.h"
+
+int quad_init_dev(unsigned long base)
+{
+	/*
+	 * The Quad UART is on the debug board.
+	 * Check if the debug board is attached before using the UART
+	 */
+	if (zoom3_debug_board_connected()) {
+		NS16550_t com_port = (NS16550_t) base;
+		int baud_divisor = CONFIG_SYS_NS16550_CLK / 16 /
+			CONFIG_BAUDRATE;
+		/*
+		 * Zoom3 has a board specific initialization of its UART.
+		 * This generic initialization has been copied from
+		 * drivers/serial/ns16550.c. The macros have been expanded.
+		 *
+		 * Do the following instead of
+		 * NS16550_init (com_port, clock_divisor);
+		 */
+		com_port->ier = 0x00;
+
+		/*
+		 * On Zoom3 board Set pre-scalar to 1
+		 * CLKSEL is GND => MCR[7] is 1 => preslr is 4
+		 * So change the prescl to 1
+		 */
+		com_port->lcr = 0xbf;
+		com_port->fcr |= 0x10;
+		com_port->mcr &= 0x7f;
+
+		/* This is generic ns16550.c setup */
+		com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
+		com_port->dll = 0;
+		com_port->dlm = 0;
+		com_port->lcr = UART_LCR_8N1;
+		com_port->mcr = UART_MCR_DTR | UART_MCR_RTS;
+		com_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR |
+			UART_FCR_TXSR;
+		com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
+		com_port->dll = baud_divisor & 0xff;
+		com_port->dlm = (baud_divisor >> 8) & 0xff;
+		com_port->lcr = UART_LCR_8N1;
+	}
+
+	/*
+	 * We have to lie here, otherwise the board init code will hang
+	 * on the check
+	 */
+	return 0;
+}
+
+void quad_putc_dev(unsigned long base, const char c)
+{
+	if (zoom3_debug_board_connected()) {
+		if (c == '\n')
+			quad_putc_dev(base, '\r');
+
+		NS16550_putc((NS16550_t) base, c);
+	} else {
+		usbtty_putc(c);
+	}
+}
+
+void quad_puts_dev(unsigned long base, const char *s)
+{
+	if (zoom3_debug_board_connected()) {
+		while ((s != NULL) && (*s != '\0'))
+			quad_putc_dev(base, *s++);
+	} else {
+		usbtty_puts(s);
+	}
+}
+
+int quad_getc_dev(unsigned long base)
+{
+	if (zoom3_debug_board_connected())
+		return NS16550_getc((NS16550_t) base);
+
+	return usbtty_getc();
+}
+
+int quad_tstc_dev(unsigned long base)
+{
+	if (zoom3_debug_board_connected())
+		return NS16550_tstc((NS16550_t) base);
+
+	return usbtty_tstc();
+}
+
+void quad_setbrg_dev(unsigned long base)
+{
+	if (zoom3_debug_board_connected()) {
+		int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 /
+			CONFIG_BAUDRATE;
+
+		NS16550_reinit((NS16550_t) base, clock_divisor);
+	}
+}
+
+QUAD_INIT(0)
+QUAD_INIT(1)
+QUAD_INIT(2)
+QUAD_INIT(3)

new file mode 100644
index 0000000..1871d79
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+
+static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
+
+/*
+ * GPIO LEDs
+ * 173 red
+ * 154 blue
+ * 61  blue2
+ */
+#define ZOOM3_LED_RED	173
+#define ZOOM3_LED_BLUE	154
+#define ZOOM3_LED_BLUE2	61
+
+void red_LED_off(void)
+{
+	/* red */
+	if (!omap_request_gpio(ZOOM3_LED_RED)) {
+		omap_set_gpio_direction(ZOOM3_LED_RED, 0);
+		omap_set_gpio_dataout(ZOOM3_LED_RED, 0);
+	}
+
+	saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
+}
+
+void blue_LED_off(void)
+{
+	/* blue */
+	if (!omap_request_gpio(ZOOM3_LED_BLUE)) {
+		omap_set_gpio_direction(ZOOM3_LED_BLUE, 0);
+		omap_set_gpio_dataout(ZOOM3_LED_BLUE, 0);
+	}
+
+	/* blue 2 */
+	if (!omap_request_gpio(ZOOM3_LED_BLUE2)) {
+		omap_set_gpio_direction(ZOOM3_LED_BLUE2, 0);
+		omap_set_gpio_dataout(ZOOM3_LED_BLUE2, 0);
+	}
+
+	saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
+}
+
+void red_LED_on(void)
+{
+	blue_LED_off();
+
+	/* red */
+	if (!omap_request_gpio(ZOOM3_LED_RED)) {
+		omap_set_gpio_direction(ZOOM3_LED_RED, 0);
+		omap_set_gpio_dataout(ZOOM3_LED_RED, 1);
+	}
+
+	saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
+}
+
+void blue_LED_on(void)
+{
+	red_LED_off();
+
+	/* blue */
+	if (!omap_request_gpio(ZOOM3_LED_BLUE)) {
+		omap_set_gpio_direction(ZOOM3_LED_BLUE, 0);
+		omap_set_gpio_dataout(ZOOM3_LED_BLUE, 1);
+	}
+
+	/* blue 2 */
+	if (!omap_request_gpio(ZOOM3_LED_BLUE2)) {
+		omap_set_gpio_direction(ZOOM3_LED_BLUE2, 0);
+		omap_set_gpio_dataout(ZOOM3_LED_BLUE2, 1);
+	}
+
+	saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
+}
+
+void __led_init(led_id_t mask, int state)
+{
+	__led_set(mask, state);
+}
+
+void __led_toggle(led_id_t mask)
+{
+	if (STATUS_LED_BLUE == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
+			blue_LED_off();
+		else
+			blue_LED_on();
+	} else if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+			red_LED_off();
+		else
+			red_LED_on();
+	}
+}
+
+void __led_set(led_id_t mask, int state)
+{
+	if (STATUS_LED_BLUE == mask) {
+		if (STATUS_LED_ON == state)
+			blue_LED_on();
+		else
+			blue_LED_off();
+	} else if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == state)
+			red_LED_on();
+		else
+			red_LED_off();
+	}
+}

new file mode 100644
index 0000000..0520257
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2010 Wind River Systems, Inc.
+ * Tom Rix <[email protected]>
+ * Aldo Cedillo <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/gpio.h>
+
+#define DEBUG_BOARD_CONNECTED		1
+#define DEBUG_BOARD_NOT_CONNECTED	0
+
+static int debug_board_connected = DEBUG_BOARD_CONNECTED;
+
+static void zoom3_debug_board_detect(void)
+{
+	int val = 0;
+
+	/*
+	 * TODO gpio 158 is UART1_RX, should we make a macro of this
+	 * instead of the raw number?
+	 */
+	if (!omap_request_gpio(158)) {
+		/*
+		 * GPIO to query for debug board
+		 * 158 db board query
+		 */
+		omap_set_gpio_direction(158, 1);
+		val = omap_get_gpio_datain(158);
+		omap_free_gpio(158);
+	}
+
+	if (!val)
+		debug_board_connected = DEBUG_BOARD_NOT_CONNECTED;
+}
+
+int zoom3_debug_board_connected(void)
+{
+	static int first_time = 1;
+
+	if (first_time) {
+		zoom3_debug_board_detect();
+		first_time = 0;
+	}
+
+	return debug_board_connected;
+}

new file mode 100644
index 0000000..e70f1cf
@@ -0,0 +1,271 @@
+/*
+ * (C) Copyright 2006-2010 Texas Instruments.
+ *
+ * Richard Woodruff <[email protected]>
+ * Syed Mohammed Khasim <[email protected]>
+ * Nishanth Menon <[email protected]>
+ * Tom Rix <[email protected]>
+ * Aldo Cedillo <[email protected]>
+ *
+ * Configuration settings for the TI OMAP3630 Zoom 3 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP36XX		1	/* which is a 36XX */
+#define CONFIG_OMAP3_ZOOM3	1	/* working with a Zoom3 */
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock defines */
+#define V_OSCK			2600000		/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ		/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ * Zoom3 uses the TL16CP754C on the debug board
+ */
+#define CONFIG_SERIAL_MULTI		1
+
+/*
+ * 0 - 1 : first USB with respect to the left edge of the debug board
+ * 2 - 3 : second USB with respect to the left edge of the debug board
+ */
+#define ZOOM3_DEFAULT_SERIAL_DEVICE	(&zoom3_serial_device0)
+
+#define V_NS16550_CLK			(1843200)	/* 1.8432 Mhz */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_REG_SIZE	(-2)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200}
+
+#define CONFIG_ENV_OVERWRITE	/* allow to overwrite serial and ethaddr */
+
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* DDR - Use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR		1
+
+/* Status LED */
+#define CONFIG_STATUS_LED		1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED	1
+#define STATUS_LED_BLUE			0 /* Check what color is used	*/
+#define STATUS_LED_RED			1 /* when using 3630		*/
+/* Blue */
+#define STATUS_LED_BIT			STATUS_LED_BLUE
+#define STATUS_LED_STATE		STATUS_LED_ON
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+/* Red */
+#define STATUS_LED_BIT1			STATUS_LED_RED
+#define STATUS_LED_STATE1		STATUS_LED_OFF
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
+/* Optional value */
+#define STATUS_LED_BOOT			STATUS_LED_BIT
+
+/* GPIO banks */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_OMAP3_GPIO_2	/* ZOOM2_LED_BLUE2 */
+#define CONFIG_OMAP3_GPIO_6	/* ZOOM2_LED_RED */
+#endif
+#define CONFIG_OMAP3_GPIO_3	/* board revision */
+#define CONFIG_OMAP3_GPIO_5	/* debug board detection, ZOOM2_LED_BLUE */
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"Zoom3"
+
+/* Commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT			/* FAT support			*/
+#undef CONFIG_CMD_I2C			/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC			/* MMC support			*/
+#define CONFIG_CMD_NAND			/* NAND support			*/
+#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* Enable lock/unlock support	*/
+
+#undef CONFIG_CMD_FLASH			/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA			/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI			/* iminfo			*/
+#undef CONFIG_CMD_IMLS			/* List all found images	*/
+#undef CONFIG_CMD_NET			/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_NFS			/* NFS support			*/
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * Board NAND info
+ */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE  /* physical address	*/
+						   /* to access nand	*/
+#define CONFIG_SYS_NAND_BASE		NAND_BASE  /* physical address	*/
+						   /* to access nand at	*/
+						   /* CS0		*/
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		10
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"usbtty=cdc_acm\0"		\
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_PROMPT		"OMAP3 Zoom3 #"
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* Memset from start of memory to 31MB */
+#define OMAP36XX_SDRC_CS0       OMAP34XX_SDRC_CS0 /* It's the same as in 34XX */
+#define CONFIG_SYS_MEMTEST_START	(OMAP36XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP36XX_SDRC_CS0 + 0x01f00000)
+/* The default load address is the start of memory */
+#define CONFIG_SYS_LOAD_ADDR		(OMAP36XX_SDRC_CS0)
+/* Everything, incl board info, in Hz */
+#undef CONFIG_SYS_CLKS_IN_HZ
+
+/*
+ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define OMAP36XX_GPT2           OMAP34XX_GPT2 /* It's the same as in 34XX */
+#define CONFIG_SYS_TIMERBASE		(OMAP36XX_GPT2)
+#define CONFIG_SYS_PTV			7	/* 2^(PTV+1) */
+#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PTV))
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using these settings
+ */
+#define CONFIG_STACKSIZE		(128 << 10)  /* regular stack 128KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ		(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ		(4 << 10)	/* FIQ stack 4 KiB */
+#endif
+
+/*
+ * Physical memory map
+ */
+#define CONFIG_NR_DRAM_BANKS		2	/* CS1 may or may not	*/
+						/* be populated		*/
+#define PHYS_SDRAM_1			OMAP36XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE		(32 << 20)
+#define PHYS_SDRAM_2			OMAP36XX_SDRC_CS1
+
+/* SDRAM bank allocation method */
+#define SDRC_R_B_C
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT **** */
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520  /* max number of sectors on  */
+					     /* one chip		  */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2    /* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10) /* Reserve 2 sectors  */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x0c0000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+/*
+ * CFI FLASH driver setup
+ */
+/* timout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+#ifndef __ASSEMBLY__
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_blash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */
+

index fceabfa..2a644ba 100644
@@ -92,6 +92,8 @@ struct serial_device *__default_serial_console (void)
 #endif
 #elif defined(CONFIG_OMAP3_ZOOM2)
 		return ZOOM2_DEFAULT_SERIAL_DEVICE;
+#elif defined(CONFIG_OMAP3_ZOOM3)
+		return ZOOM3_DEFAULT_SERIAL_DEVICE;
 #else
 #error No default console
 #endif

index 6513d8e..236e5d1 100644
@@ -66,6 +66,13 @@ extern struct serial_device zoom2_serial_device2;
 extern struct serial_device zoom2_serial_device3;
 #endif
 
+#if defined(CONFIG_OMAP3_ZOOM3)
+extern struct serial_device zoom3_serial_device0;
+extern struct serial_device zoom3_serial_device1;
+extern struct serial_device zoom3_serial_device2;
+extern struct serial_device zoom3_serial_device3;
+#endif
+
 extern struct serial_device serial_ffuart_device;
 extern struct serial_device serial_btuart_device;
 extern struct serial_device serial_stuart_device;