powerpc/p1021mds: add QE and UEC support

PATCH New Haiying Wang 1 participant 1 message Aug 16, 2010 PowerPC

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Haiying Wang

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2010-08-16 08:25 UTC #0 lore raw

PATCH 7/7 powerpc/p1021mds: add QE and UEC support

P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal.

Signed-off-by Haiying Wang <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/speed.c      |    4 ++
 arch/powerpc/include/asm/immap_85xx.h |   13 ++++++++
 board/freescale/p1021mds/p1021mds.c   |   54 +++++++++++++++++++++++++++++++++
 drivers/qe/uec.c                      |   36 ++++++++++++++++++++++
 include/configs/P1021MDS.h            |   44 ++++++++++++++++++++++++++
 5 files changed, 151 insertions(+), 0 deletions(-)

arch/powerpc/cpu/mpc85xx/speed.c +4 -0

index dd4c6b3..6f1aa7b 100644
@@ -163,10 +163,14 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 
 #ifdef CONFIG_QE
+#ifdef CONFIG_P1021
+	sysInfo->freqQE =  sysInfo->freqSystemBus;
+#else
 	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
 			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
 	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
 #endif
+#endif
 
 #if defined(CONFIG_SYS_LBC_LCRR)
 	/* We will program LCRR to this value later */

arch/powerpc/include/asm/immap_85xx.h +13 -0

index 5eeb93a..896014b 100644
@@ -1923,6 +1923,19 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SD_DATA		0x80000000
 #define MPC85xx_PMUXCR_SDHC_CD		0x40000000
 #define MPC85xx_PMUXCR_SDHC_WP		0x20000000
+#define MPC85xx_PMUXCR_QE0             0x00008000
+#define MPC85xx_PMUXCR_QE1             0x00004000
+#define MPC85xx_PMUXCR_QE2             0x00002000
+#define MPC85xx_PMUXCR_QE3             0x00001000
+#define MPC85xx_PMUXCR_QE4             0x00000800
+#define MPC85xx_PMUXCR_QE5             0x00000400
+#define MPC85xx_PMUXCR_QE6             0x00000200
+#define MPC85xx_PMUXCR_QE7             0x00000100
+#define MPC85xx_PMUXCR_QE8             0x00000080
+#define MPC85xx_PMUXCR_QE9             0x00000040
+#define MPC85xx_PMUXCR_QE10            0x00000020
+#define MPC85xx_PMUXCR_QE11            0x00000010
+#define MPC85xx_PMUXCR_QE12            0x00000008
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
 	u8	res6[8];
 	u32	devdisr;	/* Device disable control */

board/freescale/p1021mds/p1021mds.c +54 -0

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drivers/qe/uec.c +36 -0

index ccbf27d..e434564 100644
@@ -30,6 +30,9 @@
 #include "uec.h"
 #include "uec_phy.h"
 #include "miiphy.h"
+#ifdef CONFIG_P1021
+#include "../../board/freescale/p1021mds/bcsr.h"
+#endif
 
 /* Default UTBIPAR SMI address */
 #ifndef CONFIG_UTBIPAR_INIT_TBIPA

@@ -588,9 +591,25 @@ static void phy_change(struct eth_device *dev)
 {
 	uec_private_t	*uec = (uec_private_t *)dev->priv;
 
+#ifdef CONFIG_P1021
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* QE9 and QE12 need to be set for enabling QE MII managment signals */
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
 	/* Update the link, speed, duplex */
 	uec->mii_info->phyinfo->read_status(uec->mii_info);
 
+#ifdef CONFIG_P1021
+	/*
+	 * QE12 is muxed with LBCTL, it needs to be released for enabling
+	 * LBCTL signal for LBC usage.
+	 */
+	clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
 	/* Adjust the interface according to speed */
 	adjust_link(dev);
 }

@@ -1198,10 +1217,22 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
 	uec_private_t		*uec;
 	int			err, i;
 	struct phy_info         *curphy;
+#ifdef CONFIG_P1021
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
 
 	uec = (uec_private_t *)dev->priv;
 
 	if (uec->the_first_run == 0) {
+#ifdef CONFIG_P1021
+	/* reset micrel phy for each UEC */
+	reset_p1021mds_micrel_phy();
+
+	/* QE9 and QE12 need to be set for enabling QE MII managment signals */
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
+	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
 		err = init_phy(dev);
 		if (err) {
 			printf("%s: Cannot initialize PHY, aborting.\n",

@@ -1226,6 +1257,11 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
 			udelay(100000);
 		} while (((i-- > 0) && !uec->mii_info->link) || err);
 
+#ifdef CONFIG_P1021
+		/* QE12 needs to be released for enabling LBCTL signal*/
+		clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
+#endif
+
 		if (err || i <= 0)
 			printf("warning: %s: timeout on PHY link\n", dev->name);

include/configs/P1021MDS.h +44 -0

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