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agp/intel: use #ifdef idiom for intel-agp.h

PATCH New Zhenyu Wang 1 participant 3 messages Aug 27, 2010

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DRM drivers Intel i915 Agpgart driver
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Zhenyu Wang

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#0 lore raw

PATCH 1/3 agp/intel: use #ifdef idiom for intel-agp.h

Signed-off-by Zhenyu Wang <[email protected]>
---
 drivers/char/agp/intel-agp.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)
drivers/char/agp/intel-agp.h +4 -0
index 08d4753..78124a8 100644
@@ -1,6 +1,8 @@
 /*
  * Common Intel AGPGART and GTT definitions.
  */
+#ifndef _INTEL_AGP_H
+#define _INTEL_AGP_H
 
 /* Intel registers */
 #define INTEL_APSIZE	0xb4

@@ -244,3 +246,5 @@
 		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
 		agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
 		IS_SNB)
+
+#endif
Signature · 1 line
1.7.0.4
author
#1 lore raw

PATCH 2/3 agp/intel: add new intel-gtt.h for new GTT controls

New intel gfx device requires new GTT controls. Add them into under kernel include dir to be shared with drm/i915 driver.

Signed-off-by Zhenyu Wang <[email protected]>
---
 include/linux/intel-gtt.h |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/intel-gtt.h
include/linux/intel-gtt.h new file +20 -0
new file mode 100644
index 0000000..1d19ab2
@@ -0,0 +1,20 @@
+/*
+ * Common Intel AGPGART and GTT definitions.
+ */
+#ifndef _INTEL_GTT_H
+#define _INTEL_GTT_H
+
+#include <linux/agp_backend.h>
+
+/* This is for Intel only GTT controls.
+ *
+ * Sandybridge: AGP_USER_CACHED_MEMORY default to LLC only
+ */
+
+#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2)
+#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4)
+
+/* flag for GFDT type */
+#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
+
+#endif
Signature · 1 line
1.7.0.4
author
#2 lore raw

PATCH 3/3 agp/intel: Fix cache control for Sandybridge

In reply to Zhenyu Wang

Sandybridge GTT has new cache control bits in PTE, which controls graphics page cache in LLC or LLC/MLC. This one trys to use new type mask function for that. And this sets cache control to always LLC only by default on Gen6.

Signed-off-by Zhenyu Wang <[email protected]>
---
 drivers/char/agp/intel-agp.c    |    1 +
 drivers/char/agp/intel-gtt.c    |   50 +++++++++++++++++++++++++++++++-------
 drivers/gpu/drm/i915/i915_gem.c |    1 +
 3 files changed, 42 insertions(+), 10 deletions(-)
drivers/char/agp/intel-agp.c +1 -0
index 710af89..74461d1 100644
@@ -12,6 +12,7 @@
 #include <asm/smp.h>
 #include "agp.h"
 #include "intel-agp.h"
+#include <linux/intel-gtt.h>
 
 #include "intel-gtt.c"
drivers/char/agp/intel-gtt.c +40 -10

86 lines not on this page · raw message

drivers/gpu/drm/i915/i915_gem.c +1 -0
index df5a713..8ccb55a 100644
@@ -34,6 +34,7 @@
 #include <linux/slab.h>
 #include <linux/swap.h>
 #include <linux/pci.h>
+#include <linux/intel-gtt.h>
 
 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
Signature · 1 line
1.7.0.4