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perf: Use MSR names in the extra reg lists

PATCH In review Lin Ming 2 participants 2 messages Dec 27, 2010 – Jan 4, 2011

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x86 perf events
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Lin Ming

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#0 lore raw

PATCH 6/7 perf: Use MSR names in the extra reg lists

MSR names is much more readable.

Signed-off-by Lin Ming <[email protected]>
---
 arch/x86/include/asm/msr-index.h       |    3 +++
 arch/x86/kernel/cpu/perf_event_intel.c |    9 ++++++---
 2 files changed, 9 insertions(+), 3 deletions(-)
arch/x86/include/asm/msr-index.h +3 -0
index 6b89f5e..c3c42b1 100644
@@ -47,6 +47,9 @@
 #define MSR_IA32_MCG_STATUS		0x0000017a
 #define MSR_IA32_MCG_CTL		0x0000017b
 
+#define MSR_OFFCORE_RSP_0		0x000001a6
+#define MSR_OFFCORE_RSP_1		0x000001a7
+
 #define MSR_IA32_PEBS_ENABLE		0x000003f1
 #define MSR_IA32_DS_AREA		0x00000600
 #define MSR_IA32_PERF_CAPABILITIES	0x00000345
arch/x86/kernel/cpu/perf_event_intel.c +6 -3
index ad70c2c..0a67425 100644
@@ -88,7 +88,8 @@ static struct event_constraint intel_nehalem_event_constraints[] =
 
 static struct extra_reg intel_nehalem_extra_regs[] =
 {
-	INTEL_EVENT_EXTRA_REG(0xb7, 0x1a6, 0xffff, 32), /* OFFCORE_RESPONSE */
+	/* OFFCORE_RESPONSE */
+	INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, 32),
 	EVENT_EXTRA_END
 };
 

@@ -112,8 +113,10 @@ static struct event_constraint intel_westmere_event_constraints[] =
 
 static struct extra_reg intel_westmere_extra_regs[] =
 {
-	INTEL_EVENT_EXTRA_REG(0xb7, 0x1a6, 0xffff, 32), /* OFFCORE_RESPONSE_0 */
-	INTEL_EVENT_EXTRA_REG(0xbb, 0x1a7, 0xffff, 32), /* OFFCORE_RESPONSE_1 */
+	/* OFFCORE_RESPONSE_0 */
+	INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, 32),
+	/* OFFCORE_RESPONSE_1 */
+	INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, 32),
 	EVENT_EXTRA_END
 };
Signature · 1 line
1.7.3
#1 lore raw

arch/x86/kernel/cpu/perf_event_intel.c static struct event_constraint intel_nehalem_event_constraints[] = · line 94

Quoted 9 lines · Lin Ming
arch/x86/kernel/cpu/perf_event_intel.c +2 -1
@@ -88,7 +88,8 @@ static struct event_constraint intel_nehalem_event_constraints[] =
 
 static struct extra_reg intel_nehalem_extra_regs[] =
 {
-       INTEL_EVENT_EXTRA_REG(0xb7, 0x1a6, 0xffff, 32), /* OFFCORE_RESPONSE */
+       /* OFFCORE_RESPONSE */
+       INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, 32),
        EVENT_EXTRA_END
 };

Since we're going for another posting anyway, I think you can drop that comment here, it should be evident from the MSR name included in the constraint.