perf, x86: Implement AMD IBS
Subsystems (2)
cover perf, x86: Implement AMD IBS
This patch set adds support for AMD IBS to perf. It is a new implementation and unrelated to my previous postings last year. The main differences are:
* separate and independent from x86 perfctrs, IBS could be used without the x86 pmu,
* using dynamic pmu allocation, userspace uses sysfs to select the pmu,
* support for 64 bit counters,
* libperf based example code,
* shared IBS initialziation code for perf and oprofile.
The approach is still to collect raw sample data which should be the most important use case for application developers. The data format is the same as described in the IBS register specification.
Future work could be:
* better integration into the perf tool, use IBS for generic events where possible,
* support of the precise event sampling perf i/f,
* implementation of extended IBS features (e.g. ext. counter width),
* support of counting (perf stat),
* in-kernel IBS event parsing,
* IBS tracepoint support.
Changes for V2:
* Remove printks in pmu function stubs.
* Modify perf_event_ibs_init() to use ibs_caps directly.
* Added bit mask for msr offsets.
* Added caps field to raw sample format.
* Added caps check for IBS_OP_CUR_CNT emulation.
* Updated include header files to fix build errors on some distros.
* Note: I kept example code for reference, the patch must not be applied. I will come up with a sulution that integrates IBS into perf-report.
-Robert
PATCH 1/7 perf, x86: share IBS macros between perf and oprofile
Moving IBS macros from oprofile to <asm/perf_event.h> to make it available to perf. No additional changes.
--- arch/x86/include/asm/perf_event.h | 38 +++++++++++++++++++++++++++++++-- arch/x86/kernel/cpu/perf_event_amd.c | 4 +- arch/x86/oprofile/op_model_amd.c | 37 ++------------------------------ 3 files changed, 40 insertions(+), 39 deletions(-)
arch/x86/include/asm/perf_event.h +35 -3
@@ -43,14 +43,17 @@#define AMD64_RAW_EVENT_MASK \ (X86_RAW_EVENT_MASK | \ AMD64_EVENTSEL_EVENT) +#define AMD64_NUM_COUNTERS 4 +#define AMD64_NUM_COUNTERS_F15H 6 +#define AMD64_NUM_COUNTERS_MAX AMD64_NUM_COUNTERS_F15H -#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c +#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) -#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0 +#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) -#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6 +#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6/* * Intel "Architectural Performance Monitoring" CPUID
@@ -110,6 +113,35 @@ union cpuid10_edx {*/ #define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) +/* +* IBS cpuid feature detection +*/ + +#define IBS_CPUID_FEATURES 0x8000001b + +/* +* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but +* bit 0 is used to indicate the existence of IBS. +*/ +#define IBS_CAPS_AVAIL (1U<<0) +#define IBS_CAPS_FETCHSAM (1U<<1) +#define IBS_CAPS_OPSAM (1U<<2) +#define IBS_CAPS_RDWROPCNT (1U<<3) +#define IBS_CAPS_OPCNT (1U<<4) +#define IBS_CAPS_BRNTRGT (1U<<5) +#define IBS_CAPS_OPCNTEXT (1U<<6) + +#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ + | IBS_CAPS_FETCHSAM \ + | IBS_CAPS_OPSAM) + +/* +* IBS APIC setup +*/ +#define IBSCTL 0x1cc +#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) +#define IBSCTL_LVT_OFFSET_MASK 0x0F +/* IbsFetchCtl bits/masks */ #define IBS_FETCH_RAND_EN (1ULL<<57)#define IBS_FETCH_VAL (1ULL<<49)
arch/x86/kernel/cpu/perf_event_amd.c +2 -2
@@ -392,7 +392,7 @@ static __initconst const struct x86_pmu amd_pmu = { .perfctr = MSR_K7_PERFCTR0, .event_map = amd_pmu_event_map, .max_events = ARRAY_SIZE(amd_perfmon_event_map), - .num_counters = 4, + .num_counters = AMD64_NUM_COUNTERS, .cntval_bits = 48, .cntval_mask = (1ULL << 48) - 1, .apic = 1,
@@ -556,7 +556,7 @@ static __initconst const struct x86_pmu amd_pmu_f15h = { .perfctr = MSR_F15H_PERF_CTR, .event_map = amd_pmu_event_map, .max_events = ARRAY_SIZE(amd_perfmon_event_map), - .num_counters = 6, + .num_counters = AMD64_NUM_COUNTERS_F15H, .cntval_bits = 48, .cntval_mask = (1ULL << 48) - 1, .apic = 1,
arch/x86/oprofile/op_model_amd.c +3 -34
@@ -29,8 +29,6 @@#include "op_x86_model.h" #include "op_counter.h" -#define NUM_COUNTERS 4 -#define NUM_COUNTERS_F15H 6#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX #define NUM_VIRT_COUNTERS 32#else
@@ -70,35 +68,6 @@ static struct ibs_config ibs_config;static struct ibs_state ibs_state;/* -* IBS cpuid feature detection -*/ - -#define IBS_CPUID_FEATURES 0x8000001b - -/* -* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but -* bit 0 is used to indicate the existence of IBS. -*/ -#define IBS_CAPS_AVAIL (1U<<0) -#define IBS_CAPS_FETCHSAM (1U<<1) -#define IBS_CAPS_OPSAM (1U<<2) -#define IBS_CAPS_RDWROPCNT (1U<<3) -#define IBS_CAPS_OPCNT (1U<<4) -#define IBS_CAPS_BRNTRGT (1U<<5) -#define IBS_CAPS_OPCNTEXT (1U<<6) - -#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ - | IBS_CAPS_FETCHSAM \ - | IBS_CAPS_OPSAM) - -/* -* IBS APIC setup -*/ -#define IBSCTL 0x1cc -#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) -#define IBSCTL_LVT_OFFSET_MASK 0x0F - -/* * IBS randomization macros */ #define IBS_RANDOM_BITS 12
@@ -439,7 +408,7 @@ static int op_amd_fill_in_addresses(struct op_msrs * const msrs) goto fail; }/* both registers must be reserved */ -if (num_counters ==NUM_COUNTERS_F15H ) { +if (num_counters ==AMD64_NUM_COUNTERS_F15H ) { msrs->counters[i].addr =MSR_F15H_PERF_CTR + (i <<1 ); msrs->controls[i].addr =MSR_F15H_PERF_CTL + (i <<1 ); }else {
@@ -741,9 +710,9 @@ static int op_amd_init(struct oprofile_operations *ops) ops->create_files = setup_ibs_files;if (boot_cpu_data.x86 ==0x15 ) { - num_counters =NUM_COUNTERS_F15H ; + num_counters =AMD64_NUM_COUNTERS_F15H ; }else { - num_counters =NUM_COUNTERS ; + num_counters =AMD64_NUM_COUNTERS ; } op_amd_spec.num_counters = num_counters;
Signature · 1 line
1.7.6.1
PATCH 2/7 perf, x86: Implement IBS initialization
In reply to Robert RichterThis patch implements IBS feature detection and initialzation. The code is shared between perf and oprofile. If ibs is available on the system for perf, a pmu is setup.
V2:
* Remove printks in pmu function stubs.
* Modify perf_event_ibs_init() to use ibs_caps directly.
--- arch/x86/include/asm/perf_event.h | 2 + arch/x86/kernel/cpu/Makefile | 2 +- arch/x86/kernel/cpu/perf_event_amd_ibs.c | 292 ++++++++++++++++++++++++++++++ arch/x86/oprofile/nmi_int.c | 2 - arch/x86/oprofile/op_model_amd.c | 197 -------------------- arch/x86/oprofile/op_x86_model.h | 1 - 6 files changed, 295 insertions(+), 201 deletions(-) create mode 100644 arch/x86/kernel/cpu/perf_event_amd_ibs.c
arch/x86/include/asm/perf_event.h +2 -0
@@ -156,6 +156,8 @@ union cpuid10_edx {#define IBS_OP_MAX_CNT 0x0000FFFFULL#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL/* not a register bit mask */ +extern u32 get_ibs_caps (void ); +#ifdef CONFIG_PERF_EVENTS extern void perf_events_lapic_init (void );
arch/x86/kernel/cpu/Makefile +1 -1
@@ -31,7 +31,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o obj-$(CONFIG_X86_MCE) += mcheck/ obj-$(CONFIG_MTRR) += mtrr/ -obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o +obj-$(CONFIG_X86_LOCAL_APIC) += perfctr-watchdog.o perf_event_amd_ibs.o quiet_cmd_mkcapflags = MKCAP $@ cmd_mkcapflags = $(PERL) $(srctree)/$(src)/mkcapflags.pl $< $@
arch/x86/kernel/cpu/perf_event_amd_ibs.c new file +292 -0
292 lines not on this page · raw message
arch/x86/oprofile/nmi_int.c +0 -2
@@ -385,8 +385,6 @@ static void nmi_cpu_shutdown(void *dummy)apic_write (APIC_LVTPC ,per_cpu (saved_lvtpc, cpu));apic_write (APIC_LVTERR , v);nmi_cpu_restore_registers (msrs); -if (model->cpu_down) - model->cpu_down (); }static void nmi_cpu_up (void *dummy)
arch/x86/oprofile/op_model_amd.c +0 -197
233 lines not on this page · raw message
arch/x86/oprofile/op_x86_model.h +0 -1
@@ -43,7 +43,6 @@ struct op_x86_model_spec {int (*fill_in_addresses)(struct op_msrs *const msrs);void (*setup_ctrs)(struct op_x86_model_spec const *model,struct op_msrs const *const msrs); -void (*cpu_down)(void );int (*check_ctrs)(struct pt_regs *const regs,struct op_msrs const *const msrs);void (*start)(struct op_msrs const *const msrs);
Signature · 1 line
1.7.6.1
PATCH 3/7 perf, x86: Implement IBS event configuration
In reply to Robert RichterThis patch implements perf configuration for AMD IBS. The IBS pmu is selected using the type attribute in sysfs. There are two types of ibs pmus, for instruction fetch (IBS_FETCH) and for instruction execution (IBS_OP):
/sys/bus/event_source/devices/ibs_fetch/type
/sys/bus/event_source/devices/ibs_op/type
Except for the sample period IBS can only be set up with raw config values and raw data samples. The event attributes for the syscall should be programmed like this (IBS_FETCH):
type = get_pmu_type("/sys/bus/event_source/devices/ibs_fetch/type");
memset(&attr, 0, sizeof(attr));
attr.type = type;
attr.sample_type = PERF_SAMPLE_CPU | PERF_SAMPLE_RAW;
attr.config = IBS_FETCH_CONFIG_DEFAULT;This implementation does not yet support 64 bit counters. It is limited to the hardware counter bit width which is 20 bits. 64 bit support can be added later.
--- arch/x86/kernel/cpu/perf_event_amd_ibs.c | 88 +++++++++++++++++++++++++++--- 1 files changed, 81 insertions(+), 7 deletions(-)
arch/x86/kernel/cpu/perf_event_amd_ibs.c +81 -7
@@ -14,12 +14,67 @@ static u32 ibs_caps;#if defined(CONFIG_PERF_EVENTS ) && defined(CONFIG_CPU_SUP_AMD ) -static struct pmu perf_ibs; +#define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT) +#define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT + +struct perf_ibs { +struct pmu pmu; +unsigned int msr; +u64 config_mask; +u64 cnt_mask; +u64 enable_mask; +}; + +static struct perf_ibs perf_ibs_fetch; +static struct perf_ibs perf_ibs_op; + +static struct perf_ibs *get_ibs_pmu (int type) +{ +if (perf_ibs_fetch.pmu.type == type) +return &perf_ibs_fetch; +if (perf_ibs_op.pmu.type == type) +return &perf_ibs_op; +return NULL ; +}static int perf_ibs_init (struct perf_event *event) { -if (perf_ibs.type != event->attr.type) +struct hw_perf_event *hwc = &event->hw; +struct perf_ibs *perf_ibs; +u64 max_cnt, config; + + perf_ibs =get_ibs_pmu (event->attr.type); +if (!perf_ibs)return -ENOENT ; + + config = event->attr.config; +if (config & ~perf_ibs->config_mask) +return -EINVAL ; + +if (hwc->sample_period) { +if (config & perf_ibs->cnt_mask) +/* raw max_cnt may not be set */ +return -EINVAL ; +if (hwc->sample_period &0x0f ) +/* lower 4 bits can not be set in ibs max cnt */ +return -EINVAL ; + max_cnt = hwc->sample_period >>4 ; +if (max_cnt & ~perf_ibs->cnt_mask) +/* out of range */ +return -EINVAL ; + config |= max_cnt; + }else { + max_cnt = config & perf_ibs->cnt_mask; + event->attr.sample_period = max_cnt <<4 ; + hwc->sample_period = event->attr.sample_period; + } + +if (!max_cnt) +return -EINVAL ; + + hwc->config_base = perf_ibs->msr; + hwc->config = config; +return 0 ; }
@@ -32,10 +87,28 @@ static void perf_ibs_del(struct perf_event *event, int flags) { } -static struct pmu perf_ibs = { - .event_init= perf_ibs_init, - .add= perf_ibs_add, - .del= perf_ibs_del, +static struct perf_ibs perf_ibs_fetch = { + .pmu = { + .event_init = perf_ibs_init, + .add = perf_ibs_add, + .del = perf_ibs_del, + }, + .msr =MSR_AMD64_IBSFETCHCTL , + .config_mask =IBS_FETCH_CONFIG_MASK , + .cnt_mask =IBS_FETCH_MAX_CNT , + .enable_mask =IBS_FETCH_ENABLE , +}; + +static struct perf_ibs perf_ibs_op = { + .pmu = { + .event_init = perf_ibs_init, + .add = perf_ibs_add, + .del = perf_ibs_del, + }, + .msr =MSR_AMD64_IBSOPCTL , + .config_mask =IBS_OP_CONFIG_MASK , + .cnt_mask =IBS_OP_MAX_CNT , + .enable_mask =IBS_OP_ENABLE , };static __init int perf_event_ibs_init (void )
@@ -43,7 +116,8 @@ static __init int perf_event_ibs_init(void)if (!ibs_caps)return -ENODEV ;/* ibs not supported by the cpu */ -perf_pmu_register (&perf_ibs,"ibs" ,-1 ); +perf_pmu_register (&perf_ibs_fetch.pmu,"ibs_fetch" ,-1 ); +perf_pmu_register (&perf_ibs_op.pmu,"ibs_op" ,-1 );printk (KERN_INFO "perf: AMD IBS detected (0x%08x)\n" , ibs_caps);return 0 ;
Signature · 1 line
1.7.6.1
Peter Zijlstra
maintainerRe: [PATCH 3/7] perf, x86: Implement IBS event configuration
Quoted 13 lines · Robert Richter
arch/x86/kernel/cpu/perf_event_amd_ibs.c +13
-0+static struct perf_ibs perf_ibs_fetch = { + .pmu = { + .event_init = perf_ibs_init, + .add = perf_ibs_add, + .del = perf_ibs_del, + }, + .msr =MSR_AMD64_IBSFETCHCTL , + .config_mask =IBS_FETCH_CONFIG_MASK , + .cnt_mask =IBS_FETCH_MAX_CNT , + .enable_mask =IBS_FETCH_ENABLE , +}; + +static struct perf_ibs perf_ibs_op = {
arch/x86/kernel/cpu/perf_event_amd_ibs.c static void perf_ibs_del(struct perf_event *event, int flags) · line 112
Quoted 10 lines
arch/x86/kernel/cpu/perf_event_amd_ibs.c +9
-0+ .pmu = { + .event_init = perf_ibs_init, + .add = perf_ibs_add, + .del = perf_ibs_del, + }, + .msr = MSR_AMD64_IBSOPCTL, + .config_mask = IBS_OP_CONFIG_MASK, + .cnt_mask = IBS_OP_MAX_CNT, + .enable_mask = IBS_OP_ENABLE, };
Both those .pmu things want:
.task_ctx_nr = perf_invalid_context,
disabling per-task events, or you need to create a new context and somehow fix per-task scheduling for these two things.
Adding two task contexts (one for each type) really isn't nice.
PATCH 4/7 perf, x86: Implement IBS interrupt handler
In reply to Robert RichterThis patch implements code to handle ibs interrupts. If ibs data is available a raw perf_event data sample is created and sent back to the userland. This patch only implements the storage of ibs data in the raw sample, but this could be extended in a later patch by generating generic event data such as the rip from the ibs sampling data.
V2:
* Added bit mask for msr offsets.
* Added caps field to raw sample format.
* Rebase on Don's NMI patches that introduce register_nmi_handler().
--- arch/x86/include/asm/msr-index.h | 5 ++ arch/x86/kernel/cpu/perf_event_amd_ibs.c | 84 ++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+), 0 deletions(-)
arch/x86/include/asm/msr-index.h +5 -0
@@ -127,6 +127,8 @@#define MSR_AMD64_IBSFETCHCTL 0xc0011030#define MSR_AMD64_IBSFETCHLINAD 0xc0011031#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 +#define MSR_AMD64_IBSFETCH_REG_COUNT 3 +#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)#define MSR_AMD64_IBSOPCTL 0xc0011033#define MSR_AMD64_IBSOPRIP 0xc0011034#define MSR_AMD64_IBSOPDATA 0xc0011035
@@ -134,8 +136,11 @@#define MSR_AMD64_IBSOPDATA3 0xc0011037#define MSR_AMD64_IBSDCLINAD 0xc0011038#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 +#define MSR_AMD64_IBSOP_REG_COUNT 7 +#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)#define MSR_AMD64_IBSCTL 0xc001103a#define MSR_AMD64_IBSBRTARGET 0xc001103b +#define MSR_AMD64_IBS_REG_COUNT_MAX 8/* includes MSR_AMD64_IBSBRTARGET */ /* Fam 15h MSRs */ #define MSR_F15H_PERF_CTL 0xc0010200
arch/x86/kernel/cpu/perf_event_amd_ibs.c +84 -0
116 lines not on this page · raw message
Signature · 1 line
1.7.6.1
Peter Zijlstra
maintainerRe: [PATCH 4/7] perf, x86: Implement IBS interrupt handler
Quoted 5 lines · Robert Richter
arch/x86/kernel/cpu/perf_event_amd_ibs.c +5
-0+if (event->attr.sample_type &PERF_SAMPLE_RAW ) { + ibs_data.caps = ibs_caps; + size =1 ; + offset =1 ; + do {
arch/x86/kernel/cpu/perf_event_amd_ibs.c static struct perf_ibs perf_ibs_op = { · line 170
Quoted 10 lines
arch/x86/kernel/cpu/perf_event_amd_ibs.c +10
-0+rdmsrl (msr + offset, *buf++); + size++; + offset =find_next_bit (perf_ibs->offset_mask, + perf_ibs->offset_max, + offset +1 ); + }while (offset < perf_ibs->offset_max); + raw.size =sizeof (u32) +sizeof (u64) * size; + raw.data = ibs_data.data; + data.raw = &raw; + }
Another application of for_each_set_bit_continue() ?
Re: [PATCH 4/7] perf, x86: Implement IBS interrupt handler
Quoted 17 lines · Peter Zijlstra
Quoted 5 lines · Robert Richter
arch/x86/kernel/cpu/perf_event_amd_ibs.c +5
-0+if (event->attr.sample_type &PERF_SAMPLE_RAW ) { + ibs_data.caps = ibs_caps; + size =1 ; + offset =1 ; + do {arch/x86/kernel/cpu/perf_event_amd_ibs.c static struct perf_ibs perf_ibs_op = { · line 170
Quoted 10 lines
arch/x86/kernel/cpu/perf_event_amd_ibs.c +10
-0+rdmsrl (msr + offset, *buf++); + size++; + offset =find_next_bit (perf_ibs->offset_mask, + perf_ibs->offset_max, + offset +1 ); + }while (offset < perf_ibs->offset_max); + raw.size =sizeof (u32) +sizeof (u64) * size; + raw.data = ibs_data.data; + data.raw = &raw; + }
Quoted 1 line
Another application of
for_each_set_bit_continue()?
Peter, I will make this a separate patch set to decouple from this patch set. Will then update this code too. So in my next ibs patch set I wont change this here.
-Robert
Signature · 2 lines
Advanced Micro Devices, Inc. Operating System Research Center
PATCH 5/7 perf, x86: Implement IBS pmu control ops
In reply to Robert RichterAdd code to control the IBS pmu. We need to maintain per-cpu states. Since some states are used and changed by the nmi handler, access to these states must be atomic.
--- arch/x86/kernel/cpu/perf_event_amd_ibs.c | 106 +++++++++++++++++++++++++++++- 1 files changed, 103 insertions(+), 3 deletions(-)
arch/x86/kernel/cpu/perf_event_amd_ibs.c +103 -3
@@ -22,6 +22,19 @@ static u32 ibs_caps;#define IBS_FETCH_CONFIG_MASK (IBS_FETCH_RAND_EN | IBS_FETCH_MAX_CNT)#define IBS_OP_CONFIG_MASK IBS_OP_MAX_CNT +enum ibs_states { +IBS_ENABLED =0 , +IBS_STARTED =1 , +IBS_STOPPING =2 , + +IBS_MAX_STATES , +}; + +struct cpu_perf_ibs { +struct perf_event *event; +unsigned long state[BITS_TO_LONGS (IBS_MAX_STATES )]; +}; +struct perf_ibs {struct pmu pmu;unsigned int msr;
@@ -31,6 +44,7 @@ struct perf_ibs {u64 valid_mask;unsigned long offset_mask[1 ];int offset_max; +struct cpu_perf_ibs __percpu *pcpu; };struct perf_ibs_data {
@@ -95,20 +109,74 @@ static int perf_ibs_init(struct perf_event *event)return 0 ; } +static void perf_ibs_start (struct perf_event *event,int flags) +{ +struct hw_perf_event *hwc = &event->hw; + struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu); +struct cpu_perf_ibs *pcpu =this_cpu_ptr (perf_ibs->pcpu); + +if (test_and_set_bit (IBS_STARTED , pcpu->state)) +return ; + +wrmsrl (hwc->config_base, hwc->config | perf_ibs->enable_mask); +} + +static void perf_ibs_stop (struct perf_event *event,int flags) +{ +struct hw_perf_event *hwc = &event->hw; + struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu); +struct cpu_perf_ibs *pcpu =this_cpu_ptr (perf_ibs->pcpu); +u64 val; + +if (!test_and_clear_bit (IBS_STARTED , pcpu->state)) +return ; + +set_bit (IBS_STOPPING , pcpu->state); + +rdmsrl (hwc->config_base, val); + val &= ~perf_ibs->enable_mask; +wrmsrl (hwc->config_base, val); +} +static int perf_ibs_add (struct perf_event *event,int flags) { + struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu); +struct cpu_perf_ibs *pcpu =this_cpu_ptr (perf_ibs->pcpu); + +if (test_and_set_bit (IBS_ENABLED , pcpu->state)) +return -ENOSPC ; + + pcpu->event = event; + +if (flags &PERF_EF_START ) +perf_ibs_start (event,PERF_EF_RELOAD ); +return 0 ; }static void perf_ibs_del (struct perf_event *event,int flags) { + struct perf_ibs *perf_ibs = container_of(event->pmu, struct perf_ibs, pmu); +struct cpu_perf_ibs *pcpu =this_cpu_ptr (perf_ibs->pcpu); + +if (!test_and_clear_bit (IBS_ENABLED , pcpu->state)) +return ; + +perf_ibs_stop (event,0 ); + + pcpu->event =NULL ; } +static void perf_ibs_read (struct perf_event *event) { } +static struct perf_ibs perf_ibs_fetch = { .pmu = { .event_init = perf_ibs_init, .add = perf_ibs_add, .del = perf_ibs_del, + .start = perf_ibs_start, + .stop = perf_ibs_stop, + .read = perf_ibs_read, }, .msr =MSR_AMD64_IBSFETCHCTL , .config_mask =IBS_FETCH_CONFIG_MASK ,
@@ -124,6 +192,9 @@ static struct perf_ibs perf_ibs_op = { .event_init = perf_ibs_init, .add = perf_ibs_add, .del = perf_ibs_del, + .start = perf_ibs_start, + .stop = perf_ibs_stop, + .read = perf_ibs_read, }, .msr = MSR_AMD64_IBSOPCTL, .config_mask = IBS_OP_CONFIG_MASK,
@@ -136,7 +207,8 @@ static struct perf_ibs perf_ibs_op = {static int perf_ibs_handle_irq (struct perf_ibs *perf_ibs,struct pt_regs *iregs) { -struct perf_event *event =NULL ; +struct cpu_perf_ibs *pcpu =this_cpu_ptr (perf_ibs->pcpu); +struct perf_event *event = pcpu->event;struct hw_perf_event *hwc = &event->hw;struct perf_sample_data data;struct perf_raw_record raw;
@@ -146,6 +218,14 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)unsigned int msr;u64 *buf; +if (!test_bit (IBS_STARTED , pcpu->state)) { +/* Catch spurious interrupts after stopping IBS: */ +if (!test_and_clear_bit (IBS_STOPPING , pcpu->state)) +return 0 ; +rdmsrl (perf_ibs->msr, *ibs_data.regs); +return (*ibs_data.regs & perf_ibs->valid_mask); + } + msr = hwc->config_base; buf = ibs_data.regs;rdmsrl (msr, *buf);
@@ -194,13 +274,33 @@ perf_ibs_nmi_handler(unsigned int cmd, struct pt_regs *regs)return handled; } +static __init int perf_ibs_pmu_init (struct perf_ibs *perf_ibs,char *name) +{ +struct cpu_perf_ibs __percpu *pcpu; +int ret; + + pcpu = alloc_percpu(struct cpu_perf_ibs); +if (!pcpu) +return -ENOMEM ; + + perf_ibs->pcpu = pcpu; + + ret =perf_pmu_register (&perf_ibs->pmu, name,-1 ); +if (ret) { + perf_ibs->pcpu =NULL ; +free_percpu (pcpu); + } + +return ret; +} +static __init int perf_event_ibs_init (void ) {if (!ibs_caps)return -ENODEV ;/* ibs not supported by the cpu */ -perf_pmu_register (&perf_ibs_fetch.pmu,"ibs_fetch" ,-1 ); -perf_pmu_register (&perf_ibs_op.pmu,"ibs_op" ,-1 ); +perf_ibs_pmu_init (&perf_ibs_fetch,"ibs_fetch" ); +perf_ibs_pmu_init (&perf_ibs_op,"ibs_op" );register_nmi_handler (NMI_LOCAL , &perf_ibs_nmi_handler,0 ,"perf_ibs" );printk (KERN_INFO "perf: AMD IBS detected (0x%08x)\n" , ibs_caps);
Signature · 1 line
1.7.6.1
PATCH 6/7 perf, x86: Implement 64 bit counter support for IBS
In reply to Robert RichterThis patch implements 64 bit counter support for IBS. The sampling period is no longer limited to the hw counter width.
The functions perf_event_set_period() and perf_event_try_update() can be used as generic functions. They can replace similar code that is duplicate across architectures.
V2: Added caps check for IBS_OP_CUR_CNT emulation.
--- arch/x86/include/asm/perf_event.h | 2 + arch/x86/kernel/cpu/perf_event_amd_ibs.c | 204 +++++++++++++++++++++++++++--- 2 files changed, 185 insertions(+), 21 deletions(-)
arch/x86/include/asm/perf_event.h +2 -0
@@ -150,6 +150,8 @@ union cpuid10_edx {#define IBS_FETCH_MAX_CNT 0x0000FFFFULL/* IbsOpCtl bits */ +/* lower 4 bits of the current count are ignored: */ +#define IBS_OP_CUR_CNT (0xFFFF0ULL<<32)#define IBS_OP_CNT_CTL (1ULL<<19)#define IBS_OP_VAL (1ULL<<18)#define IBS_OP_ENABLE (1ULL<<17)
arch/x86/kernel/cpu/perf_event_amd_ibs.c +183 -21
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Signature · 1 line
1.7.6.1
PATCH 7/7 perf, x86: Example code for AMD IBS
In reply to Robert RichterThis patch includes an example to use IBS via perf_event.
usage: ibs [-h]
ibs ibs_fetch | ibs_op [-s] [-C CPU] [-m BUFFERPAGES] <command>
<command>
Command to execute.
-e CONFIG
64 bit configuration value, refers to msrs IbsFetchCtl (0xC0011030) or IbsOpCtl (0xC0011033). The default sample period is set to 100000.
-c COUNT
Event period to sample (default: 100000).
-h
Print help.
-s
system wide profiling (set per default)
-C CPU
profile on CPU (not yet implemented)
-m BUFFERPAGES
Per-cpu buffer pages to allocate.
V2:
* Updated include header files to fix build errors on some distros.
* Caps field added to sampling format.
* Note: I kept example code for reference, the patch must not be applied. I will come up with a sulution that integrates IBS into perf-report.
--- tools/perf/Documentation/examples/Makefile | 44 +++ tools/perf/Documentation/examples/ibs.c | 445 ++++++++++++++++++++++++++++ 2 files changed, 489 insertions(+), 0 deletions(-) create mode 100644 tools/perf/Documentation/examples/Makefile create mode 100644 tools/perf/Documentation/examples/ibs.c
tools/perf/Documentation/examples/Makefile new file +44 -0
@@ -0,0 +1,44 @@ +all: ibs + +CFLAGS += -I../.. +CFLAGS += -I../../util/include +CFLAGS += -DNO_NEWT_SUPPORT + +LIB_FILE=../../libperf.a + +INSTALL = install + +ifeq ("$(origin O)", "command line") + OUTPUT := $(O)/ +endif + +ifneq ($(OUTPUT),) +# check that the output directory actually exists +OUTDIR := $(shell cd $(OUTPUT) && /bin/pwd) +$(if $(OUTDIR),, $(error output directory "$(OUTPUT)" does not exist)) +endif + +ifndef DESTDIR +prefix = $(HOME) +endif +bindir_relative = bin +bindir = $(prefix)/$(bindir_relative) + +DESTDIR_SQ = $(subst ','\'',$(DESTDIR)) +bindir_SQ = $(subst ','\'',$(bindir)) + +../../libperf.a: + $(MAKE) CFLAGS="-DNO_NEWT_SUPPORT" -C ../.. libperf.a + +$(OUTPUT)ibs: ibs.c $(LIB_FILE) + $(CC) $(CFLAGS) $^ -o $@ + +clean: + $(MAKE) -C ../.. clean + $(RM) ibs + +install: all + $(INSTALL) -d -m 755 '$(DESTDIR_SQ)$(bindir_SQ)' + $(INSTALL) $(OUTPUT)ibs '$(DESTDIR_SQ)$(bindir_SQ)' + +.PHONY: all clean install
tools/perf/Documentation/examples/ibs.c new file +445 -0
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Signature · 1 line
1.7.6.1