PSC9131/PSC9130/PSC9231 Processor Support Added

- PSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements.
- PSC9130 is exactly same as PSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131).
- PSC9231 is similar to PSC9131 except no MAPLE

The PSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations.

This patch takes care of code pertaining to power side functionality only.

---
Applied on git://git.denx.de/u-boot.git (branch master)

 arch/powerpc/cpu/mpc85xx/Makefile         |    1 +
 arch/powerpc/cpu/mpc8xxx/cpu.c            |    6 +-
 arch/powerpc/include/asm/config_mpc85xx.h |   14 +++-
 arch/powerpc/include/asm/immap_85xx.h     |  117 ++++++++++++++++++++++++++++-
 arch/powerpc/include/asm/processor.h      |    5 +
 5 files changed, 140 insertions(+), 3 deletions(-)

index 058d609..c3077ec 100644
@@ -70,6 +70,7 @@ COBJS-$(CONFIG_PPC_P3041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P3060)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
+COBJS-$(CONFIG_PSC9131)		+= ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)	+= ether_fcc.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o

index 0365ca8..987d3c1 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ * Copyright 2009-2012 Freescale Semiconductor, Inc.
  *
  * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
  * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains

@@ -113,6 +113,10 @@ struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(P5010, P5010_E, 1),
 	CPU_TYPE_ENTRY(P5020, P5020, 2),
 	CPU_TYPE_ENTRY(P5020, P5020_E, 2),
+	CPU_TYPE_ENTRY(PSC9130, 9130, 1),
+	CPU_TYPE_ENTRY(PSC9130, 9130_E, 1),
+	CPU_TYPE_ENTRY(PSC9131, 9131, 1),
+	CPU_TYPE_ENTRY(PSC9131, 9131_E, 1),
 #elif defined(CONFIG_MPC86xx)
 	CPU_TYPE_ENTRY(8610, 8610, 1),
 	CPU_TYPE_ENTRY(8641, 8641, 2),

index 8654625..694d2fb 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

@@ -459,6 +459,18 @@
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 
+#elif defined(CONFIG_PSC9131)
+#define CONFIG_MAX_CPUS			1
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_SYS_FSL_NUM_LAWS		12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+
 #else
 #error Processor type not defined for this platform
 #endif

index 4e32639..c9e112c 100644
@@ -1136,6 +1136,11 @@
 #define SVR_8641	0x809000
 #define SVR_8641D	0x809001
 
+#define SVR_9130	0x860001
+#define SVR_9130_E	0x860801
+#define SVR_9131	0x860000
+#define SVR_9131_E	0x860800
+
 #define SVR_Unknown	0xFFFFFF
 
 #define _GLOBAL(n)\

1.7.5.4