perf/x86: Implement cycles:p for SNB/IVB

tip:perf/core tip-bot for Peter Zijlstra 1 participant 6 messages Jun 6, 2012 1 message not in the archive

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tip-bot for Peter Zijlstra

author maintainer

2012-06-06 15:59 UTC #1 lore raw

Commit-ID:  cccb9ba9e4ee0d750265f53de9258df69655c40b
Gitweb:     http://git.kernel.org/tip/cccb9ba9e4ee0d750265f53de9258df69655c40b
Author:     Peter Zijlstra <[email protected]>
AuthorDate: Tue, 5 Jun 2012 10:26:43 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Wed, 6 Jun 2012 16:59:47 +0200

perf/x86: Implement cycles:p for SNB/IVB

Now that there's finally a chip with working PEBS (IvyBridge), we can enable the hardware and implement cycles:p for SNB/IVB.

Cc Stephane Eranian <[email protected]>

Requested-and-tested-by Linus Torvalds <[email protected]>

Signed-off-by Peter Zijlstra <[email protected]>

Link http://lkml.kernel.org/r/1338884803.28282.153.camel@twins open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/kernel/cpu/perf_event.h       |    1 +
 arch/x86/kernel/cpu/perf_event_intel.c |   50 ++++++++++++++++++++++++++-----
 2 files changed, 43 insertions(+), 8 deletions(-)

arch/x86/kernel/cpu/perf_event.h +1 -0

index 83794d8..7241e2f 100644
@@ -365,6 +365,7 @@ struct x86_pmu {
 	int		pebs_record_size;
 	void		(*drain_pebs)(struct pt_regs *regs);
 	struct event_constraint *pebs_constraints;
+	void		(*pebs_aliases)(struct perf_event *event);
 
 	/*
 	 * Intel LBR

arch/x86/kernel/cpu/perf_event_intel.c +42 -8

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tip-bot for Peter Zijlstra

author maintainer

2012-06-06 15:59 UTC #2 lore raw

[tip:perf/core] perf/x86: Enable/Add IvyBridge hardware support

In reply to a message not in the archive

Commit-ID:  b6db437ba8322f5cee0bd355ad2ef9f73c413754
Gitweb:     http://git.kernel.org/tip/b6db437ba8322f5cee0bd355ad2ef9f73c413754
Author:     Peter Zijlstra <[email protected]>
AuthorDate: Tue, 5 Jun 2012 10:26:43 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Wed, 6 Jun 2012 16:59:49 +0200

perf/x86: Enable/Add IvyBridge hardware support

Implement rudimentary IVB perf support. The SDM states its identical to SNB with exception of the exact event tables, but a quick look suggests they're similar enough.

Also mark SNB-EP as broken for now.

Requested-and-tested-by Linus Torvalds <[email protected]>

Cc Stephane Eranian <[email protected]>

Signed-off-by Peter Zijlstra <[email protected]>

Link http://lkml.kernel.org/r/1338884803.28282.153.camel@twins open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/kernel/cpu/perf_event_intel.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

arch/x86/kernel/cpu/perf_event_intel.c +2 -1

index 2312c1f..187c294 100644
@@ -1909,8 +1909,9 @@ __init int intel_pmu_init(void)
 		break;
 
 	case 42: /* SandyBridge */
-		x86_add_quirk(intel_sandybridge_quirk);
 	case 45: /* SandyBridge, "Romely-EP" */
+		x86_add_quirk(intel_sandybridge_quirk);
+	case 58: /* IvyBridge */
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));

tip-bot for Peter Zijlstra

author maintainer

2012-06-06 16:00 UTC #3 lore raw

[tip:perf/core] perf/x86: Update SNB PEBS constraints

In reply to a message not in the archive

Commit-ID:  8440ccb43fc0ecffcf1acee0273d766e6a8cd51d
Gitweb:     http://git.kernel.org/tip/8440ccb43fc0ecffcf1acee0273d766e6a8cd51d
Author:     Peter Zijlstra <[email protected]>
AuthorDate: Tue, 5 Jun 2012 10:26:43 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Wed, 6 Jun 2012 16:59:52 +0200

perf/x86: Update SNB PEBS constraints

Afaict there's no need to (incompletely) iterate the MEM_UOPS_RETIRED.* umask state.

Signed-off-by Peter Zijlstra <[email protected]>

Cc Stephane Eranian <[email protected]>

Link http://lkml.kernel.org/r/1338884803.28282.153.camel@twins open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/kernel/cpu/perf_event_intel_ds.c |    9 +--------
 1 files changed, 1 insertions(+), 8 deletions(-)

arch/x86/kernel/cpu/perf_event_intel_ds.c +1 -8

index 5a3edc2..35e2192 100644
@@ -400,14 +400,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
 	INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 	INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 	INTEL_EVENT_CONSTRAINT(0xcd, 0x8),    /* MEM_TRANS_RETIRED.* */
-	INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf), /* MEM_UOP_RETIRED.STLB_MISS_LOADS */
-	INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf), /* MEM_UOP_RETIRED.STLB_MISS_STORES */
-	INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOP_RETIRED.LOCK_LOADS */
-	INTEL_UEVENT_CONSTRAINT(0x22d0, 0xf), /* MEM_UOP_RETIRED.LOCK_STORES */
-	INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOP_RETIRED.SPLIT_LOADS */
-	INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf), /* MEM_UOP_RETIRED.SPLIT_STORES */
-	INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOP_RETIRED.ANY_LOADS */
-	INTEL_UEVENT_CONSTRAINT(0x82d0, 0xf), /* MEM_UOP_RETIRED.ANY_STORES */
+	INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 	INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 	INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 	INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */

tip-bot for Peter Zijlstra

author maintainer

2012-06-06 16:13 UTC #4 lore raw

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Commit-ID:  0780c927a02492f917a74f51f3c801c76a637c57
Gitweb:     http://git.kernel.org/tip/0780c927a02492f917a74f51f3c801c76a637c57
Author:     Peter Zijlstra <[email protected]>
AuthorDate: Tue, 5 Jun 2012 10:26:43 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Wed, 6 Jun 2012 17:22:34 +0200

perf/x86: Implement cycles:p for SNB/IVB

Now that there's finally a chip with working PEBS (IvyBridge), we can enable the hardware and implement cycles:p for SNB/IVB.

Cc Stephane Eranian <[email protected]>

Requested-and-tested-by Linus Torvalds <[email protected]>

Signed-off-by Peter Zijlstra <[email protected]>

Link http://lkml.kernel.org/r/1338884803.28282.153.camel@twins open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/kernel/cpu/perf_event.h       |    1 +
 arch/x86/kernel/cpu/perf_event_intel.c |   50 ++++++++++++++++++++++++++-----
 2 files changed, 43 insertions(+), 8 deletions(-)

arch/x86/kernel/cpu/perf_event.h +1 -0

index 83794d8..7241e2f 100644
@@ -365,6 +365,7 @@ struct x86_pmu {
 	int		pebs_record_size;
 	void		(*drain_pebs)(struct pt_regs *regs);
 	struct event_constraint *pebs_constraints;
+	void		(*pebs_aliases)(struct perf_event *event);
 
 	/*
 	 * Intel LBR

arch/x86/kernel/cpu/perf_event_intel.c +42 -8

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tip-bot for Peter Zijlstra

author maintainer

2012-06-06 16:13 UTC #5 lore raw

[tip:perf/core] perf/x86: Enable/Add IvyBridge hardware support

In reply to a message not in the archive

Commit-ID:  47a8863dbb11745446314ca126593789ab74d93a
Gitweb:     http://git.kernel.org/tip/47a8863dbb11745446314ca126593789ab74d93a
Author:     Peter Zijlstra <[email protected]>
AuthorDate: Tue, 5 Jun 2012 10:26:43 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Wed, 6 Jun 2012 17:22:39 +0200

perf/x86: Enable/Add IvyBridge hardware support

Implement rudimentary IVB perf support. The SDM states its identical to SNB with exception of the exact event tables, but a quick look suggests they're similar enough.

Also mark SNB-EP as broken for now.

Requested-and-tested-by Linus Torvalds <[email protected]>

Cc Stephane Eranian <[email protected]>

Signed-off-by Peter Zijlstra <[email protected]>

Link http://lkml.kernel.org/r/1338884803.28282.153.camel@twins open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/kernel/cpu/perf_event_intel.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

arch/x86/kernel/cpu/perf_event_intel.c +2 -1

index 2312c1f..187c294 100644
@@ -1909,8 +1909,9 @@ __init int intel_pmu_init(void)
 		break;
 
 	case 42: /* SandyBridge */
-		x86_add_quirk(intel_sandybridge_quirk);
 	case 45: /* SandyBridge, "Romely-EP" */
+		x86_add_quirk(intel_sandybridge_quirk);
+	case 58: /* IvyBridge */
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));

tip-bot for Peter Zijlstra

author maintainer

2012-06-06 16:14 UTC #6 lore raw

[tip:perf/core] perf/x86: Update SNB PEBS constraints

In reply to a message not in the archive

Commit-ID:  212d95dfdb66e5c81879b08e4f7fbfc8498b1ab5
Gitweb:     http://git.kernel.org/tip/212d95dfdb66e5c81879b08e4f7fbfc8498b1ab5
Author:     Peter Zijlstra <[email protected]>
AuthorDate: Tue, 5 Jun 2012 10:26:43 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Wed, 6 Jun 2012 17:22:43 +0200

perf/x86: Update SNB PEBS constraints

Afaict there's no need to (incompletely) iterate the MEM_UOPS_RETIRED.* umask state.

Signed-off-by Peter Zijlstra <[email protected]>

Cc Stephane Eranian <[email protected]>

Link http://lkml.kernel.org/r/1338884803.28282.153.camel@twins open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/kernel/cpu/perf_event_intel_ds.c |    9 +--------
 1 files changed, 1 insertions(+), 8 deletions(-)

arch/x86/kernel/cpu/perf_event_intel_ds.c +1 -8

index 5a3edc2..35e2192 100644
@@ -400,14 +400,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
 	INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
 	INTEL_EVENT_CONSTRAINT(0xc5, 0xf),    /* BR_MISP_RETIRED.* */
 	INTEL_EVENT_CONSTRAINT(0xcd, 0x8),    /* MEM_TRANS_RETIRED.* */
-	INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf), /* MEM_UOP_RETIRED.STLB_MISS_LOADS */
-	INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf), /* MEM_UOP_RETIRED.STLB_MISS_STORES */
-	INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOP_RETIRED.LOCK_LOADS */
-	INTEL_UEVENT_CONSTRAINT(0x22d0, 0xf), /* MEM_UOP_RETIRED.LOCK_STORES */
-	INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOP_RETIRED.SPLIT_LOADS */
-	INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf), /* MEM_UOP_RETIRED.SPLIT_STORES */
-	INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOP_RETIRED.ANY_LOADS */
-	INTEL_UEVENT_CONSTRAINT(0x82d0, 0xf), /* MEM_UOP_RETIRED.ANY_STORES */
+	INTEL_EVENT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */
 	INTEL_EVENT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */
 	INTEL_EVENT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
 	INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */