nds32: split common cache access from cpu into lib

This commit does the following updates.
1. Split the common cache access from cpu.c into lib folder.
2. Rename the following cache api to adapt common.h
- dcache_flush_rang -> flush_dcache_rang
- icache_inval_range -> invalidate_icache_range
3. Add invalidate_dcache_range

arch/nds32/lib/cache.c +0 -0

arch/nds32/lib/cache.c +4 -0

+	else
+		return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
+					>> DCM_CFG_OFF_DSZ) - 1);
+}

arch/nds32/lib/cache.c +20 -0

+		start += line_size;
+	}
+}
+
+void invalidate_icache_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(ICACHE);
+	while (end > start) {
+		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
+		start += line_size;
+	}
+}
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+	unsigned long line_size;
+
+	line_size = CACHE_LINE_SIZE(DCACHE);

Dear Macpaul Lin,

Quoted 6 lines

This commit does the following updates.
1. Split the common cache access from cpu.c into lib folder.
2. Rename the following cache api to adapt common.h
- dcache_flush_rang -> flush_dcache_rang
- icache_inval_range -> invalidate_icache_range
3. Add invalidate_dcache_range

So basically this connects it to standard cache api?

[...]

Quoted 1 line

arch/nds32/lib/cache.c +0 -0

[...]

arch/nds32/lib/cache.c line 28

Quoted 5 lines

arch/nds32/lib/cache.c +5 -0

+static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
+{
+     if (cache == ICACHE)
+             return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
+                                     >> ICM_CFG_OFF_ISZ) - 1);

These crazy macros can be probably done easier and can share some code maybe? Maybe not though, I dunno, just a thought.

arch/nds32/lib/cache.c line 42

Quoted 4 lines

arch/nds32/lib/cache.c +4 -0

+void flush_dcache_range(unsigned long start, unsigned long end)
+     while (end > start) {
+             __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
+             __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));

You probably want to do those two calls in one asm volatile () block. And this too ... use "asm volatile()" and not "__asm__ volatile" or "asm __volatile__" and similar combinations of these, just a nit ;-)

arch/nds32/lib/cache.c line 72

Quoted 4 lines

arch/nds32/lib/cache.c +4 -0

+void flush_cache(unsigned long addr, unsigned long size)
+{
+     flush_dcache_range(addr, addr + size);
+     invalidate_icache_range(addr, addr + size);

You probably want to flush dcache in here and that's it.

arch/nds32/lib/cache.c line 77

Quoted 5 lines

arch/nds32/lib/cache.c +5 -0

+}
+
+void icache_enable(void)
+{
+     __asm__ __volatile__ (

See my nit above for the rest ;-) But all in all it's good, we should be applying this around V2-V3 of this patch, for the -next release. Thanks for your patch!

This commit does the following updates.
1. Split the common cache access from cpu.c into lib folder.
2. Rename the following cache api to adapt common.h
- dcache_flush_rang -> flush_dcache_rang
- icache_inval_range -> invalidate_icache_range
3. Add invalidate_dcache_range

Signed-off-by Macpaul Lin <[email protected]>

---
Changes for v2:
- flush_dcache_range: merge two asm calls into a single asm volatile() block.
- Replace __asm__ __volatile__ block into asm volatile()

Dear Macpaul Lin,

arch/nds32/lib/cache.c line 72

Quoted 4 lines

arch/nds32/lib/cache.c new file +4 -0

+void flush_cache(unsigned long addr, unsigned long size)
+{
+	flush_dcache_range(addr, addr + size);
+	invalidate_icache_range(addr, addr + size);

You probably want to flush dcache in here and that's it.

Quoted 7 lines

Dear Macpaul Lin,

arch/nds32/lib/cache.c line 72

Quoted 4 lines

arch/nds32/lib/cache.c new file +4 -0

+void flush_cache(unsigned long addr, unsigned long size)
+{
+   flush_dcache_range(addr, addr + size);
+   invalidate_icache_range(addr, addr + size);

You probably want to flush dcache in here and that's it.

i don't think so ... i think that's what flush_dcache_range() is for. and our
common/cmd_*.c files assume that flush_cache() will invalidate icache (see the
bootm/load funcs that write executable content into memory and then flush the
regions).
-mike

Quoted 8 lines

Dear Macpaul Lin,

arch/nds32/lib/cache.c line 72

Quoted 4 lines

arch/nds32/lib/cache.c new file +4 -0

+void flush_cache(unsigned long addr, unsigned long size)
+{
+	flush_dcache_range(addr, addr + size);
+	invalidate_icache_range(addr, addr + size);

You probably want to flush dcache in here and that's it.

i don't think so ... i think that's what flush_dcache_range() is for. and our common/cmd_*.c files assume that flush_cache() will invalidate icache (see the bootm/load funcs that write executable content into memory and then flush the regions).

Dear Mike Frysinger,

Quoted 9 lines · On Sunday 15 July 2012 04:12:45 Marek Vasut wrote:

Quoted 7 lines

Dear Macpaul Lin,

arch/nds32/lib/cache.c line 72

Quoted 4 lines

arch/nds32/lib/cache.c new file +4 -0

+void flush_cache(unsigned long addr, unsigned long size)
+{
+	flush_dcache_range(addr, addr + size);
+	invalidate_icache_range(addr, addr + size);

You probably want to flush dcache in here and that's it.

Quoted 4 lines

i don't think so ... i think that's what flush_dcache_range() is for. and our common/cmd_*.c files assume that flush_cache() will invalidate icache (see the bootm/load funcs that write executable content into memory and then flush the regions).

Than it's borked on arm926ejs too ... ?

Quoted 12 lines

Dear Mike Frysinger,

Quoted 10 lines · On Sunday 15 July 2012 04:12:45 Marek Vasut wrote:

Quoted 8 lines

Dear Macpaul Lin,

arch/nds32/lib/cache.c line 72

Quoted 4 lines

arch/nds32/lib/cache.c new file +4 -0

+void flush_cache(unsigned long addr, unsigned long size)
+{
+	flush_dcache_range(addr, addr + size);
+	invalidate_icache_range(addr, addr + size);

You probably want to flush dcache in here and that's it.

Quoted 6 lines

Quoted 4 lines

i don't think so ... i think that's what flush_dcache_range() is for. and our common/cmd_*.c files assume that flush_cache() will invalidate icache (see the bootm/load funcs that write executable content into memory and then flush the regions).

Than it's borked on arm926ejs too ... ?

if it doesn't flush icache in the flush_cache() function, then i would say so

sounds like we should rip all this cache stuff out of common.h and into like cache.h so we can document the API expectations. i think Wolfgang was against this before, but maybe that was just creating a header for one specific cache macro and not all cache stuff ?

sounds like we should rip all this cache stuff out of common.h and into

Quoted 2 lines

like cache.h so we can document the API expectations. i think Wolfgang was against this before, but maybe that was just creating a header for

one

Quoted 1 line

specific cache macro and not all cache stuff ?

Certainly this sounds good. We'd also be able to add some nice instrumentation
while at that, to detect problematic cases with DEBUG enabled or so. The cache
stuff is starting to get really crazy.

Best regards,
Marek Vasut

Since this discussion hasn't been finished,
and we haven't decide the final action about the new policy about cache.h and common.h.
I'd like to pick this patch v2 for the coming release for fixing build error for board adp-ag102.
What do you think? :-)