Pending Tegra2 patches

index 2403874..d9bb851 100644
@@ -502,6 +502,7 @@ static int clock_periph_id_isvalid(enum periph_id id)
 		case PERIPH_ID_RESERVED81:
 		case PERIPH_ID_RESERVED82:
 		case PERIPH_ID_RESERVED83:
+		case PERIPH_ID_RESERVED91:
 			printf("Peripheral id %d is reserved\n", id);
 			break;
 		default:

index ff83bbf..20db9e6 100644
@@ -175,6 +175,12 @@ enum periph_id {
 
 	/* 88 */
 	PERIPH_ID_CRAM2,
+	PERIPH_ID_SYNC_CLK_DOUBLER,
+	PERIPH_ID_CLK_M_DOUBLER,
+	PERIPH_ID_RESERVED91,
+	PERIPH_ID_SUS_OUT,
+	PERIPH_ID_DEV2_OUT,
+	PERIPH_ID_DEV1_OUT,
 
 	PERIPH_ID_COUNT,
 	PERIPH_ID_NONE = -1,

index d9bb851..6ebddf8 100644
@@ -396,6 +396,16 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 	NONE(CRAM2),
 };
 
+/* number of clock outputs of a PLL */
+static const u8 pll_num_clkouts[] = {
+	1,	/* PLLC */
+	1,	/* PLLM */
+	4,	/* PLLP */
+	1,	/* PLLA */
+	0,	/* PLLU */
+	0,	/* PLLD */
+};
+
 /*
  * Get the oscillator frequency, from the corresponding hardware configuration
  * field.

@@ -604,6 +614,34 @@ unsigned long clock_get_periph_rate(enum periph_id periph_id,
 		(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
 }
 
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
+{
+	struct clk_pll *pll = get_pll(clkid);
+	int data = 0, div = 0, offset = 0;
+
+	if (!clock_id_is_pll(clkid))
+		return -1;
+
+	if (pllout + 1 > pll_num_clkouts[clkid])
+		return -1;
+
+	div = clk_get_divider(8, pll_rate[clkid], rate);
+
+	if (div < 0)
+		return -1;
+
+	/* out2 and out4 are in the high part of the register */
+	if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
+		offset = 16;
+
+	data = (div << PLL_OUT_RATIO_SHIFT) |
+	       PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
+	clrsetbits_le32(&pll->pll_out[pllout >> 1],
+	                PLL_OUT_RATIO_MASK << offset, data << offset);
+
+	return 0;
+}
+
 /**
  * Find the best available 7.1 format divisor given a parent clock rate and
  * required child clock rate. This function assumes that a second-stage

index 80a5a15..f08da1b 100644
@@ -214,7 +214,7 @@ void wb_start(void)
 
 	reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |
 	      PLLM_OUT1_RATIO_VAL_8;
-	writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out);
+	writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);
 
 	reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
 	      SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |

index 8c3be91..7b548c2 100644
@@ -27,8 +27,7 @@
 /* PLL registers - there are several PLLs in the clock controller */
 struct clk_pll {
 	uint pll_base;		/* the control register */
-	uint pll_out;		/* output control */
-	uint reserved;
+	uint pll_out[2];	/* output control */
 	uint pll_misc;		/* other misc things */
 };
 

@@ -112,6 +111,14 @@ struct clk_rst_ctlr {
 #define PLL_DIVM_SHIFT		0
 #define PLL_DIVM_MASK		(0x1f << PLL_DIVM_SHIFT)
 
+/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
+#define PLL_OUT_RSTN		(1 << 0)
+#define PLL_OUT_CLKEN		(1 << 1)
+#define PLL_OUT_OVRRIDE		(1 << 2)
+
+#define PLL_OUT_RATIO_SHIFT	8
+#define PLL_OUT_RATIO_MASK	(0xffU << PLL_OUT_RATIO_SHIFT)
+
 /* CLK_RST_CONTROLLER_PLLx_MISC_0 */
 #define PLL_CPCON_SHIFT		8
 #define PLL_CPCON_MASK		(15U << PLL_CPCON_SHIFT)

index 20db9e6..dfef51e 100644
@@ -186,6 +186,13 @@ enum periph_id {
 	PERIPH_ID_NONE = -1,
 };
 
+enum pll_out_id {
+	PLL_OUT1,
+	PLL_OUT2,
+	PLL_OUT3,
+	PLL_OUT4
+};
+
 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
 #define PERIPH_REG(id) ((id) >> 5)
 

@@ -218,6 +225,18 @@ unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
 		u32 divp, u32 cpcon, u32 lfcon);
 
 /**
+ * Set PLL output frequency
+ *
+ * @param clkid		clock id
+ * @param pllout	pll output id (
+ * @param rate		desired output rate
+ *
+ * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
+ */
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
+                     unsigned rate);
+
+/**
  * Read low-level parameters of a PLL.
  *
  * @param id	clock id to read (note: USB is not supported)

index 61b91c0..260767d 100644
@@ -22,4 +22,4 @@
  */
 
 void board_init_uart_f(void);
-void gpio_config_uart(void);
+void gpio_early_init_uart(void);

index 6c16dce..4f54117 100644
@@ -65,11 +65,7 @@ void board_init_f(ulong dummy)
 	board_init_uart_f();
 
 	/* Initialize periph GPIOs */
-#ifdef CONFIG_SPI_UART_SWITCH
 	gpio_early_init_uart();
-#else
-	gpio_config_uart();
-#endif
 
 	/*
 	 * We call relocate_code() with relocation target same as the

index 93f12ea..6d9369d 100644
@@ -41,13 +41,6 @@
 #include <mmc.h>
 #endif
 
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Tamonten - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 void gpio_early_init(void)

index 0f8f167..6aa2e57 100644
@@ -24,13 +24,6 @@
 #include <mmc.h>
 #endif
 
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Paz00 - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
 
 #ifdef CONFIG_TEGRA_MMC
 /*

index 893cca8..c589a06 100644
@@ -34,13 +34,6 @@
 #include <mmc.h>
 #endif
 
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on TrimSlice - no UART-related GPIOs.
- */
-void gpio_config_uart(void)
-{
-}
 
 void pin_mux_spi(void)
 {

index afe832a..2385162 100644
@@ -72,6 +72,11 @@ void __pin_mux_spi(void)
 
 void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
 
+void __gpio_early_init_uart(void)
+{
+}
+
+void gpio_early_init_uart(void) __attribute__((weak, alias("__gpio_early_init_uart")));
 /*
  * Routine: power_det_init
  * Description: turn off power detects

@@ -156,11 +161,8 @@ int board_early_init_f(void)
 
 	/* Initialize periph GPIOs */
 	gpio_early_init();
-#ifdef CONFIG_SPI_UART_SWITCH
 	gpio_early_init_uart();
-#else
-	gpio_config_uart();
-#endif
+
 	return 0;
 }
 #endif	/* EARLY_INIT */

index b4a811d..da1649a 100644
@@ -33,13 +33,6 @@
 #include <mmc.h>
 #endif
 
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Harmony - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
 
 #ifdef CONFIG_TEGRA_MMC
 /*

index 667f60a..d2df2df 100644
@@ -46,7 +46,7 @@ static void gpio_config_uart_seaboard(void)
 	gpio_direction_output(GPIO_PI3, 0);
 }
 
-void gpio_config_uart(void)
+void gpio_early_init_uart(void)
 {
 	if (machine_is_ventana())
 		return;

index 598b2e5..e8325fe 100644
@@ -34,13 +34,6 @@
 #include <mmc.h>
 #endif
 
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Whistler - no UART-related GPIOs.
- */
-void gpio_config_uart(void)
-{
-}
 
 /*
  * Routine: pin_mux_mmc