Add support for NVIDIA Tegra114 SoC

arch/arm/include/asm/arch-tegra114/gpio.h

Quoted 6 lines · Tom Warren

Common Tegra files are in arch-tegra, shared between T20/T30/T114. Tegra114-specific headers are in arch-tegra114. Note that some of these will be filled in as more T114 support is added (drivers, WB/LP0 support, etc.).

arch/arm/include/asm/arch-tegra114/gpio.h +0 -0

I think the Tegra30 and Tegra114 GPIO controllers are basically identical. Can this file be shared at all?

arch/arm/include/asm/arch-tegra114/tegra.h

Quoted 3 lines

arch/arm/include/asm/arch-tegra114/tegra.h +1 -0

 
+#define BCT_ODMDATA_OFFSET   6116    /* 12 bytes from end of BCT */

That's the Tegra30 value. I'm pretty sure the Tegra30 and Tegra114 BCTs are laid out very differently, so this value isn't valid.

Stephen,

Quoted 11 lines · Stephen Warren

arch/arm/include/asm/arch-tegra114/gpio.h

Quoted 6 lines · Tom Warren

Common Tegra files are in arch-tegra, shared between T20/T30/T114. Tegra114-specific headers are in arch-tegra114. Note that some of these will be filled in as more T114 support is added (drivers, WB/LP0 support, etc.).

arch/arm/include/asm/arch-tegra114/gpio.h +0 -0

I think the Tegra30 and Tegra114 GPIO controllers are basically identical. Can this file be shared at all?

gpio.h is identical for T30 and T114, but not for T20. I've already commonized what I could in arch-tegra/gpio.h, but to do the same for the gpio_ctlr struct and gpio_pin enums would involve #ifdefs, which is moving in the wrong direction, IMO. If you have a way to share one or two files between T20/T30/T114/future SoCs, I'll give it a try.

struct tegra_gpio_soc_config {
        u32 bank_stride;
        u32 upper_offset;
};

static struct tegra_gpio_soc_config tegra20_gpio_config = {
        .bank_stride = 0x80,
        .upper_offset = 0x800,
};

static struct tegra_gpio_soc_config tegra30_gpio_config = {
        .bank_stride = 0x100,
        .upper_offset = 0x80,
};

static struct of_device_id tegra_gpio_of_match[] = {
        { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
        { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
        { },
};

#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \

#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)

#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)

Quoted 15 lines · Tom Warren

Stephen,

Quoted 11 lines · Stephen Warren

arch/arm/include/asm/arch-tegra114/gpio.h

Quoted 6 lines · Tom Warren

Common Tegra files are in arch-tegra, shared between T20/T30/T114. Tegra114-specific headers are in arch-tegra114. Note that some of these will be filled in as more T114 support is added (drivers, WB/LP0 support, etc.).

arch/arm/include/asm/arch-tegra114/gpio.h +0 -0

I think the Tegra30 and Tegra114 GPIO controllers are basically identical. Can this file be shared at all?

Quoted 5 lines

gpio.h is identical for T30 and T114, but not for T20. I've already commonized what I could in arch-tegra/gpio.h, but to do the same for the gpio_ctlr struct and gpio_pin enums would involve #ifdefs, which is moving in the wrong direction, IMO. If you have a way to share one or two files between T20/T30/T114/future SoCs, I'll give it a try.

This may not work well for U-Boot since it uses structs to define the register layouts rather than simply #defining the various register addresses, but:

We use the exact same driver code for Tegra20/30/114. The difference in register layout between Tegra20/30 can be described algorithmically with the following data:

Quoted 15 lines

struct tegra_gpio_soc_config {
        u32 bank_stride;
        u32 upper_offset;
};

static struct tegra_gpio_soc_config tegra20_gpio_config = {
        .bank_stride = 0x80,
        .upper_offset = 0x800,
};

static struct tegra_gpio_soc_config tegra30_gpio_config = {
        .bank_stride = 0x100,
        .upper_offset = 0x80,
};

Quoted 5 lines

static struct of_device_id tegra_gpio_of_match[] = {
        { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
        { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
        { },
};

which feeds into a few register offset #defines:

Quoted 1 line

#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \

...

Quoted 1 line

#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)

...

Quoted 1 line

#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)

Alternatively, can the Tegra114 GPIO header simply #include the Tegra30 GPIO header and do nothing else, via some relative include or similar? I'm not sure how gross that'd turn out to be.

Common Tegra files are in arch-tegra, shared between T20/T30/T114. Tegra114-specific headers are in arch-tegra114. Note that some of these will be filled in as more T114 support is added (drivers, WB/LP0 support, etc.).

Signed-off-by Tom Warren <[email protected]>

---

Quoted 7 lines · Tom Warren

Common Tegra files are in arch-tegra, shared between T20/T30/T114. Tegra114-specific headers are in arch-tegra114. Note that some of these will be filled in as more T114 support is added (drivers, WB/LP0 support, etc.).

Signed-off-by Tom Warren <[email protected]>

---

arch/arm/include/asm/arch-tegra/clk_rst.h enum { · line 235

Quoted 7 lines

arch/arm/include/asm/arch-tegra/clk_rst.h +5 -0

+#if defined(CONFIG_TEGRA20)
 #define OSC_FREQ_SHIFT         30
 #define OSC_FREQ_MASK          (3U << OSC_FREQ_SHIFT)
+#else  /* Tegra30, Tegra114 */
+#define OSC_FREQ_SHIFT         28
+#define OSC_FREQ_MASK          (0xF << OSC_FREQ_SHIFT)
+#endif

Can this be a new define instead of a #ifdef? That makes it easier in the future to make a single u-boot to boot on all tegras.

arch/arm/include/asm/arch-tegra/tegra.h enum { · line 77

Quoted 11 lines

index 953936c..670745f 100644

arch/arm/include/asm/arch-tegra/tegra.h +1 -0

@@ -73,6 +73,7 @@ enum {
        SKU_ID_AP25E            = 0x1b,
        SKU_ID_T25E             = 0x1c,
        SKU_ID_T30              = 0x81, /* Cardhu value */
+       SKU_ID_T114             = 0x00, /* Dalmore value */
 };

Is that really the proper SKU id? Or is it just unprogrammed on the early chips?

arch/arm/include/asm/arch-tegra114/clock.h line 2

Quoted 11 lines

arch/arm/include/asm/arch-tegra114/clock.h new file +2 -0

new file mode 100644
index 0000000..9e56f57
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.

2013, here and all new files

-Allen
--
nvpublic

arch/arm/cpu/arm720t/tegra-common/cpu.c enum tegra_family_t get_family(void) · line 46

Quoted 10 lines · Tom Warren

This provides SPL support for T114 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot.

arch/arm/cpu/arm720t/tegra-common/cpu.c +1 -1

 
-     if (chip_id == 0x30)
+     if (chip_id >= 0x30)
              return TEGRA_FAMILY_T3x;
      else
              return TEGRA_FAMILY_T2x;

Shouldn't that comparison use CHIPID_TEGRA30?

Shouldn't there be a TEGRA_FAMILY_T11x for Tegra114; anything that cares about >=Tegra30 can compare the family with >= not ==.

Hmm. It seems the only use of the FAMILY value is get_num_cpus() right below; why not have that just switch on the same chip_id variable that everything else uses?

arch/arm/cpu/arm720t/tegra-common/cpu.h line 30

Quoted 9 lines

arch/arm/cpu/arm720t/tegra-common/cpu.h +6 -0

 
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE        0
+#endif

Surely those are in a standard header somewhere; we shouldn't create yet another duplicate of them.

Quoted 4 lines

arch/arm/cpu/arm720t/tegra114/cpu.c +1 -0

 
+static int is_partition_powered(u32 mask)

arch/arm/cpu/arm720t/tegra114/cpu.c line 234

Quoted 5 lines

arch/arm/cpu/arm720t/tegra114/cpu.c +5 -0

+     reg = readl(&pmc->pmc_pwrgate_status);
+     if ((reg & mask) == mask)
+             return TRUE;
+
+     return FALSE;

The last 4 lines are just "return reg & mask;" or "return (reg & mask) == mask;". Same in the next function.

arch/arm/cpu/arm720t/tegra114/cpu.c line 281

Quoted 7 lines

arch/arm/cpu/arm720t/tegra114/cpu.c +6 -0

+void powerup_cpus(void)
+{
+     debug("powerup_cpus entry\n");
+
+     /* Are we booting to the fast cluster? */
+     if (get_cluster_id() == 0) {

Why would we ever boot on anything other than the fast cluster? I would assume that the kernel assume it will always get booted on the fast cluster, which would then imply that U-Boot had to boot on or switch to the fast cluster.

Stephen,

Quoted 6 lines · Stephen Warren

Quoted 4 lines · Tom Warren

This provides SPL support for T114 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot.

arch/arm/cpu/arm720t/tegra-common/cpu.h +0 -0

Quoted 9 lines

arch/arm/cpu/arm720t/tegra-common/cpu.h line 30

Quoted 6 lines

arch/arm/cpu/arm720t/tegra-common/cpu.h +6 -0

+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE        0
+#endif

Surely those are in a standard header somewhere; we shouldn't create yet another duplicate of them.

Couldn't find 'em on a quick search (grep define.TRUE) except in places like scsi.h and ext4_common.h and fpga.h. If you have a standard header that you know of, let me know.

Quoted 10 lines

Quoted 9 lines

arch/arm/cpu/arm720t/tegra114/cpu.c +6 -0

 
+static int is_partition_powered(u32 mask)
 
+     reg = readl(&pmc->pmc_pwrgate_status);
+     if ((reg & mask) == mask)
+             return TRUE;
+
+     return FALSE;

Quoted 2 lines

The last 4 lines are just "return reg & mask;" or "return (reg & mask) == mask;". Same in the next function.

I'm porting internal bootloader bringup code here, and trying to avoid unnecessary changes, but I can modify these to remove the TRUE/FALSE in V2.

Quoted 11 lines

arch/arm/cpu/arm720t/tegra114/cpu.c line 281

Quoted 6 lines

arch/arm/cpu/arm720t/tegra114/cpu.c +6 -0

+void powerup_cpus(void)
+{
+     debug("powerup_cpus entry\n");
+
+     /* Are we booting to the fast cluster? */
+     if (get_cluster_id() == 0) {

Why would we ever boot on anything other than the fast cluster? I would assume that the kernel assume it will always get booted on the fast cluster, which would then imply that U-Boot had to boot on or switch to the fast cluster.

Again, this is from internal NV bootloader code that I know works. I don't know the circumstances where we might be booted on the LP cluster, but I figured if the internal bootloader code thought it worth checking, so should I. If you have unimpeachable evidence to the contrary, I can optimize this out.

This provides SPL support for T114 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot.

Signed-off-by Tom Warren <[email protected]>

---
 arch/arm/cpu/arm720t/tegra-common/cpu.c |   23 ++-
 arch/arm/cpu/arm720t/tegra-common/cpu.h |   13 +-
 arch/arm/cpu/arm720t/tegra114/Makefile  |   42 ++++
 arch/arm/cpu/arm720t/tegra114/config.mk |   19 ++
 arch/arm/cpu/arm720t/tegra114/cpu.c     |  328 +++++++++++++++++++++++++++++++
 5 files changed, 411 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/cpu/arm720t/tegra114/Makefile
 create mode 100644 arch/arm/cpu/arm720t/tegra114/config.mk
 create mode 100644 arch/arm/cpu/arm720t/tegra114/cpu.c

arch/arm/cpu/arm720t/tegra-common/cpu.c +0 -0

index 693d584..846163c 100644

arch/arm/cpu/arm720t/tegra-common/cpu.c +1 -0

                return TEGRA_FAMILY_T3x;
        else
                return TEGRA_FAMILY_T2x;

@@ -56,6 +56,7 @@ int get_num_cpus(void)
  */
 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
        /* T20: 1 GHz */
+       /*  n,  m, p, cpcon */
        {{ 1000, 13, 0, 12},    /* OSC 13M */
         { 625,  12, 0, 8},     /* OSC 19.2M */
         { 1000, 12, 0, 12},    /* OSC 12M */

arch/arm/cpu/arm720t/tegra-common/cpu.c +5 -0

+       /* T114: 1.4 GHz */
+       {{ 862, 8, 0, 8},
+        { 583, 8, 0, 4},
+        { 696, 12, 0, 8},
+        { 700, 13, 0, 8},
        },
 };
 

arch/arm/cpu/arm720t/tegra-common/cpu.c +0 -0

                writel(rst, CSITE_CPU_DBG2_LAR);
                writel(rst, CSITE_CPU_DBG3_LAR);
 #endif

arch/arm/cpu/arm720t/tegra-common/cpu.h +0 -0

index 3e2ea3a..45b346d 100644

Quoted 20 lines · Tom Warren

This provides SPL support for T114 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot.

Signed-off-by Tom Warren <[email protected]>

---
 arch/arm/cpu/arm720t/tegra-common/cpu.c |   23 ++-
 arch/arm/cpu/arm720t/tegra-common/cpu.h |   13 +-
 arch/arm/cpu/arm720t/tegra114/Makefile  |   42 ++++
 arch/arm/cpu/arm720t/tegra114/config.mk |   19 ++
 arch/arm/cpu/arm720t/tegra114/cpu.c     |  328 +++++++++++++++++++++++++++++++
 5 files changed, 411 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/cpu/arm720t/tegra114/Makefile
 create mode 100644 arch/arm/cpu/arm720t/tegra114/config.mk
 create mode 100644 arch/arm/cpu/arm720t/tegra114/cpu.c

arch/arm/cpu/arm720t/tegra-common/cpu.c +0 -0

index 693d584..846163c 100644

arch/arm/cpu/arm720t/tegra-common/cpu.c enum tegra_family_t get_family(void) · line 43

Quoted 5 lines

arch/arm/cpu/arm720t/tegra-common/cpu.c +1 -1

@@ -40,7 +40,7 @@ enum tegra_family_t get_family(void)
        chip_id = reg >> 8;
        chip_id &= 0xff;
        debug("  tegra_get_family: chip_id = %x\n", chip_id);
-       if (chip_id == 0x30)
+       if (chip_id >= 0x30)

Should this be CHIPID_TEGRA30? And it would probably be better to do:

if (chipid == CHIPID_TEGRA30 || chipid == CHIPID_TEGRA114)

         return TEGRA_FAMILY_T3x;
else if (chipid == CHIPID_TEGRA20)
         return TEGRA_FAMILY_T2x;
else
         fail;

That forces the person doing the support for the next tegra chip to have to make a conscious decision about what to do here.

Quoted 17 lines

arch/arm/cpu/arm720t/tegra-common/cpu.c +1 -0

                return TEGRA_FAMILY_T3x;
        else
                return TEGRA_FAMILY_T2x;

@@ -56,6 +56,7 @@ int get_num_cpus(void)
  */
 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
        /* T20: 1 GHz */
+       /*  n,  m, p, cpcon */
        {{ 1000, 13, 0, 12},    /* OSC 13M */
         { 625,  12, 0, 8},     /* OSC 19.2M */
         { 1000, 12, 0, 12},    /* OSC 12M */

@@ -76,11 +77,11 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
         { 700, 13, 0, 8},
        },
 

arch/arm/cpu/arm720t/tegra-common/cpu.c struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = { · line 83

Quoted 5 lines

arch/arm/cpu/arm720t/tegra-common/cpu.c +0 -5

-       /* TEGRA_SOC2_SLOW: 312 MHz */
-       {{ 312, 13, 0, 12},     /* OSC 13M */
-        { 260, 16, 0, 8},      /* OSC 19.2M */
-        { 312, 12, 0, 12},     /* OSC 12M */
-        { 312, 26, 0, 12},     /* OSC 26M */

Removing TEGRA_SOC2_SLOW should probably be a separate patch, since it doesn't hae anything to do with t114.

Quoted 13 lines

arch/arm/cpu/arm720t/tegra-common/cpu.c +5 -0

+       /* T114: 1.4 GHz */
+       {{ 862, 8, 0, 8},
+        { 583, 8, 0, 4},
+        { 696, 12, 0, 8},
+        { 700, 13, 0, 8},
        },
 };
 

@@ -166,8 +167,8 @@ void init_pllx(void)
        sel = &tegra_pll_x_table[chip_type][osc];
        pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
 

arch/arm/cpu/arm720t/tegra-common/cpu.c void init_pllx(void) · line 171

Quoted 4 lines

arch/arm/cpu/arm720t/tegra-common/cpu.c +2 -2

-       /* adjust PLLP_out1-4 on T30 */
-       if (chip_type == TEGRA_SOC_T30) {
+       /* adjust PLLP_out1-4 on T30/T114 */
+       if (chip_type >= TEGRA_SOC_T30) {

same comment here about >= T30

arch/arm/cpu/arm720t/tegra-common/cpu.c void enable_cpu_clock(int enable) · line 207

Quoted 10 lines

arch/arm/cpu/arm720t/tegra-common/cpu.c +1 -1

                debug("  init_pllx: adjusting PLLP out freqs\n");
                adjust_pllp_out_freqs();
        }

@@ -203,7 +204,7 @@ void enable_cpu_clock(int enable)
         */
        clk = readl(&clkrst->crc_clk_cpu_cmplx);
        clk |= 1 << CPU1_CLK_STP_SHIFT;
-#if defined(CONFIG_TEGRA30)
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)

Can this be runtime instead of #ifdef?

arch/arm/cpu/arm720t/tegra-common/cpu.c void clock_enable_coresight(int enable) · line 312

Quoted 10 lines

arch/arm/cpu/arm720t/tegra-common/cpu.c +1 -1

        clk |= 1 << CPU2_CLK_STP_SHIFT;
        clk |= 1 << CPU3_CLK_STP_SHIFT;
 #endif

@@ -308,7 +309,7 @@ void clock_enable_coresight(int enable)
                 * Clock divider request for 204MHz would setup CSITE clock as
                 * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz
                 */
-               if (tegra_get_chip_type() == TEGRA_SOC_T30)
+               if (tegra_get_chip_type() >= TEGRA_SOC_T30)

same comment here about >= T30

arch/arm/cpu/arm720t/tegra-common/cpu.c void clock_enable_coresight(int enable) · line 322

Quoted 10 lines

arch/arm/cpu/arm720t/tegra-common/cpu.c +1 -1

                        src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
                else
                        src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);

@@ -318,7 +319,7 @@ void clock_enable_coresight(int enable)
                rst = CORESIGHT_UNLOCK;
                writel(rst, CSITE_CPU_DBG0_LAR);
                writel(rst, CSITE_CPU_DBG1_LAR);
-#if defined(CONFIG_TEGRA30)
+#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)

same comment here about runtime vs ifdef

Quoted 11 lines

arch/arm/cpu/arm720t/tegra-common/cpu.c +0 -0

                writel(rst, CSITE_CPU_DBG2_LAR);
                writel(rst, CSITE_CPU_DBG3_LAR);
 #endif

arch/arm/cpu/arm720t/tegra-common/cpu.h +0 -0

index 3e2ea3a..45b346d 100644
@@ -22,14 +22,21 @@
  */
 #include <asm/types.h>
 

arch/arm/cpu/arm720t/tegra-common/cpu.h line 31

Quoted 7 lines

arch/arm/cpu/arm720t/tegra-common/cpu.h +7 -0

+#ifndef TRUE
+#define TRUE   1
+#endif
+#ifndef FALSE
+#define FALSE  0
+#endif
+

u-boot seems a little inconsistent here, but it looks like most of u-boot uses C99 "true" and "false"

Quoted 4 lines

arch/arm/cpu/arm720t/tegra-common/cpu.h +0 -0

 /* Stabilization delays, in usec */
 #define PLL_STABILIZATION_DELAY (300)

arch/arm/cpu/arm720t/tegra-common/cpu.h line 40

Quoted 10 lines

arch/arm/cpu/arm720t/tegra-common/cpu.h +3 -3

 #define IO_STABILIZATION_DELAY (1000)
 
-#if defined(CONFIG_TEGRA30)
-#define NVBL_PLLP_KHZ  (408000)
-#else  /* Tegra20 */
+#if defined(CONFIG_TEGRA20)
 #define NVBL_PLLP_KHZ  (216000)
+#else  /* Tegra30/Tegra114 */
+#define NVBL_PLLP_KHZ  (408000)
 #endif

Again here it's probably better to explicitly do:

#if defined(CONFIG_TEGRA20)
...
#elsif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
...
#else
#error "unknown tegra chip"
#endif

Or better yet, make it runtime if possible.

arch/arm/cpu/arm720t/tegra-common/cpu.h

Quoted 7 lines

arch/arm/cpu/arm720t/tegra-common/cpu.h +6 -0

+
+       /* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
+       reg = readl(&pmc->pmc_cntrl);
+       reg &= ~(CPUPWRREQ_POL);
+       reg |= CPUPWRREQ_OE;
+       writel(reg, &pmc->pmc_cntrl);

clrsetbits_le32() instead?

arch/arm/cpu/arm720t/tegra-common/cpu.h

Quoted 12 lines

arch/arm/cpu/arm720t/tegra-common/cpu.h +11 -0

+
+       /*
+        * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
+        * to 408 to satisfy the requirement of having at least 16 CPU clock
+        * cycles before clamp removal.
+        */
+
+       reg = readl(&clkrst->crc_cpu_softrst_ctrl2);
+       reg &= 0xFFFFF000;      /* bits 11:0 */
+       reg |= 408;
+       writel(reg, &clkrst->crc_cpu_softrst_ctrl2);

clrsetbits_le32() instead?

arch/arm/cpu/arm720t/tegra-common/cpu.h

Quoted 4 lines

arch/arm/cpu/arm720t/tegra-common/cpu.h +4 -0

+       val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
+               (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
+               (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
+               (0 << CLK_SYS_RATE_APB_RATE_SHIFT);

Remove the 0's?

arch/arm/cpu/arm720t/tegra-common/cpu.h

Quoted 3 lines

arch/arm/cpu/arm720t/tegra-common/cpu.h +2 -0

+       writel(val, &clkrst->crc_clk_sys_rate);
+

-Allen
--
nvpublic

These files are used by both SPL and main U-Boot.

arch/arm/cpu/tegra-common/board.c +1 -1

@@ -68,7 +70,7 @@ unsigned int query_sdram_size(void)
 	case 3:
 		return 0x40000000;	/* 1GB */
 	}
-#else	/* Tegra30 */
+#elif defined(CONFIG_TEGRA30)
 	/* bits 31:28 in OdmData are used for RAM size on T30  */
 	switch ((reg) >> 28) {
 	case 0:

Quoted 14 lines · Tom Warren

These files are used by both SPL and main U-Boot.

arch/arm/cpu/tegra-common/board.c +1 -1

@@ -68,7 +70,7 @@ unsigned int query_sdram_size(void)
      case 3:
              return 0x40000000;      /* 1GB */
      }
-#else        /* Tegra30 */
+#elif defined(CONFIG_TEGRA30)
      /* bits 31:28 in OdmData are used for RAM size on T30  */
      switch ((reg) >> 28) {
      case 0:

arch/arm/cpu/tegra-common/board.c unsigned int query_sdram_size(void) · line 90

Quoted 5 lines

arch/arm/cpu/tegra-common/board.c +2 -0

@@ -84,6 +86,8 @@ unsigned int query_sdram_size(void)
      case 8:
              return 0x7ff00000;      /* 2GB - 1MB */
      }
+#else
+             return 0x7ff00000;      /* 2GB - 1MB */

Indentation looks wrong.

I doubt all Tegra114 systems have 2GB RAM; is there no ODMDATA field allocated for the RAM size? I know there was some discussion of removing it from ODMDATA and simply reading a memory controller register, since the information was duplicated there.

arch/arm/cpu/tegra114-common/pinmux.c

Quoted 3 lines

arch/arm/cpu/tegra114-common/clock.c +0 -0

arch/arm/cpu/tegra114-common/pinmux.c +0 -0

I didn't review those two files.

Quoted 3 lines · Tom Warren

These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.).

board/nvidia/dts/tegra114-dalmore.dts line 12

Quoted 6 lines

board/nvidia/dts/tegra114-dalmore.dts +4 -0

 
+     memory {
+             device_type = "memory";
+             reg = <0x80000000 0x40000000>;
+     };

Indeed, that says just 1GB...

Stephen,

Quoted 12 lines · Stephen Warren

Quoted 10 lines · Tom Warren

These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.).

board/nvidia/dts/tegra114-dalmore.dts +4 -0

 
+     memory {
+             device_type = "memory";
+             reg = <0x80000000 0x40000000>;
+     };

Quoted 2 lines

Indeed, that says just 1GB...

True, but that's what's in current Cardhu DTS, and Harmony, Seaboard, and Ventana DTS files. Only Whistler has 0x20000000 (512MB).

How is this used, and how do we keep it in sync with what's really on the board/in the ODMDATA field?

Quoted 21 lines · Tom Warren

Stephen,

Quoted 5 lines · Stephen Warren

Quoted 3 lines · Tom Warren

These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.).

Quoted 9 lines

board/nvidia/dts/tegra114-dalmore.dts line 12

Quoted 6 lines

board/nvidia/dts/tegra114-dalmore.dts +4 -0

 
+     memory {
+             device_type = "memory";
+             reg = <0x80000000 0x40000000>;
+     };

Indeed, that says just 1GB...

True, but that's what's in current Cardhu DTS, and Harmony, Seaboard, and Ventana DTS files. Only Whistler has 0x20000000 (512MB).

Quoted 2 lines

How is this used, and how do we keep it in sync with what's really on the board/in the ODMDATA field?

I don't believe U-Boot uses that property from the DT. Probably the DT isn't parsed early enough for it to be useful. But if we add it to the .dts file, it may as well be correct even so. Or, perhaps we should just remove it from the U-Boot DT since it isn't useful.

Stephen,

Quoted 25 lines · Stephen Warren

Quoted 23 lines · Tom Warren

Stephen,

Quoted 5 lines · Stephen Warren

Quoted 3 lines · Tom Warren

These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.).

Quoted 9 lines

board/nvidia/dts/tegra114-dalmore.dts line 12

Quoted 6 lines

board/nvidia/dts/tegra114-dalmore.dts +4 -0

 
+     memory {
+             device_type = "memory";
+             reg = <0x80000000 0x40000000>;
+     };

Indeed, that says just 1GB...

True, but that's what's in current Cardhu DTS, and Harmony, Seaboard, and Ventana DTS files. Only Whistler has 0x20000000 (512MB).

How is this used, and how do we keep it in sync with what's really on the board/in the ODMDATA field?

Quoted 4 lines

I don't believe U-Boot uses that property from the DT. Probably the DT isn't parsed early enough for it to be useful. But if we add it to the .dts file, it may as well be correct even so. Or, perhaps we should just remove it from the U-Boot DT since it isn't useful.

Another candidate for a clean-up pass patchset over all Tegra code. For now, I'll bump it to 2GB for Dalmore (and Cardhu), since that's what's on the sample boards.

Quoted 28 lines · Tom Warren

Stephen,

Quoted 25 lines · Stephen Warren

Quoted 23 lines · Tom Warren

Stephen,

Quoted 5 lines · Stephen Warren

Quoted 3 lines · Tom Warren

These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.).

Quoted 9 lines

board/nvidia/dts/tegra114-dalmore.dts line 12

Quoted 6 lines

board/nvidia/dts/tegra114-dalmore.dts +4 -0

 
+     memory {
+             device_type = "memory";
+             reg = <0x80000000 0x40000000>;
+     };

Indeed, that says just 1GB...

True, but that's what's in current Cardhu DTS, and Harmony, Seaboard, and Ventana DTS files. Only Whistler has 0x20000000 (512MB).

How is this used, and how do we keep it in sync with what's really on the board/in the ODMDATA field?

Quoted 8 lines

Quoted 4 lines

I don't believe U-Boot uses that property from the DT. Probably the DT isn't parsed early enough for it to be useful. But if we add it to the .dts file, it may as well be correct even so. Or, perhaps we should just remove it from the U-Boot DT since it isn't useful.

Another candidate for a clean-up pass patchset over all Tegra code. For now, I'll bump it to 2GB for Dalmore (and Cardhu), since that's what's on the sample boards.

1GB would be safer for Cardhu; there are certainly very commonly used Cardhu SKUs with only 1GB of RAM. I have one. In fact, I once heard that most Linux-oriented Cardhu were 1GB and the 2GB devices were mostly used for Windows development.

Quoted 2 lines · Tom Warren

This build is stripped down. It boots to the command prompt. GPIO is the only peripheral supported. Others TBD.

board/nvidia/dalmore/dalmore.c line 35

Quoted 6 lines

board/nvidia/dalmore/dalmore.c +4 -0

 
+void pinmux_init(void)
+{
+     pinmux_config_table(tegra3_pinmux_common,
+             ARRAY_SIZE(tegra3_pinmux_common));

I assume that should say "tegra114" not "tegra3"?

include/configs/dalmore.h line 25

Quoted 4 lines

include/configs/dalmore.h +2 -0

 
+/* Must be off for Dalmore to boot !?!? FIXME */
+#define CONFIG_SYS_DCACHE_OFF

Who knows if there is any A15 core/cache controller support in U-Boot yet?

Aside from any comments I've made, the series, briefly,

Reviewed-by Stephen Warren <[email protected]>

board/nvidia/dalmore/dalmore.c line 35

Quoted 9 lines · Tom Warren

This build is stripped down. It boots to the command prompt. GPIO is the only peripheral supported. Others TBD.

board/nvidia/dalmore/dalmore.c +4 -0

 
+void pinmux_init(void)
+{
+     pinmux_config_table(tegra3_pinmux_common,
+             ARRAY_SIZE(tegra3_pinmux_common));

I assume that should say "tegra114" not "tegra3"?

include/configs/dalmore.h line 25

Quoted 4 lines

include/configs/dalmore.h +2 -0

 
+/* Must be off for Dalmore to boot !?!? FIXME */
+#define CONFIG_SYS_DCACHE_OFF

Who knows if there is any A15 core/cache controller support in U-Boot yet?

Aside from any comments I've made, the series, briefly,

Reviewed-by Stephen Warren <[email protected]>

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Hi Stephen,

Quoted 15 lines · Stephen Warren

board/nvidia/dalmore/dalmore.c line 35

Quoted 9 lines · Tom Warren

This build is stripped down. It boots to the command prompt. GPIO is the only peripheral supported. Others TBD.

board/nvidia/dalmore/dalmore.c +4 -0

 
+void pinmux_init(void)
+{
+     pinmux_config_table(tegra3_pinmux_common,
+             ARRAY_SIZE(tegra3_pinmux_common));

I assume that should say "tegra114" not "tegra3"?

Quoted 1 line

include/configs/dalmore.h +0 -0

Quoted 4 lines

include/configs/dalmore.h line 25

Quoted 2 lines

include/configs/dalmore.h +2 -0

+/* Must be off for Dalmore to boot !?!? FIXME */
+#define CONFIG_SYS_DCACHE_OFF

Who knows if there is any A15 core/cache controller support in U-Boot yet?

Sort-of. It works ok for me on snow, so long as you have a patch to enable L2 support.

Regards,
Simon

Quoted 7 lines

Aside from any comments I've made, the series, briefly,

Reviewed-by Stephen Warren <[email protected]>

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Simon,

Quoted 23 lines · Simon Glass

Hi Stephen,

Quoted 19 lines · Stephen Warren

board/nvidia/dalmore/dalmore.c line 35

Quoted 9 lines · Tom Warren

This build is stripped down. It boots to the command prompt. GPIO is the only peripheral supported. Others TBD.

board/nvidia/dalmore/dalmore.c +4 -0

 
+void pinmux_init(void)
+{
+     pinmux_config_table(tegra3_pinmux_common,
+             ARRAY_SIZE(tegra3_pinmux_common));

I assume that should say "tegra114" not "tegra3"?

include/configs/dalmore.h line 25

Quoted 4 lines

include/configs/dalmore.h +2 -0

 
+/* Must be off for Dalmore to boot !?!? FIXME */
+#define CONFIG_SYS_DCACHE_OFF

Who knows if there is any A15 core/cache controller support in U-Boot yet?

Quoted 2 lines

Sort-of. It works ok for me on snow, so long as you have a patch to enable L2 support.

Which patch, exactly, to enable L2 support? I'd like to test it on T114.

Thanks

Quoted 11 lines

Regards,
Simon

Quoted 7 lines

Aside from any comments I've made, the series, briefly,

Reviewed-by Stephen Warren <[email protected]>

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot