clk: tegra: initialise parent of uart clocks
Subsystems (3)
PATCH 1/1 clk: tegra: initialise parent of uart clocks
Initialise the parent of UARTs to PLLP and disabling clock by default.
--- drivers/clk/tegra/clk-tegra20.c | 3 +++ drivers/clk/tegra/clk-tegra30.c | 4 ++++ 2 files changed, 7 insertions(+), 0 deletions(-)
drivers/clk/tegra/clk-tegra20.c +3 -0
@@ -1252,7 +1252,10 @@ static __initdata struct tegra_clk_init_table init_table[] = { {emc, clk_max, 0, 1}, {cclk, clk_max, 0, 1}, {uarta, pll_p, 0, 1}, + {uartb, pll_p, 0, 0}, + {uartc, pll_p, 0, 0}, {uartd, pll_p, 0, 1}, + {uarte, pll_p, 0, 0}, {usbd, clk_max, 12000000, 0}, {usb2, clk_max, 12000000, 0}, {usb3, clk_max, 12000000, 0},
drivers/clk/tegra/clk-tegra30.c +4 -0
@@ -1875,6 +1875,10 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {static __initdata struct tegra_clk_init_table init_table[] = { {uarta, pll_p,408000000 ,1 }, + {uartb, pll_p,408000000 ,0 }, + {uartc, pll_p,408000000 ,0 }, + {uartd, pll_p,408000000 ,0 }, + {uarte, pll_p,408000000 ,0 }, {pll_a, clk_max,564480000 ,1 }, {pll_a_out0, clk_max,11289600 ,1 }, {extern1, pll_a_out0,0 ,1 },
Signature · 1 line
1.7.1.1
Quoted 3 lines · Laxman Dewangan
Initialise the parent of UARTs to PLLP and disabling clock by default.
I wonder if we should move the parent definitions to DT at some point.
Cheers,
Peter.
Quoted 6 lines · Peter De Schrijver
Quoted 3 lines · Laxman Dewangan
Initialise the parent of UARTs to PLLP and disabling clock by default.
I wonder if we should move the parent definitions to DT at some point.
I think that's what Prashant is going to work on next, right?
Quoted 1 line · Laxman Dewangan
Initialise the parent of UARTs to PLLP
OK
Quoted 1 line
and disabling clock by default.
Hmm. Only the clocks initialized by the new entries you added are marked disabled (or rather, not actively enabled; if they're enabled already, they won't be disabled). We should treat all UARTs equally. Historically we've needed to enable the serial clocks forcibly since the regular serial driver didn't call clk_get() or clk_prepare_enable() on any clocks, but I notice that it does now, since sometime in kernel 3.8. As such, I think you can modify all the UART entries in these tables to have the enable/state field set to false (0). Can you try that and check that it works for the serial console ports? Thanks.
Quoted 5 lines · Stephen Warren
Quoted 1 line · Laxman Dewangan
Initialise the parent of UARTs to PLLP
OK
Quoted 1 line
and disabling clock by default.
Quoted 9 lines
Hmm. Only the clocks initialized by the new entries you added are marked disabled (or rather, not actively enabled; if they're enabled already, they won't be disabled). We should treat all UARTs equally. Historically we've needed to enable the serial clocks forcibly since the regular serial driver didn't call
clk_get()orclk_prepare_enable()on any clocks, but I notice that it does now, since sometime in kernel 3.8. As such, I think you can modify all the UART entries in these tables to have the enable/state field set to false (0). Can you try that and check that it works for the serial console ports? Thanks.
Yes, this work even if I make state to 0 (disabled) in clock init table. The of_serial driver call the clk_prepare_enable() if property "clock_frequency" is there in dt node and in our dts file, we have already this property.
I sent V2 patch.