Tegra: USB: EHCI: add Tegra30 compatible support
Subsystems (5)
cover Tegra: USB: EHCI: add Tegra30 compatible support
Tegra114 USB EHCI is compatible with Tegra30 USB EHCI except:
1. Port Reset - Tegra30 takes 55ms, Tegra114 takes 50 ms to finish.
2. PLL parameters.
Jim Lin (3):
ARM: Tegra: FDT: Add USB support for T20/T30/T114
ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Tegra: Config: Enable Tegra30/Tegra114 USB function
arch/arm/dts/tegra114.dtsi | 105 ++++++++ arch/arm/dts/tegra20.dtsi | 81 ++++++ arch/arm/dts/tegra30.dtsi | 108 ++++++++ arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249 ------------------ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra114/usb.h | 287 +++++++++++++++++++++ arch/arm/include/asm/arch-tegra20/usb.h | 279 +++++++++++++++++++++ arch/arm/include/asm/arch-tegra30/usb.h | 294 ++++++++++++++++++++++ board/nvidia/common/board.c | 2 +- board/nvidia/dts/tegra114-dalmore.dts | 7 + board/nvidia/dts/tegra30-cardhu.dts | 6 + drivers/usb/host/ehci-hcd.c | 40 ++- drivers/usb/host/ehci-tegra.c | 376 ++++++++++++++++++++------- include/configs/cardhu.h | 14 + include/configs/dalmore.h | 14 + include/configs/tegra114-common.h | 3 + include/configs/tegra30-common.h | 3 + include/fdtdec.h | 2 + lib/fdtdec.c | 2 + 20 files changed, 1523 insertions(+), 360 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/usb.h create mode 100644 arch/arm/include/asm/arch-tegra114/usb.h create mode 100644 arch/arm/include/asm/arch-tegra20/usb.h create mode 100644 arch/arm/include/asm/arch-tegra30/usb.h
Signature · 1 line
1.7.7
PATCH 1/3 ARM: Tegra: FDT: Add USB support for T20/T30/T114
Add DT node for USB function.
--- arch/arm/dts/tegra114.dtsi | 105 ++++++++++++++++++++++++++++++++ arch/arm/dts/tegra20.dtsi | 81 ++++++++++++++++++++++++ arch/arm/dts/tegra30.dtsi | 108 +++++++++++++++++++++++++++++++++ board/nvidia/dts/tegra114-dalmore.dts | 7 ++ board/nvidia/dts/tegra30-cardhu.dts | 6 ++ include/fdtdec.h | 2 + lib/fdtdec.c | 2 + 7 files changed, 311 insertions(+), 0 deletions(-)
arch/arm/dts/tegra114.dtsi +105 -0
@@ -216,4 +216,109 @@ clocks = <&tegra_car 15>; status = "disable"; }; + +/* This table has USB timing parameters for each Oscillator frequency we + * support. There are four sets of values: + * + * 1. PLLU configuration information (reference clock is osc/clk_m and + * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). + * Reference frequency MHZ 12.0 13.0 19.2 26.0 + * ---------------------------------------------------- + * DIVN 960 960 200 960 + * DIVM 12 13 4 26 + * CPCON 12 12 3 12 + * LFCON 2 2 2 2 + * + * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: + * Reference frequency MHZ 12.0 13.0 19.2 26.0 + * ---------------------------------------------------- + * PLLU_ENABLE_DLY_COUNT 02 2 3 4 + * PLLU_STABLE_COUNT 47 51 75 102 + * PLL_ACTIVE_DLY_COUNT 08 9 12 9 + * XTAL_FREQ_COUNT 118 127 188 254 + * + * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and + * SessEnd. Each of these signals have their own debouncer and for each of + * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or + * BIAS_DEBOUNCE_B). + * + * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: + * 0xffff -> No debouncing at all + * <n> ms = <n> * 1000 / (1/19.2MHz) / 4 + * + * So to program a 10 ms debounce for BIAS_DEBOUNCE_A, we have: + * BIAS_DEBOUNCE_A[15:0] = 10 * 1000 * 19.2 / 4 = 48000 = 0xBB80 + * + * We need to use only DebounceA for BOOTROM. We don't need the DebounceB + * values, so we can keep those to default. + * + * 4. The 20 microsecond delay after bias cell operation. + * UTMIP_BIAS_PAD_TRK_COUNT + * + * enum { + * PARAM_DIVN, // PLL FEEDBACK DIVIDER + * PARAM_DIVM, // PLL INPUT DIVIDER + * PARAM_DIVP, // POST DIVIDER (2^N) + * PARAM_CPCON, // BASE PLLC CHARGE Pump setup ctrl + * PARAM_LFCON, // BASE PLLC LOOP FILter setup ctrl + * PARAM_ENABLE_DELAY_COUNT, // PLL-U Enable Delay Count + * PARAM_STABLE_COUNT, // PLL-U STABLE count + * PARAM_ACTIVE_DELAY_COUNT, // PLL-U Active delay count + * PARAM_XTAL_FREQ_COUNT, // PLL-U XTAL frequency count + * PARAM_DEBOUNCE_A_TIME, // 10MS DELAY for BIAS_DEBOUNCE_A + * PARAM_BIAS_TIME, // 20US DELAY AFter bias cell op + * // UTMIP_BIAS_PAD_TRK_COUNT + *}; + */ + usbparams at 0 { + compatible = "nvidia,usbparams"; + osc-frequency = <13000000>; + /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ + params = <0x3c0 0x0d 0x00 0xc 2 0x02 0x33 0x09 0x7f 0x7ef4 6>; + }; + + usbparams at 1 { + compatible = "nvidia,usbparams"; + osc-frequency = <19200000>; + params = <0x0c8 0x04 0x00 0x3 2 0x03 0x4b 0x0c 0xbc 0xbb80 8>; + }; + + usbparams at 2 { + compatible = "nvidia,usbparams"; + osc-frequency = <12000000>; + params = <0x3c0 0x0c 0x00 0xc 2 0x02 0x2f 0x08 0x76 0x7530 5>; + }; + + usbparams at 3 { + compatible = "nvidia,usbparams"; + osc-frequency = <26000000>; + params = <0x3c0 0x1a 0x00 0xc 2 0x04 0x66 0x09 0xfe 0xfde8 0xb>; + }; + + usb at 7d000000 { + compatible = "nvidia,tegra30-ehci", "nvidia,tegra114-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = < 52 >; + phy_type = "utmi"; + clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ + status = "disabled"; + }; + + usb at 7d004000 { + compatible = "nvidia,tegra30-ehci", "nvidia,tegra114-ehci"; + reg = <0x7d004000 0x4000>; + interrupts = < 53 >; + phy_type = "utmi"; + clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ + status = "disabled"; + }; + + usb at 7d008000 { + compatible = "nvidia,tegra30-ehci", "nvidia,tegra114-ehci"; + reg = <0x7d008000 0x4000>; + interrupts = < 129 >; + phy_type = "utmi"; + clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ + status = "disabled"; + }; };
arch/arm/dts/tegra20.dtsi +81 -0
87 lines not on this page · raw message
arch/arm/dts/tegra30.dtsi +108 -0
112 lines not on this page · raw message
board/nvidia/dts/tegra114-dalmore.dts +7 -0
@@ -14,6 +14,7 @@ i2c4 = "/i2c at 7000c700"; sdhci0 = "/sdhci at 78000600"; sdhci1 = "/sdhci at 78000400"; + usb0 = "/usb at 7d008000"; }; memory {
@@ -61,4 +62,10 @@ bus-width = <8>; status = "okay"; }; + + usb at 7d008000 { + /* SPDIF_IN: USB_VBUS_EN1 */ + nvidia,vbus-gpio = <&gpio 86 0>; + status = "okay"; + }; };
board/nvidia/dts/tegra30-cardhu.dts +6 -0
@@ -14,6 +14,7 @@ i2c4 = "/i2c at 7000c700"; sdhci0 = "/sdhci at 78000600"; sdhci1 = "/sdhci at 78000000"; + usb0 = "/usb at 7d008000"; }; memory {
@@ -63,4 +64,9 @@ status = "okay"; bus-width = <8>; }; + + usb at 7d008000 { + nvidia,vbus-gpio = <&gpio 233 3>; /* PDD1, EN_3V3_PU */ + status = "okay"; + }; };
include/fdtdec.h +2 -0
@@ -64,6 +64,8 @@ struct fdt_memory {enum fdt_compat_id {COMPAT_UNKNOWN ,COMPAT_NVIDIA_TEGRA20_USB ,/* Tegra20 USB port */ +COMPAT_NVIDIA_TEGRA30_USB ,/* Tegra30 USB port */ +COMPAT_NVIDIA_TEGRA114_USB ,/* Tegra114 USB port */ COMPAT_NVIDIA_TEGRA114_I2C ,/* Tegra114 I2C w/single clock source */ COMPAT_NVIDIA_TEGRA20_I2C ,/* Tegra20 i2c */ COMPAT_NVIDIA_TEGRA20_DVC ,/* Tegra20 dvc (really just i2c) */
lib/fdtdec.c +2 -0
@@ -37,6 +37,8 @@ DECLARE_GLOBAL_DATA_PTR;static const char *const compat_names[COMPAT_COUNT ] = {COMPAT (UNKNOWN ,"<none>" ),COMPAT (NVIDIA_TEGRA20_USB ,"nvidia,tegra20-ehci" ), +COMPAT (NVIDIA_TEGRA30_USB ,"nvidia,tegra30-ehci" ), +COMPAT (NVIDIA_TEGRA114_USB ,"nvidia,tegra114-ehci" ),COMPAT (NVIDIA_TEGRA114_I2C ,"nvidia,tegra114-i2c" ),COMPAT (NVIDIA_TEGRA20_I2C ,"nvidia,tegra20-i2c" ),COMPAT (NVIDIA_TEGRA20_DVC ,"nvidia,tegra20-i2c-dvc" ),
Signature · 1 line
1.7.7
PATCH 1/3 ARM: Tegra: FDT: Add USB support for T20/T30/T114
Quoted 71 lines · Jim Lin
Add DT node for USB function.
arch/arm/dts/tegra114.dtsi +67
-0+/* This table has USB timing parameters for each Oscillator frequency we + * support. There are four sets of values: + * + * 1. PLLU configuration information (reference clock is osc/clk_m and + * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). + * Reference frequency MHZ 12.0 13.0 19.2 26.0 + * ---------------------------------------------------- + * DIVN 960 960 200 960 + * DIVM 12 13 4 26 + * CPCON 12 12 3 12 + * LFCON 2 2 2 2 + * + * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: + * Reference frequency MHZ 12.0 13.0 19.2 26.0 + * ---------------------------------------------------- + * PLLU_ENABLE_DLY_COUNT 02 2 3 4 + * PLLU_STABLE_COUNT 47 51 75 102 + * PLL_ACTIVE_DLY_COUNT 08 9 12 9 + * XTAL_FREQ_COUNT 118 127 188 254 + * + * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and + * SessEnd. Each of these signals have their own debouncer and for each of + * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or + * BIAS_DEBOUNCE_B). + * + * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: + * 0xffff -> No debouncing at all + * <n> ms = <n> * 1000 / (1/19.2MHz) / 4 + * + * So to program a 10 ms debounce for BIAS_DEBOUNCE_A, we have: + * BIAS_DEBOUNCE_A[15:0] = 10 * 1000 * 19.2 / 4 = 48000 = 0xBB80 + * + * We need to use only DebounceA for BOOTROM. We don't need the DebounceB + * values, so we can keep those to default. + * + * 4. The 20 microsecond delay after bias cell operation. + * UTMIP_BIAS_PAD_TRK_COUNT + * + * enum { + * PARAM_DIVN, // PLL FEEDBACK DIVIDER + * PARAM_DIVM, // PLL INPUT DIVIDER + * PARAM_DIVP, // POST DIVIDER (2^N) + * PARAM_CPCON, // BASE PLLC CHARGE Pump setup ctrl + * PARAM_LFCON, // BASE PLLC LOOP FILter setup ctrl + * PARAM_ENABLE_DELAY_COUNT, // PLL-U Enable Delay Count + * PARAM_STABLE_COUNT, // PLL-U STABLE count + * PARAM_ACTIVE_DELAY_COUNT, // PLL-U Active delay count + * PARAM_XTAL_FREQ_COUNT, // PLL-U XTAL frequency count + * PARAM_DEBOUNCE_A_TIME, // 10MS DELAY for BIAS_DEBOUNCE_A + * PARAM_BIAS_TIME, // 20US DELAY AFter bias cell op + * // UTMIP_BIAS_PAD_TRK_COUNT + *}; + */ + usbparams at 0 { + compatible = "nvidia,usbparams"; + osc-frequency = <13000000>; + /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ + params = <0x3c0 0x0d 0x00 0xc 2 0x02 0x33 0x09 0x7f 0x7ef4 6>; + }; + + usbparams at 1 { + compatible = "nvidia,usbparams"; + osc-frequency = <19200000>; + params = <0x0c8 0x04 0x00 0x3 2 0x03 0x4b 0x0c 0xbc 0xbb80 8>; + }; + + usbparams at 2 {
arch/arm/dts/tegra114.dtsi line 296
Quoted 10 lines
arch/arm/dts/tegra114.dtsi +10
-0+ compatible = "nvidia,usbparams"; + osc-frequency = <12000000>; + params = <0x3c0 0x0c 0x00 0xc 2 0x02 0x2f 0x08 0x76 0x7530 5>; + }; + + usbparams at 3 { + compatible = "nvidia,usbparams"; + osc-frequency = <26000000>; + params = <0x3c0 0x1a 0x00 0xc 2 0x04 0x66 0x09 0xfe 0xfde8 0xb>; + };
None of the above should be present; this is SoC-specific information and should be part of the USB driver itself. There's no benefit to putting the information into DT just to parse it back out into the same tables that the driver could have contained in the first place.
The same comment applies to all 3 tegra*.dtsi files. For the Tegra20 case, please make sure that what you add here is identical to what has been proposed for the final kernel USB bindings. Ask Venu (now CC'd) for a pointer to that.
arch/arm/dts/tegra114.dtsi line 301
Quoted 4 lines
arch/arm/dts/tegra114.dtsi +4
-0+ usb at 7d000000 { + compatible = "nvidia,tegra30-ehci", "nvidia,tegra114-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = < 52 >;
There shouldn't be spaces after < or before >.
The bindings here don't match the kernel. Please make sure they do.
This patch only touches 2 board files: Cardhu and Dalmore. Will USB support on other boards continue to work without any DT changes? Existing functionality can't be broken. I'd expect to see a bunch more DT files edited here.
PATCH 1/3 ARM: Tegra: FDT: Add USB support for T20/T30/T114
Quoted 79 lines · Stephen Warren
Quoted 78 lines · Jim Lin
Add DT node for USB function.
arch/arm/dts/tegra114.dtsi +74
-0+/* This table has USB timing parameters for each Oscillator frequency we + * support. There are four sets of values: + * + * 1. PLLU configuration information (reference clock is osc/clk_m and + * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). + * Reference frequency MHZ 12.0 13.0 19.2 26.0 + * ---------------------------------------------------- + * DIVN 960 960 200 960 + * DIVM 12 13 4 26 + * CPCON 12 12 3 12 + * LFCON 2 2 2 2 + * + * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: + * Reference frequency MHZ 12.0 13.0 19.2 26.0 + * ---------------------------------------------------- + * PLLU_ENABLE_DLY_COUNT 02 2 3 4 + * PLLU_STABLE_COUNT 47 51 75 102 + * PLL_ACTIVE_DLY_COUNT 08 9 12 9 + * XTAL_FREQ_COUNT 118 127 188 254 + * + * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and + * SessEnd. Each of these signals have their own debouncer and for each of + * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or + * BIAS_DEBOUNCE_B). + * + * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: + * 0xffff -> No debouncing at all + * <n> ms = <n> * 1000 / (1/19.2MHz) / 4 + * + * So to program a 10 ms debounce for BIAS_DEBOUNCE_A, we have: + * BIAS_DEBOUNCE_A[15:0] = 10 * 1000 * 19.2 / 4 = 48000 = 0xBB80 + * + * We need to use only DebounceA for BOOTROM. We don't need the DebounceB + * values, so we can keep those to default. + * + * 4. The 20 microsecond delay after bias cell operation. + * UTMIP_BIAS_PAD_TRK_COUNT + * + * enum { + * PARAM_DIVN, // PLL FEEDBACK DIVIDER + * PARAM_DIVM, // PLL INPUT DIVIDER + * PARAM_DIVP, // POST DIVIDER (2^N) + * PARAM_CPCON, // BASE PLLC CHARGE Pump setup ctrl + * PARAM_LFCON, // BASE PLLC LOOP FILter setup ctrl + * PARAM_ENABLE_DELAY_COUNT, // PLL-U Enable Delay Count + * PARAM_STABLE_COUNT, // PLL-U STABLE count + * PARAM_ACTIVE_DELAY_COUNT, // PLL-U Active delay count + * PARAM_XTAL_FREQ_COUNT, // PLL-U XTAL frequency count + * PARAM_DEBOUNCE_A_TIME, // 10MS DELAY for BIAS_DEBOUNCE_A + * PARAM_BIAS_TIME, // 20US DELAY AFter bias cell op + * // UTMIP_BIAS_PAD_TRK_COUNT + *}; + */ + usbparams at 0 { + compatible = "nvidia,usbparams"; + osc-frequency = <13000000>; + /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ + params = <0x3c0 0x0d 0x00 0xc 2 0x02 0x33 0x09 0x7f 0x7ef4 6>; + }; + + usbparams at 1 { + compatible = "nvidia,usbparams"; + osc-frequency = <19200000>; + params = <0x0c8 0x04 0x00 0x3 2 0x03 0x4b 0x0c 0xbc 0xbb80 8>; + }; + + usbparams at 2 { + compatible = "nvidia,usbparams"; + osc-frequency = <12000000>; + params = <0x3c0 0x0c 0x00 0xc 2 0x02 0x2f 0x08 0x76 0x7530 5>; + }; + + usbparams at 3 { + compatible = "nvidia,usbparams";
Quoted 8 lines
arch/arm/dts/tegra114.dtsi line 296
Quoted 3 lines
arch/arm/dts/tegra114.dtsi +3
-0+ osc-frequency = <26000000>; + params = <0x3c0 0x1a 0x00 0xc 2 0x04 0x66 0x09 0xfe 0xfde8 0xb>; + };None of the above should be present; this is SoC-specific information and should be part of the USB driver itself. There's no benefit to putting the information into DT just to parse it back out into the same tables that the driver could have contained in the first place.
Parameters are not completely same for T20, T30, and T114. Putting over dt file is for expanding on future chips.
Quoted 13 lines
The same comment applies to all 3 tegra*.dtsi files. For the Tegra20 case, please make sure that what you add here is identical to what has been proposed for the final kernel USB bindings. Ask Venu (now CC'd) for a pointer to that.
arch/arm/dts/tegra114.dtsi line 301
Quoted 4 lines
arch/arm/dts/tegra114.dtsi +4
-0+ usb at 7d000000 { + compatible = "nvidia,tegra30-ehci", "nvidia,tegra114-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = < 52 >;There shouldn't be spaces after < or before >.
Quoted 5 lines
The bindings here don't match the kernel. Please make sure they do. This patch only touches 2 board files: Cardhu and Dalmore. Will USB support on other boards continue to work without any DT changes? Existing functionality can't be broken. I'd expect to see a bunch more DT files edited here.
For T20, I only have Seaboard and Harmony platforms.
For other T20 platforms, I may blindly add USB support as you suggested, is that okay?
--
nvpublic
PATCH 1/3 ARM: Tegra: FDT: Add USB support for T20/T30/T114
Quoted 8 lines · Jim Lin
Quoted 7 lines · Stephen Warren
Quoted 6 lines · Jim Lin
Add DT node for USB function.
arch/arm/dts/tegra114.dtsi +2
-0+/* This table has USB timing parameters for each Oscillator frequency we + * support. There are four sets of values:
...
Quoted 11 lines
Quoted 10 lines
arch/arm/dts/tegra114.dtsi line 296
Quoted 5 lines
arch/arm/dts/tegra114.dtsi +5
-0+ usbparams at 3 { + compatible = "nvidia,usbparams"; + osc-frequency = <26000000>; + params = <0x3c0 0x1a 0x00 0xc 2 0x04 0x66 0x09 0xfe 0xfde8 0xb>; + };None of the above should be present; this is SoC-specific information and should be part of the USB driver itself. There's no benefit to putting the information into DT just to parse it back out into the same tables that the driver could have contained in the first place.
Quoted 2 lines
Parameters are not completely same for T20, T30, and T114. Putting over dt file is for expanding on future chips.
The driver itself is going to need to change anything in all likelihood, so there's no point attempting to put the parameters somewhere else to avoid changing the driver.
Even ignoring all that, the USB DT binding for Tegra is already defined, and does not include this information, so it must be in the driver.
...
Quoted 9 lines
Quoted 5 lines
The bindings here don't match the kernel. Please make sure they do. This patch only touches 2 board files: Cardhu and Dalmore. Will USB support on other boards continue to work without any DT changes? Existing functionality can't be broken. I'd expect to see a bunch more DT files edited here.
For T20, I only have Seaboard and Harmony platforms.
For other T20 platforms, I may blindly add USB support as you suggested, is that okay?
Yes, please update all Tegra boards so that nothing breaks. For boards you don't have, others can perform the testing once you've posted the patches.
PATCH 1/3 ARM: Tegra: FDT: Add USB support for T20/T30/T114
In reply to Stephen WarrenQuoted 20 lines
-----Original Message-----
From: Stephen Warren [mailto:swarren at wwwdotorg.org]
Sent: Friday, May 03, 2013 12:40 AM
To: Jim Lin
Cc: u-boot at lists.denx.de; marex at denx.de; Stephen Warren; Tom Warren; Venu Byravarasu
Subject: Re: [U-Boot] [PATCH 1/3] ARM: Tegra: FDT: Add USB support for T20/T30/T114arch/arm/dts/tegra114.dtsi
Quoted 7 lines · Jim Lin
Add DT node for USB function.
arch/arm/dts/tegra114.dtsi +3
-0+/* This table has USB timing parameters for each Oscillator frequency we + * support. There are four sets of values: + *
Quoted 4 lines
The same comment applies to all 3 tegra*.dtsi files. For the Tegra20 case, please make sure that what you add here is identical to what has been proposed for the final kernel USB bindings. Ask Venu (now CC'd) for a pointer to that.
Plz see attached file for finalized Tegra20 DT bindings.
Quoted 8 lines
arch/arm/dts/tegra114.dtsi line 301
Quoted 5 lines
arch/arm/dts/tegra114.dtsi +4
-0+ usb at 7d000000 { + compatible = "nvidia,tegra30-ehci", "nvidia,tegra114-ehci"; + reg = <0x7d000000 0x4000>; + interrupts = < 52 >;There shouldn't be spaces after < or before >.
Quoted 6 lines
The bindings here don't match the kernel. Please make sure they do.
This patch only touches 2 board files: Cardhu and Dalmore. Will USB support on other boards continue to work without any DT changes? Existing functionality can't be broken. I'd expect to see a bunch more DT files edited here.
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PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
In reply to Jim LinTegra30 and Tegra114 are compatible except
1. T30 takes 55 ms to finish Port Reset. T114 takes 50 ms.
2. PLL parameters
Tested on Tegra20 Harmony/Seaboard, Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well.
--- arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249 ------------------ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra114/usb.h | 287 +++++++++++++++++++++ arch/arm/include/asm/arch-tegra20/usb.h | 279 +++++++++++++++++++++ arch/arm/include/asm/arch-tegra30/usb.h | 294 ++++++++++++++++++++++ board/nvidia/common/board.c | 2 +- drivers/usb/host/ehci-hcd.c | 40 ++- drivers/usb/host/ehci-tegra.c | 376 ++++++++++++++++++++------- 9 files changed, 1178 insertions(+), 360 deletions(-) delete mode 100644 arch/arm/include/asm/arch-tegra/usb.h create mode 100644 arch/arm/include/asm/arch-tegra114/usb.h create mode 100644 arch/arm/include/asm/arch-tegra20/usb.h create mode 100644 arch/arm/include/asm/arch-tegra30/usb.h
arch/arm/include/asm/arch-tegra/clk_rst.h +10 -0
@@ -225,6 +225,16 @@ enum { IN_408_OUT_9_6_DIVISOR = 83, }; +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */ +#define PLLU_POWERDOWN (1 << 16) +#define PLL_ENABLE_POWERDOWN (1 << 14) +#define PLL_ACTIVE_POWERDOWN (1 << 12) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */ +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) +/* CLK_RST_CONTROLLER_OSC_CTRL_0 */ #define OSC_XOBP_SHIFT 1#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
arch/arm/include/asm/arch-tegra/usb.h deleted +0 -249
249 lines not on this page · raw message
arch/arm/include/asm/arch-tegra114/tegra.h +1 -0
@@ -30,5 +30,6 @@#define NVBOOTINFOTABLE_BCTPTR 0x4C/* BCT pointer in BIT in IRAM */ #define MAX_NUM_CPU 4 +#define TEGRA_USB1_BASE 0x7D000000#endif /* TEGRA114_H */
arch/arm/include/asm/arch-tegra114/usb.h new file +287 -0
287 lines not on this page · raw message
arch/arm/include/asm/arch-tegra20/usb.h new file +279 -0
279 lines not on this page · raw message
arch/arm/include/asm/arch-tegra30/usb.h new file +294 -0
294 lines not on this page · raw message
board/nvidia/common/board.c +1 -1
@@ -46,7 +46,7 @@#include <asm/arch/emc.h> #endif #ifdef CONFIG_USB_EHCI_TEGRA -#include <asm/arch-tegra/usb.h> +#include <asm/arch/usb.h> #endif #ifdef CONFIG_TEGRA_MMC #include <asm/arch-tegra/tegra_mmc.h>
drivers/usb/host/ehci-hcd.c +28 -12
@@ -122,6 +122,31 @@ static struct descriptor {#define ehci_is_TDI () (0)#endif +int __ehci_get_port_speed (struct ehci_hcor *hcor,uint32_t reg) +{ +return PORTSC_PSPD (reg); +} + +int ehci_get_port_speed (struct ehci_hcor *hcor,uint32_t reg) + __attribute__((weak,alias ("__ehci_get_port_speed" ))); + +void __ehci_set_usbmode (int index) +{ +uint32_t tmp; +uint32_t *reg_ptr; + + reg_ptr = (uint32_t *)((u8 *)&ehcic[index].hcor->or_usbcmd +USBMODE ); + tmp =ehci_readl (reg_ptr); + tmp |=USBMODE_CM_HC ; +#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN ) + tmp |=USBMODE_BE ; +#endif +ehci_writel (reg_ptr, tmp); +} + +void ehci_set_usbmode (int index) + __attribute__((weak,alias ("__ehci_set_usbmode" ))); +void __ehci_powerup_fixup (uint32_t *status_reg,uint32_t *reg) {mdelay (50 );
@@ -149,8 +174,6 @@ static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)static int ehci_reset (int index) {uint32_t cmd; -uint32_t tmp; -uint32_t *reg_ptr;int ret =0 ; cmd =ehci_readl (&ehcic[index].hcor->or_usbcmd);
@@ -163,15 +186,8 @@ static int ehci_reset(int index) goto out; } -if (ehci_is_TDI ()) { - reg_ptr = (uint32_t *)((u8 *)ehcic[index].hcor +USBMODE ); - tmp =ehci_readl (reg_ptr); - tmp |=USBMODE_CM_HC ; -#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN ) - tmp |=USBMODE_BE ; -#endif -ehci_writel (reg_ptr, tmp); - } +if (ehci_is_TDI ()) +ehci_set_usbmode (index);#ifdef CONFIG_USB_EHCI_TXFIFO_THRESH cmd =ehci_readl (&ehcic[index].hcor->or_txfilltuning);
@@ -711,7 +727,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, tmpbuf[1 ] |=USB_PORT_STAT_POWER >>8 ;if (ehci_is_TDI ()) { -switch (PORTSC_PSPD (reg)) { +switch (ehci_get_port_speed (ctrl->hcor, reg)) {case PORTSC_PSPD_FS :break ;case PORTSC_PSPD_LS :
drivers/usb/host/ehci-tegra.c +278 -98
543 lines not on this page · raw message
Signature · 1 line
1.7.7
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Dear Jim Lin,
Quoted 8 lines
Tegra30 and Tegra114 are compatible except
1. T30 takes 55 ms to finish Port Reset. T114 takes 50 ms.
2. PLL parametersTested on Tegra20 Harmony/Seaboard, Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well.
Quoted 8 lines
Signed-off-by Jim Lin <[email protected]>--- arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249 ------------------ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra114/usb.h | 287 +++++++++++++++++++++ arch/arm/include/asm/arch-tegra20/usb.h | 279 +++++++++++++++++++++ arch/arm/include/asm/arch-tegra30/usb.h | 294 ++++++++++++++++++++++
Do we now have three copies of the same stuff ?
[...]
Best regards,
Marek Vasut
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Marek,
Quoted 24 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Monday, April 29, 2013 4:47 PM
To: Jim Lin
Cc: u-boot at lists.denx.de; Tom Warren; Stephen Warren
Subject: Re: [PATCH 2/3] ARM: Tegra: USB: Add driver support for Tegra30/Tegra114Dear Jim Lin,
Quoted 8 lines
Tegra30 and Tegra114 are compatible except 1. T30 takes 55 ms to finish Port Reset. T114 takes
50 ms.
2. PLL parametersTested on Tegra20 Harmony/Seaboard, Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well.
Quoted 6 lines
Signed-off-by Jim Lin <[email protected]>--- arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249 ------------------ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra114/usb.h | 287
Quoted 7 lines
+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra20/usb.h | 279+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra30/usb.h | 294++++++++++++++++++++++
Do we now have three copies of the same stuff ?
When only T20 was supported (for USB), there was a common (arch-tegra/usb.h) header. That's been moved to arch-tegra20/usb.h, and (unfortunately) there are 2 new usb.h files due to the HW differences in the registers between T20 and T30/T114. I don't see any easy way to have a common usb.h file for Tegra w/o adding ugly #ifdefs to the USB register space struct(s).
Tom
Quoted 4 lines
[...]
Best regards,
Marek Vasut
--
nvpublic
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Dear Tom Warren,
Quoted 40 lines
Marek,
Quoted 38 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Monday, April 29, 2013 4:47 PM
To: Jim Lin
Cc: u-boot at lists.denx.de; Tom Warren; Stephen Warren
Subject: Re: [PATCH 2/3] ARM: Tegra: USB: Add driver support for Tegra30/Tegra114Dear Jim Lin,
Quoted 10 lines
Tegra30 and Tegra114 are compatible except 1. T30 takes 55 ms to finish Port Reset. T114 takes
50 ms.2. PLL parameters
Tested on Tegra20 Harmony/Seaboard, Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well.
Quoted 7 lines
Signed-off-by Jim Lin <[email protected]>---
arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249 ------------------ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra114/usb.h | 287+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra20/usb.h | 279+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra30/usb.h | 294++++++++++++++++++++++
Quoted 8 lines
Quoted 1 line
Do we now have three copies of the same stuff ?
When only T20 was supported (for USB), there was a common (
arch-tegra/usb.h) header. That's been moved toarch-tegra20/usb.h, and (unfortunately) there are 2 newusb.hfiles due to the HW differences in the registers between T20 and T30/T114. I don't see any easy way to have a commonusb.hfile for Tegra w/o adding ugly #ifdefs to the USB register space struct(s).
Thanks for clearing that up.
Best regards,
Marek Vasut
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
In reply to Tom WarrenQuoted 32 lines · Tom Warren
Marek,
Quoted 30 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Monday, April 29, 2013 4:47 PM
To: Jim Lin
Cc: u-boot at lists.denx.de; Tom Warren; Stephen Warren
Subject: Re: [PATCH 2/3] ARM: Tegra: USB: Add driver support for Tegra30/Tegra114Dear Jim Lin,
Quoted 8 lines
Tegra30 and Tegra114 are compatible except 1. T30 takes 55 ms to finish Port Reset. T114 takes
50 ms.
2. PLL parametersTested on Tegra20 Harmony/Seaboard, Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well.
Quoted 6 lines
Signed-off-by Jim Lin <[email protected]>--- arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249 ------------------ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra114/usb.h | 287+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra20/usb.h | 279+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra30/usb.h | 294++++++++++++++++++++++
Quoted 8 lines
Quoted 1 line
Do we now have three copies of the same stuff ?
When only T20 was supported (for USB), there was a common (
arch-tegra/usb.h) header. That's been moved toarch-tegra20/usb.h, and (unfortunately) there are 2 newusb.hfiles due to the HW differences in the registers between T20 and T30/T114. I don't see any easy way to have a commonusb.hfile for Tegra w/o adding ugly #ifdefs to the USB register space struct(s).
Just how different are they? Are all of the related defines and masks different too? Do we have conflicts? Moved registers? Just conflicting values? A quick peek shows '30' and '114' are pretty similar, except for masks. Maybe splitting the struct up so you can discard some of the reserved gaps, run-time checking to see if we can or cannot use a particular part of the struct?
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20130430/90bd70dd/attachment.pgp>
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Tom,
Quoted 43 lines · Tom Rini
Quoted 32 lines · Tom Warren
Marek,
Quoted 30 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Monday, April 29, 2013 4:47 PM
To: Jim Lin
Cc: u-boot at lists.denx.de; Tom Warren; Stephen Warren
Subject: Re: [PATCH 2/3] ARM: Tegra: USB: Add driver support for Tegra30/Tegra114Dear Jim Lin,
Quoted 8 lines
Tegra30 and Tegra114 are compatible except 1. T30 takes 55 ms to finish Port Reset. T114 takes
50 ms.
2. PLL parametersTested on Tegra20 Harmony/Seaboard, Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well.
Quoted 6 lines
Signed-off-by Jim Lin <[email protected]>--- arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249 ------------------ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra114/usb.h | 287+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra20/usb.h | 279+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra30/usb.h | 294++++++++++++++++++++++
Quoted 8 lines
Quoted 1 line
Do we now have three copies of the same stuff ?
When only T20 was supported (for USB), there was a common (
arch-tegra/usb.h) header. That's been moved toarch-tegra20/usb.h, and (unfortunately) there are 2 newusb.hfiles due to the HW differences in the registers between T20 and T30/T114. I don't see any easy way to have a commonusb.hfile for Tegra w/o adding ugly #ifdefs to the USB register space struct(s).
Quoted 7 lines
Just how different are they? Are all of the related defines and masks different too? Do we have conflicts? Moved registers? Just conflicting values? A quick peek shows '30' and '114' are pretty similar, except for masks. Maybe splitting the struct up so you can discard some of the reserved gaps, run-time checking to see if we can or cannot use a particular part of the struct?
This is really Jim's patchset (and his specialty), but here's what I know about Tegra USB regs:
T20 had a gap in the registers @ offset 0x130. T30 (and T114) moved the offset of the command/status/interrupt regs down to fill in this gap, which dragged all the subsequent registers back 16 bytes. The two SoCs 'families' sync up again at offset 0x400 and are pretty much equal from there on out to 0x840.
The defines are probably 90% the same, with some weirdness for the first USB controller (USB1) and its PTS/STS bits that differs in offset from the other 2 controllers (again, no clue why the HW guys would do this).
So we could have the 3 different USB headers in the arch-tegraXX area contain the register structs, and have a common arch-tegra/usb.h that has the #defines that are the same, and is included in the arch-tegraxx/usb.h files. That would reduce this down somewhat, without the ugliness of #ifdefs in the structs.
What do you think?
Tom
Quoted 4 lines
--
Tom
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Quoted 69 lines · Tom Warren
Tom,
Quoted 43 lines · Tom Rini
Quoted 32 lines · Tom Warren
Marek,
Quoted 30 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Monday, April 29, 2013 4:47 PM
To: Jim Lin
Cc: u-boot at lists.denx.de; Tom Warren; Stephen Warren
Subject: Re: [PATCH 2/3] ARM: Tegra: USB: Add driver support for Tegra30/Tegra114Dear Jim Lin,
Quoted 8 lines
Tegra30 and Tegra114 are compatible except 1. T30 takes 55 ms to finish Port Reset. T114 takes
50 ms.
2. PLL parametersTested on Tegra20 Harmony/Seaboard, Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well.
Quoted 6 lines
Signed-off-by Jim Lin <[email protected]>--- arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249 ------------------ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra114/usb.h | 287+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra20/usb.h | 279+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra30/usb.h | 294++++++++++++++++++++++
Quoted 8 lines
Quoted 1 line
Do we now have three copies of the same stuff ?
When only T20 was supported (for USB), there was a common (
arch-tegra/usb.h) header. That's been moved toarch-tegra20/usb.h, and (unfortunately) there are 2 newusb.hfiles due to the HW differences in the registers between T20 and T30/T114. I don't see any easy way to have a commonusb.hfile for Tegra w/o adding ugly #ifdefs to the USB register space struct(s).Quoted 7 lines
Just how different are they? Are all of the related defines and masks different too? Do we have conflicts? Moved registers? Just conflicting values? A quick peek shows '30' and '114' are pretty similar, except for masks. Maybe splitting the struct up so you can discard some of the reserved gaps, run-time checking to see if we can or cannot use a particular part of the struct?
This is really Jim's patchset (and his specialty), but here's what I know about Tegra USB regs:
T20 had a gap in the registers @ offset
0x130. T30 (and T114) moved the offset of the command/status/interrupt regs down to fill in this gap, which dragged all the subsequent registers back 16 bytes. The two SoCs 'families' sync up again at offset0x400and are pretty much equal from there on out to0x840.The defines are probably 90% the same, with some weirdness for the first USB controller (USB1) and its PTS/STS bits that differs in offset from the other 2 controllers (again, no clue why the HW guys would do this).
Quoted 7 lines
So we could have the 3 different USB headers in the arch-tegraXX area contain the register structs, and have a common
arch-tegra/usb.hthat has the #defines that are the same, and is included in thearch-tegraxx/usb.hfiles. That would reduce this down somewhat, without the ugliness of #ifdefs in the structs.What do you think?
Sounds like the best we can do then. It's probable that trying to define USB_REGMAP_GAPSIZE1/2 or whatever to do it on the fly would just be uglier still. Thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 836 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20130501/49a86e52/attachment.pgp>
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Dear Tom Rini,
Quoted 81 lines · Tom Warren
Quoted 80 lines
Tom,
Quoted 51 lines · Tom Rini
Quoted 41 lines · Tom Warren
Marek,
Quoted 39 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Monday, April 29, 2013 4:47 PM
To: Jim Lin
Cc: u-boot at lists.denx.de; Tom Warren; Stephen Warren
Subject: Re: [PATCH 2/3] ARM: Tegra: USB: Add driver support for Tegra30/Tegra114Dear Jim Lin,
Quoted 10 lines
Tegra30 and Tegra114 are compatible except 1. T30 takes 55 ms to finish Port Reset. T114 takes
50 ms.2. PLL parameters
Tested on Tegra20 Harmony/Seaboard, Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well.
Quoted 8 lines
Signed-off-by Jim Lin <[email protected]>---
arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249 ------------------ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra114/usb.h | 287+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra20/usb.h | 279+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra30/usb.h | 294++++++++++++++++++++++
Quoted 8 lines
Quoted 1 line
Do we now have three copies of the same stuff ?
When only T20 was supported (for USB), there was a common (
arch-tegra/usb.h) header. That's been moved toarch-tegra20/usb.h, and (unfortunately) there are 2 newusb.hfiles due to the HW differences in the registers between T20 and T30/T114. I don't see any easy way to have a commonusb.hfile for Tegra w/o adding ugly #ifdefs to the USB register space struct(s).Quoted 6 lines
Just how different are they? Are all of the related defines and masks different too? Do we have conflicts? Moved registers? Just conflicting values? A quick peek shows '30' and '114' are pretty similar, except for masks. Maybe splitting the struct up so you can discard some of the reserved gaps, run-time checking to see if we can or cannot use a particular part of the struct?
This is really Jim's patchset (and his specialty), but here's what I know about Tegra USB regs:
T20 had a gap in the registers @ offset
0x130. T30 (and T114) moved the offset of the command/status/interrupt regs down to fill in this gap, which dragged all the subsequent registers back 16 bytes. The two SoCs 'families' sync up again at offset0x400and are pretty much equal from there on out to0x840.The defines are probably 90% the same, with some weirdness for the first USB controller (USB1) and its PTS/STS bits that differs in offset from the other 2 controllers (again, no clue why the HW guys would do this).
So we could have the 3 different USB headers in the arch-tegraXX area contain the register structs, and have a common
arch-tegra/usb.hthat has the #defines that are the same, and is included in thearch-tegraxx/usb.hfiles. That would reduce this down somewhat, without the ugliness of #ifdefs in the structs.
Quoted 5 lines
Quoted 1 line
What do you think?
Sounds like the best we can do then. It's probable that trying to define USB_REGMAP_GAPSIZE1/2 or whatever to do it on the fly would just be uglier still. Thanks!
This is a problem with the struct-based access indeed. I agree with Tom it'd be worth to at least try distilling the common part into header shared between those three CPUs.
btw you're also adding some kernel-doc-alike annotations to functions, why don't you follow kerneldoc style altogether?
Best regards,
Marek Vasut
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Quoted 97 lines · Marek Vasut
Dear Tom Rini,
Quoted 15 lines · Tom Warren
Quoted 14 lines
Tom,
Quoted 11 lines · Tom Rini
Quoted 10 lines · Tom Warren
Marek,
Quoted 8 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Monday, April 29, 2013 4:47 PM
To: Jim Lin
Cc: u-boot at lists.denx.de; Tom Warren; Stephen Warren
Subject: Re: [PATCH 2/3] ARM: Tegra: USB: Add driver support for Tegra30/Tegra114Quoted 3 lines
Quoted 3 lines
Quoted 3 lines
Quoted 3 lines
Quoted 3 lines
Dear Jim Lin,
Quoted 1 line
Tegra30 and Tegra114 are compatible except 1. T30 takes 55 ms
to
Quoted 7 lines
Quoted 7 lines
Quoted 7 lines
Quoted 7 lines
Quoted 7 lines
Quoted 7 lines
finish Port Reset. T114 takes
50 ms.2. PLL parameters
Tested on Tegra20 Harmony/Seaboard, Tegra30 Cardhu, and
Tegra114
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Dalmore platforms. All works well.
Signed-off-by Jim Lin <[email protected]>---
arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249------------------
arch/arm/include/asm/arch-tegra114/tegra.h|
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
Quoted 14 lines
Quoted 2 lines
1 + arch/arm/include/asm/arch-tegra114/usb.h | 287+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra20/usb.h | 279+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra30/usb.h | 294++++++++++++++++++++++
Do we now have three copies of the same stuff ?
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 6 lines
When only T20 was supported (for USB), there was a common (
arch-tegra/usb.h) header. That's been moved toarch-tegra20/usb.h, and (unfortunately) there are 2 newusb.hfiles due to the HW differences in the registers between T20 and T30/T114. I don't see any easy way to have a commonusb.hfile for Tegra w/o adding ugly #ifdefs to the USB register space struct(s).Just how different are they? Are all of the related defines and
masks
Quoted 7 lines
Quoted 7 lines
Quoted 5 lines
different too? Do we have conflicts? Moved registers? Just conflicting values? A quick peek shows '30' and '114' are pretty similar, except for masks. Maybe splitting the struct up so you can discard some of the reserved gaps, run-time checking to see if we can or cannot use a particular part of the struct?
This is really Jim's patchset (and his specialty), but here's what I
know
Quoted 9 lines
Quoted 9 lines
about Tegra USB regs:
T20 had a gap in the registers @ offset
0x130. T30 (and T114) moved the offset of the command/status/interrupt regs down to fill in this gap, which dragged all the subsequent registers back 16 bytes. The two SoCs 'families' sync up again at offset0x400and are pretty much equal from there on out to0x840.The defines are probably 90% the same, with some weirdness for the
first
Quoted 5 lines
Quoted 5 lines
USB controller (USB1) and its PTS/STS bits that differs in offset from the other 2 controllers (again, no clue why the HW guys would do this).
So we could have the 3 different USB headers in the arch-tegraXX area contain the register structs, and have a common
arch-tegra/usb.hthathas
Quoted 1 line
Quoted 1 line
the #defines that are the same, and is included in the
arch-tegraxx/usb.hQuoted 8 lines
Quoted 4 lines
files. That would reduce this down somewhat, without the ugliness of #ifdefs in the structs.
What do you think?
Sounds like the best we can do then. It's probable that trying to define USB_REGMAP_GAPSIZE1/2 or whatever to do it on the fly would just be uglier still. Thanks!
Quoted 9 lines
This is a problem with the struct-based access indeed. I agree with Tom it'd be
worth to at least try distilling the common part into header shared between those three CPUs.btw you're also adding some kernel-doc-alike annotations to functions, why don't
you follow kerneldoc style altogether?
I'll let Jim answer that.
Quoted 4 lines
Best regards,
Marek Vasut
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Adding Jim back into the conversation since he got dropped a couple of emails back.
Quoted 128 lines · Tom Warren
Quoted 109 lines · Marek Vasut
Dear Tom Rini,
Quoted 15 lines · Tom Warren
Quoted 14 lines
Tom,
Quoted 11 lines · Tom Rini
Quoted 10 lines · Tom Warren
Marek,
Quoted 8 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Monday, April 29, 2013 4:47 PM
To: Jim Lin
Cc: u-boot at lists.denx.de; Tom Warren; Stephen Warren
Subject: Re: [PATCH 2/3] ARM: Tegra: USB: Add driver support for Tegra30/Tegra114Quoted 3 lines
Quoted 3 lines
Quoted 3 lines
Quoted 3 lines
Quoted 3 lines
Dear Jim Lin,
Quoted 1 line
Tegra30 and Tegra114 are compatible except 1. T30 takes 55 ms
to
Quoted 7 lines
Quoted 7 lines
Quoted 7 lines
Quoted 7 lines
Quoted 7 lines
Quoted 7 lines
finish Port Reset. T114 takes
50 ms.2. PLL parameters
Tested on Tegra20 Harmony/Seaboard, Tegra30 Cardhu, and
Tegra114
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Dalmore platforms. All works well.
Signed-off-by Jim Lin <[email protected]>---
arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249------------------
arch/arm/include/asm/arch-tegra114/tegra.h|Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
Quoted 2 lines
1 + arch/arm/include/asm/arch-tegra114/usb.h | 287+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra20/usb.h | 279+++++++++++++++++++++
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
Quoted 5 lines
Quoted 1 line
arch/arm/include/asm/arch-tegra30/usb.h | 294++++++++++++++++++++++
Do we now have three copies of the same stuff ?
When only T20 was supported (for USB), there was a common (
arch-tegra/usb.h) header. That's been moved to
arch-tegra20/usb.h,Quoted 2 lines
Quoted 2 lines
Quoted 2 lines
Quoted 2 lines
and (unfortunately) there are 2 new
usb.hfiles due to the HW differences in the registers between T20 and T30/T114. I don'tsee
Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
Quoted 2 lines
any easy way to have a common
usb.hfile for Tegra w/o adding ugly #ifdefs to the USB register space struct(s).Just how different are they? Are all of the related defines and
masks
Quoted 4 lines
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different too? Do we have conflicts? Moved registers? Just conflicting values? A quick peek shows '30' and '114' are pretty similar, except for masks. Maybe splitting the struct up so you can discard some of the reserved gaps, run-time checking to see if we
can
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or cannot use a particular part of the struct?
This is really Jim's patchset (and his specialty), but here's what I
know
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about Tegra USB regs:
T20 had a gap in the registers @ offset
0x130. T30 (and T114) movedthe
Quoted 3 lines
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offset of the command/status/interrupt regs down to fill in this gap, which dragged all the subsequent registers back 16 bytes. The two SoCs 'families' sync up again at offset
0x400and are pretty much equalfrom
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there on out to
0x840.The defines are probably 90% the same, with some weirdness for the
first
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USB controller (USB1) and its PTS/STS bits that differs in offset from the other 2 controllers (again, no clue why the HW guys would do
this).
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So we could have the 3 different USB headers in the arch-tegraXX area contain the register structs, and have a common
arch-tegra/usb.hthathas
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the #defines that are the same, and is included in the
arch-tegraxx/usb.hQuoted 8 lines
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files. That would reduce this down somewhat, without the ugliness of #ifdefs in the structs.
What do you think?
Sounds like the best we can do then. It's probable that trying to define USB_REGMAP_GAPSIZE1/2 or whatever to do it on the fly would just be uglier still. Thanks!
This is a problem with the struct-based access indeed. I agree with Tom it'd be
worth to at least try distilling the common part into header shared between
those three CPUs.Quoted 4 lines
btw you're also adding some kernel-doc-alike annotations to functions, why don't
you follow kerneldoc style altogether?I'll let Jim answer that.
Quoted 4 lines
Best regards,
Marek Vasut
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
In reply to Marek VasutQuoted 85 lines · Marek Vasut
Dear Tom Rini,
Quoted 83 lines · Tom Warren
Quoted 81 lines
Tom,
Quoted 51 lines · Tom Rini
Quoted 41 lines · Tom Warren
Marek,
Quoted 39 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Monday, April 29, 2013 4:47 PM
To: Jim Lin
Cc: u-boot at lists.denx.de; Tom Warren; Stephen Warren
Subject: Re: [PATCH 2/3] ARM: Tegra: USB: Add driver support for Tegra30/Tegra114Dear Jim Lin,
Quoted 10 lines
Tegra30 and Tegra114 are compatible except 1. T30 takes 55 ms to finish Port Reset. T114 takes
50 ms.2. PLL parameters
Tested on Tegra20 Harmony/Seaboard, Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well.
Quoted 8 lines
Signed-off-by Jim Lin <[email protected]>---
arch/arm/include/asm/arch-tegra/clk_rst.h | 10 + arch/arm/include/asm/arch-tegra/usb.h | 249 ------------------ arch/arm/include/asm/arch-tegra114/tegra.h | 1 + arch/arm/include/asm/arch-tegra114/usb.h | 287+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra20/usb.h | 279+++++++++++++++++++++
Quoted 1 line
arch/arm/include/asm/arch-tegra30/usb.h | 294++++++++++++++++++++++
Quoted 8 lines
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Do we now have three copies of the same stuff ?
When only T20 was supported (for USB), there was a common (
arch-tegra/usb.h) header. That's been moved toarch-tegra20/usb.h, and (unfortunately) there are 2 newusb.hfiles due to the HW differences in the registers between T20 and T30/T114. I don't see any easy way to have a commonusb.hfile for Tegra w/o adding ugly #ifdefs to the USB register space struct(s).Quoted 6 lines
Just how different are they? Are all of the related defines and masks different too? Do we have conflicts? Moved registers? Just conflicting values? A quick peek shows '30' and '114' are pretty similar, except for masks. Maybe splitting the struct up so you can discard some of the reserved gaps, run-time checking to see if we can or cannot use a particular part of the struct?
This is really Jim's patchset (and his specialty), but here's what I know about Tegra USB regs:
T20 had a gap in the registers @ offset
0x130. T30 (and T114) moved the offset of the command/status/interrupt regs down to fill in this gap, which dragged all the subsequent registers back 16 bytes. The two SoCs 'families' sync up again at offset0x400and are pretty much equal from there on out to0x840.The defines are probably 90% the same, with some weirdness for the first USB controller (USB1) and its PTS/STS bits that differs in offset from the other 2 controllers (again, no clue why the HW guys would do this).
So we could have the 3 different USB headers in the arch-tegraXX area contain the register structs, and have a common
arch-tegra/usb.hthat has the #defines that are the same, and is included in thearch-tegraxx/usb.hfiles. That would reduce this down somewhat, without the ugliness of #ifdefs in the structs.What do you think?
Quoted 7 lines
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Sounds like the best we can do then. It's probable that trying to define USB_REGMAP_GAPSIZE1/2 or whatever to do it on the fly would just be uglier still. Thanks!
This is a problem with the struct-based access indeed. I agree with Tom it'd be worth to at least try distilling the common part into header shared between those three CPUs.
OK. I will add this into next version of patch.
Quoted 3 lines
btw you're also adding some kernel-doc-alike annotations to functions, why don't you follow kerneldoc style altogether?
I don't understand what you meant here.
Could you give me an example? Like what I did is wrong or not good. And what is correct or better one.
Thanks.
--
nvpublic
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Dear Jim Lin,
[...]
Quoted 5 lines
Quoted 4 lines
This is a problem with the struct-based access indeed. I agree with Tom it'd be worth to at least try distilling the common part into header shared between those three CPUs.
Quoted 8 lines
OK. I will add this into next version of patch.
Quoted 2 lines
btw you're also adding some kernel-doc-alike annotations to functions, why don't you follow kerneldoc style altogether?
I don't understand what you meant here.
Could you give me an example? Like what I did is wrong or not good. And what is correct or better one.
These kinds of annotations:
+/*
+ * Process a list of nodes, adding them to our list of SDMMC ports.
+ *
+ * @param blob fdt blob + * @param node_list list of nodes to process (any <=0 are ignored) + * @param count number of nodes to process
+ * @return 0 if ok, -1 on error
+ */
See http://www.denx.de/wiki/U-Boot/CodingStyle@the bottom for the right style.
Best regards,
Marek Vasut
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Jim,
Quoted 9 lines
-----Original Message-----
From: Marek Vasut [mailto:marex at denx.de]
Sent: Thursday, May 02, 2013 4:39 AM
To: Jim Lin
Cc: Tom Rini; u-boot at lists.denx.de; Tom Warren; Stephen Warren; Tom Warren
Subject: Re: [U-Boot] [PATCH 2/3] ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Quoted 10 lines
Dear Jim Lin,
[...]
Quoted 6 lines
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This is a problem with the struct-based access indeed. I agree with Tom it'd be worth to at least try distilling the common part into header shared between those three CPUs.
OK. I will add this into next version of patch.
I did a quick hack for arch-tegra/usb.h (common defines) and arch-tegra114/usb.h (register struct plus some unique defines) that I'll send you as an example.
Quoted 13 lines
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btw you're also adding some kernel-doc-alike annotations to functions, why don't you follow kerneldoc style altogether?
I don't understand what you meant here.
Could you give me an example? Like what I did is wrong or not good. And what is correct or better one.These kinds of annotations:
+/*
+ * Process a list of nodes, adding them to our list of SDMMC ports.
+ *
Quoted 8 lines
+ * @param blob fdt blob + * @param node_list list of nodes to process (any <=0 are ignored) + * @param count number of nodes to process+ * @return 0 if ok, -1 on error
+ */See http://www.denx.de/wiki/U-Boot/CodingStyle at the bottom for the right style.
Note that the 'SDMMC ports' part s/b 'USB ports', or 'USB controllers'. Please change it.
Marek is asking why we have inconsistent function commenting in ehci-tegra.c - read the kernel.doc howto pointed to in the URL above, and make sure any function/struct/enum comments adhere to that style (/** to start, Return: instead of @return, etc.), so that one can run the kernel-doc scripts and extract info about our EHCI driver's functions, etc. This is something I'll look at doing in all the Tegra-specific drivers and source in a future patchset.
Tom
Quoted 3 lines
Best regards,
Marek Vasut
--
nvpublic
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
In reply to Jim LinQuoted 3 lines · Jim Lin
Tegra30 and Tegra114 are compatible except
1. T30 takes 55 ms to finish Port Reset. T114 takes 50 ms.
Is that 55-vs-50 some aspect of the HW specification itself, or the overall result of multiple separate delays? I ask because the statement that one piece of HW differs from another only in a delay, especially where that delay is enormous in HW terms, seem very unusual.
arch/arm/include/asm/arch-tegra114/tegra.h line 33
Quoted 3 lines
arch/arm/include/asm/arch-tegra114/tegra.h +1
-0+#define TEGRA_USB1_BASE 0x7D000000
That shouldn't be needed; if some of the module base addresses come from DT, then they all should, or there's no point using DT.
arch/arm/include/asm/arch-tegra114/usb.h line 27
Quoted 7 lines
arch/arm/include/asm/arch-tegra114/usb.h +5
-0+#ifndef _TEGRA_USB_H_ +#define _TEGRA_USB_H_ + + +/* USB Controller (USBx_CONTROLLER_) regs */
There's an extra blank line there. The same problem exists elsewhere, and in the other copies of this file.
drivers/usb/host/ehci-tegra.c static const u8 utmip_hs_sync_start_delay = 9; · line 117
Quoted 8 lines
drivers/usb/host/ehci-tegra.c +2
-2void ehci_powerup_fixup (uint32_t *status_reg,uint32_t *reg) { -mdelay (50 ); -if (((u32 ) status_reg &TEGRA_USB_ADDR_MASK ) !=TEGRA_USB1_BASE ) +udelay (49990 ); +if (is_T30_compatible) {
The code shouldn't test against a specific chip version, but rather against some property of the HW (like the length of the delay). That way, it will be scalable when we support 10 different Tegra versions and the mapping from version number to feature isn't easy to represent.
drivers/usb/host/ehci-tegra.c static const u8 utmip_hs_sync_start_delay = 9; · line 128
Quoted 11 lines
drivers/usb/host/ehci-tegra.c +11
-0+/* +* Tegra 114 takes 50 ms to assert Port Enable bit. +* We have to exit earlier. Otherwise ehci-hcd.c will clear +* our Port Enable bit. +*/ +if (is_T114_compatible) +return ; +/* Tegra 3 takes about 55 ms to assert Port Enable bit. */ +udelay (5010 ); +return ; + }
This looks like an enormous hack. What is it doing? Why? Can't all 3 chips simply loop polling until some enable status bit is set?
drivers/usb/host/ehci-tegra.c static const u8 utmip_hs_sync_start_delay = 9; · line 131
Quoted 3 lines
drivers/usb/host/ehci-tegra.c +2
-0+udelay (10 ); +if (((u32 )status_reg &TEGRA_USB_ADDR_MASK ) !=TEGRA_USB1_BASE )return ;
This also should test against a feature, not the identity of the port. The DT properties nvidia,has-legacy-mode or nvidia,needs-double-reset might be relevant here?
drivers/usb/host/ehci-tegra.c static void set_host_mode(struct fdt_usb *config) · line 180
Quoted 6 lines
drivers/usb/host/ehci-tegra.c +1
-1@@ -171,7 +177,7 @@ static void set_host_mode(struct fdt_usb *config)* bail out in this case. */ if (config->dr_mode ==DR_MODE_OTG && - (readl (&config->reg->phy_vbus_sensors) &VBUS_VLD_STS )) + (readl (&config->reg->phy_vbus_sensors) &VBUS_VLD_STS ))
That's an unrelated whitespace change. Whitespace cleanup should be in a separate patch first, so it doesn't clutter functional changes.
Quoted 4 lines
drivers/usb/host/ehci-tegra.c +0
-0@@ -232,45 +240,112 @@ static int init_utmi_usb_controller(struct fdt_usb *config)* To Use the A Session Valid for cable detection logic, VBUS_WAKEUP * mux must be switched to actually use a_sess_vld threshold. */
drivers/usb/host/ehci-tegra.c static int init_utmi_usb_controller(struct fdt_usb *config) · line 248
Quoted 10 lines
drivers/usb/host/ehci-tegra.c +5
-4-if (fdt_gpio_isvalid (&config->vbus_gpio)) { +if (config->dr_mode ==DR_MODE_OTG && +fdt_gpio_isvalid (&config->vbus_gpio))clrsetbits_le32 (&usbctlr->usb1_legacy_ctrl, -VBUS_SENSE_CTL_MASK , -VBUS_SENSE_CTL_A_SESS_VLD <<VBUS_SENSE_CTL_SHIFT ); - } +VBUS_SENSE_CTL_MASK , +VBUS_SENSE_CTL_A_SESS_VLD << +VBUS_SENSE_CTL_SHIFT );
Partially a white-space change. There are many other ws-changes later that I didn't bother pointing out.
Quoted 3 lines
drivers/usb/host/ehci-tegra.c +3
-0+ timing = (u32 *)config->params; +if (is_T30_compatible) + goto pll_T30_init;
...
Quoted 3 lines
drivers/usb/host/ehci-tegra.c +3
-0+ goto pll_init_done; + +pll_T30_init:
...
Quoted 1 line
+pll_init_done:
Uggh. Use functions.
Quoted 10 lines
drivers/usb/host/ehci-tegra.c +2
-4@@ -325,17 +409,37 @@ static int init_utmi_usb_controller(struct fdt_usb *config)/* Disable ICUSB FS/LS transceiver */ clrbits_le32 (&usbctlr->icusb_ctrl,IC_ENB1 ); -/* Select UTMI parallel interface */ -clrsetbits_le32 (&usbctlr->port_sc1,PTS_MASK , -PTS_UTMI <<PTS_SHIFT ); -clrbits_le32 (&usbctlr->port_sc1,STS ); +if (!is_T30_compatible) { +/* Select UTMI parallel interface */
drivers/usb/host/ehci-tegra.c static int init_utmi_usb_controller(struct fdt_usb *config) · line 423
Quoted 10 lines
drivers/usb/host/ehci-tegra.c +10
-0+if (config->periph_id ==PERIPH_ID_USBD ) { +clrsetbits_le32 (&usbctlr->port_sc1,PTS1_MASK , +PTS_UTMI <<PTS1_SHIFT ); +clrbits_le32 (&usbctlr->port_sc1,STS1 ); + }else { +clrsetbits_le32 (&usbctlr->port_sc1,PTS_MASK , +PTS_UTMI <<PTS_SHIFT ); +clrbits_le32 (&usbctlr->port_sc1,STS ); + } + }
This changes behaviour on Tegra20. While it may be correct, it has nothing to do with adding Tegra30/114 support, and hence should be a separate patch earlier in the series.
drivers/usb/host/ehci-tegra.c int board_usb_init(const void *blob) · line 667
Quoted 11 lines
drivers/usb/host/ehci-tegra.c +10
-0+int board_usb_init (const void *blob) + if (!count) + goto skip_T20_process; + err = process_nodes(blob, node_list, count); +if (err) { +printf ("%s: Error processing T20 compatible USB node(s)!\n" , + __func__); +return err; + } +skip_T20_process:
Uggh. Instead of:
if (!count)
goto skip;
code;skip:
do:
if (count) {
code;
}drivers/usb/host/ehci-tegra.c int board_usb_init(const void *blob) · line 672
Quoted 5 lines
drivers/usb/host/ehci-tegra.c +5
-0+ + count =fdtdec_find_aliases_for_id (blob,"usb" , +COMPAT_NVIDIA_TEGRA114_USB , node_list,USB_PORTS_MAX ); +if (count) + is_T114_compatible =1 ;
Don't use globals for that. Or, if you do, just return as soon as you've found a match, so it's impossible to end up with some Tegra20 and some Tegra30 controllers both enabled.
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Quoted 9 lines · Stephen Warren
Quoted 3 lines · Jim Lin
Tegra30 and Tegra114 are compatible except
1. T30 takes 55 ms to finish Port Reset. T114 takes 50 ms.Is that 55-vs-50 some aspect of the HW specification itself, or the overall result of multiple separate delays? I ask because the statement that one piece of HW differs from another only in a delay, especially where that delay is enormous in HW terms, seem very unusual.
50 ms comes from USB 2.0 specification for root port. 55 ms comes from T30 Technical Reference Manual. Overall result of multiple separate delays.
--
nvpublic
PATCH 2/3 ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Quoted 6 lines · Jim Lin
Quoted 5 lines · Stephen Warren
Quoted 3 lines · Jim Lin
Tegra30 and Tegra114 are compatible except
1. T30 takes 55 ms to finish Port Reset. T114 takes 50 ms.
Quoted 7 lines
Quoted 4 lines
Is that 55-vs-50 some aspect of the HW specification itself, or the overall result of multiple separate delays? I ask because the statement that one piece of HW differs from another only in a delay, especially where that delay is enormous in HW terms, seem very unusual.
50 ms comes from USB 2.0 specification for root port. 55 ms comes from T30 Technical Reference Manual.
OK, I see this value is indeed in the TRM, so I guess the code is OK.
Quoted 1 line
Overall result of multiple separate delays.
That doesn't seem true though; the TRM simply documents a single 55ms delay, not a set of delays that add up to 55ms.
PATCH 3/3 Tegra: Config: Enable Tegra30/Tegra114 USB function
In reply to Jim LinAdd USB EHCI, storage and network support.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.
--- include/configs/cardhu.h | 14 ++++++++++++++ include/configs/dalmore.h | 14 ++++++++++++++ include/configs/tegra114-common.h | 3 +++ include/configs/tegra30-common.h | 3 +++ 4 files changed, 34 insertions(+), 0 deletions(-)
include/configs/cardhu.h +14 -0
@@ -70,6 +70,20 @@#define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 << 20) +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#include "tegra-common-post.h" #endif /* __CONFIG_H */
include/configs/dalmore.h +14 -0
@@ -75,6 +75,20 @@#define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 << 20) +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#include "tegra-common-post.h" #endif /* __CONFIG_H */
include/configs/tegra114-common.h +3 -0
@@ -77,4 +77,7 @@/* Total I2C ports on Tegra114 */ #define TEGRA_I2C_NUM_CONTROLLERS 5 +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI +#endif /* _TEGRA114_COMMON_H_ */
include/configs/tegra30-common.h +3 -0
@@ -90,4 +90,7 @@/* Total I2C ports on Tegra30 */ #define TEGRA_I2C_NUM_CONTROLLERS 5 +/* For USB EHCI controller */ +#define CONFIG_EHCI_IS_TDI +#endif /* _TEGRA30_COMMON_H_ */
Signature · 1 line
1.7.7
PATCH 3/3 Tegra: Config: Enable Tegra30/Tegra114 USB function
Quoted 4 lines · Jim Lin
Add USB EHCI, storage and network support.
Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.
What about updating include/configs/beaver.h too?
cover Tegra: USB: EHCI: add Tegra30 compatible support
In reply to Jim LinQuoted 9 lines · Jim Lin
Tegra114 USB EHCI is compatible with Tegra30 USB EHCI except:
1. Port Reset - Tegra30 takes 55ms, Tegra114 takes 50 ms to finish.
2. PLL parameters.Jim Lin (3):
ARM: Tegra: FDT: Add USB support for T20/T30/T114
ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Tegra: Config: Enable Tegra30/Tegra114 USB function
The series,
On both Cardhu (Tegra30) and Dalmore (Tegra114). :-) :-) Now, I can netboot with upstream U-Boot on all my boards.
cover Tegra: USB: EHCI: add Tegra30 compatible support
Quoted 11 lines · Stephen Warren
Quoted 9 lines · Jim Lin
Tegra114 USB EHCI is compatible with Tegra30 USB EHCI except:
1. Port Reset - Tegra30 takes 55ms, Tegra114 takes 50 ms to finish.
2. PLL parameters.Jim Lin (3):
ARM: Tegra: FDT: Add USB support for T20/T30/T114
ARM: Tegra: USB: Add driver support for Tegra30/Tegra114
Tegra: Config: Enable Tegra30/Tegra114 USB function
Quoted 6 lines
The series,
Tested-by Stephen Warren <[email protected]>On both Cardhu (Tegra30) and Dalmore (Tegra114). :-) :-) Now, I can netboot with upstream U-Boot on all my boards.
I just noticed one problem with this patch series. If I run the following commands with Cardhu in its dock, and a USB Ethernet dongle attached to the dock:
usb start 0
dhcp ${scriptaddr} boot.scr.uimg
... then everything works as expected; the file is downloaded.
However, if I run those same commands with Cardhu either undocked, or docked but with no USB Ethernet dongle plugged into the dock, then the dhcp command hangs the system hard; CTRL-C won't interrupt it for example.
Can you please fix this?