clk: tegra114: Initialize host1x and related clocks
Subsystems (3)
PATCH 1/1 clk: tegra114: Initialize host1x and related clocks
From: Mikko Perttunen <[email protected]>
The host1x clock should be a child of PLLC and runs too fast by default, so throttle it while at it. The disp1 and disp2 clocks should use PLLP by default. They will usually be reparented to either pll_d_out0 or pll_d2_out0 as part of the display driver setup.
--- drivers/clk/tegra/clk-tegra114.c | 3 +++ 1 file changed, 3 insertions(+)
drivers/clk/tegra/clk-tegra114.c +3 -0
@@ -2223,6 +2223,9 @@ static struct tegra_clk_init_table init_table[] __initdata = { {i2s4, pll_a_out0, 11289600, 0}, {dfll_soc, pll_p, 51000000, 1}, {dfll_ref, pll_p, 51000000, 1}, + {host1x, pll_c, 150000000, 0}, + {disp1, pll_p, 600000000, 0}, + {disp2, pll_p, 600000000, 0}, {clk_max, clk_max, 0, 0}, /* This MUST be the last entry. */ };
Signature · 1 line
1.8.4
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Stephen Warren
Acked-byQuoted 6 lines · Thierry Reding
From: Mikko Perttunen <[email protected]>
The host1x clock should be a child of PLLC and runs too fast by default, so throttle it while at it. The disp1 and disp2 clocks should use PLLP by default. They will usually be reparented to either
pll_d_out0orpll_d2_out0as part of the display driver setup.