ths8200 fixes
cover ths8200 fixes
This patch series applies a few fixes for ths8200 from Cisco's internal tree.
PATCH 1/3 ths8200: Zero blanking level for RGB.
Currently only RGB444 input data is supported so set to zero.
Acked-by Lad, Prabhakar <[email protected]>
Signed-off-by Martin Bugge <[email protected]>
--- drivers/media/i2c/ths8200.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/media/i2c/ths8200.c +2 -2
@@ -217,8 +217,8 @@ static void ths8200_core_init(struct v4l2_subdev *sd)/* Disable embedded syncs on the output by setting * the amplitude to zero for all channels. */ -ths8200_write (sd,THS8200_DTG1_Y_SYNC_MSB ,0x2a ); -ths8200_write (sd,THS8200_DTG1_CBCR_SYNC_MSB ,0x2a ); +ths8200_write (sd,THS8200_DTG1_Y_SYNC_MSB ,0x00 ); +ths8200_write (sd,THS8200_DTG1_CBCR_SYNC_MSB ,0x00 ); }static void ths8200_setup (struct v4l2_subdev *sd,struct v4l2_bt_timings *bt)
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1.8.1.4
PATCH 2/3 ths8200: Corrected sync polarities setting.
In reply to Martin BuggeHS_IN/VS_IN was always set to positive.
Acked-by Lad, Prabhakar <[email protected]>
Signed-off-by Martin Bugge <[email protected]>
--- drivers/media/i2c/ths8200.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/media/i2c/ths8200.c +1 -1
@@ -356,7 +356,7 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt)/* Timing of video input bus is derived from HS, VS, and FID dedicated * inputs */ -ths8200_write (sd,THS8200_DTG2_CNTL ,0x47 | polarity); +ths8200_write (sd,THS8200_DTG2_CNTL ,0x44 | polarity);/* leave reset */ ths8200_s_stream (sd, true);
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1.8.1.4
PATCH 3/3 ths8200: Format adjustment.
In reply to Martin BuggeCloser inspection on excact transmitted format showed that we needed to add 1 on vertical sync.
Acked-by Lad, Prabhakar <[email protected]>
Signed-off-by Martin Bugge <[email protected]>
--- drivers/media/i2c/ths8200.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
drivers/media/i2c/ths8200.c +10 -10
@@ -318,15 +318,15 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt) (htotal(bt) >> 8) & 0x1f);ths8200_write (sd,THS8200_DTG2_HLENGTH_HDLY_LSB ,htotal (bt)); -/* v sync width transmitted */ -ths8200_write (sd,THS8200_DTG2_VLENGTH1_LSB , (bt->vsync) &0xff ); +/* v sync width transmitted (must add 1 to get correct output) */ +ths8200_write (sd,THS8200_DTG2_VLENGTH1_LSB , (bt->vsync +1 ) &0xff );ths8200_write_and_or (sd,THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB ,0x3f , - ((bt->vsync) >>2 ) &0xc0 ); + ((bt->vsync +1 ) >>2 ) &0xc0 ); -/* The pixel value v sync is asserted on */ +/* The pixel value v sync is asserted on (must add 1 to get correct output) */ ths8200_write_and_or (sd,THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB ,0xf8 , - (vtotal (bt)>>8 ) &0x7 ); -ths8200_write (sd,THS8200_DTG2_VDLY1_LSB ,vtotal (bt)); + ((vtotal (bt) +1 ) >>8 ) &0x7 ); +ths8200_write (sd,THS8200_DTG2_VDLY1_LSB ,vtotal (bt) +1 );/* For progressive video vlength2 must be set to all 0 and vdly2 must * be set to all 1.
@@ -336,11 +336,11 @@ static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt)ths8200_write (sd,THS8200_DTG2_VDLY2_LSB ,0xff );/* Internal delay factors to synchronize the sync pulses and the data */ -/* Experimental values delays (hor 4, ver 1) */ -ths8200_write (sd,THS8200_DTG2_HS_IN_DLY_MSB , (htotal (bt)>>8 ) &0x1f ); -ths8200_write (sd,THS8200_DTG2_HS_IN_DLY_LSB , (htotal (bt) -4 ) &0xff ); +/* Experimental values delays (hor 0, ver 0) */ +ths8200_write (sd,THS8200_DTG2_HS_IN_DLY_MSB ,0 ); +ths8200_write (sd,THS8200_DTG2_HS_IN_DLY_LSB ,0 );ths8200_write (sd,THS8200_DTG2_VS_IN_DLY_MSB ,0 ); -ths8200_write (sd,THS8200_DTG2_VS_IN_DLY_LSB ,1 ); +ths8200_write (sd,THS8200_DTG2_VS_IN_DLY_LSB ,0 );/* Polarity of received and transmitted sync signals */ if (bt->polarities &V4L2_DV_HSYNC_POS_POL ) {
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1.8.1.4