PCI:designware:Fix comment for setting number of lanes

Corrects comment for setting number of lanes.

---
 drivers/pci/host/pcie-designware.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

index 6d23d8c..391966f 100644
@@ -766,7 +766,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	u32 membase;
 	u32 memlimit;
 
-	/* set the number of lines as 4 */
+	/* set the number of lanes */
 	dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
 	val &= ~PORT_LINK_MODE_MASK;
 	switch (pp->lanes) {

1.7.0.1

This patch correct iATU programming for cfg1, io and mem viewport. Enable ATU only after configuring it.

---
 drivers/pci/host/pcie-designware.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

index 391966f..46f4a19 100644
@@ -522,13 +522,13 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
 			  PCIE_ATU_LIMIT);
 	dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)

@@ -537,7 +537,6 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,

@@ -545,6 +544,7 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
 			  PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)

@@ -553,7 +553,6 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
 			  PCIE_ATU_VIEWPORT);
 	dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
-	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 	dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
 	dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
 	dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,

@@ -561,6 +560,7 @@ static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
 	dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
 	dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
 			  PCIE_ATU_UPPER_TARGET);
+	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 }
 
 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,

1.7.0.1

K2NjIHN0YWJsZUB2Z2VyLmtlcm5lLm9yZw0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0t DQo+IEZyb206IE1vaGl0IEtVTUFSIERDRw0KPiBTZW50OiBUaHVyc2RheSwgRmVicnVhcnkgMjAs IDIwMTQgMTA6NTMgQU0NCj4gVG86IGpnMS5oYW5Ac2Ftc3VuZy5jb20NCj4gQ2M6IE1vaGl0IEtV TUFSIERDRzsgQWpheSBLSEFOREVMV0FMOyBCam9ybiBIZWxnYWFzOyBzcGVhci1kZXZlbDsNCj4g bGludXgtcGNpQHZnZXIua2VybmVsLm9yZw0KPiBTdWJqZWN0OiBbUEFUQ0ggMi8yXSBQQ0k6ZGVz aWdud2FyZTpGaXggaUFUVSBwcm9ncmFtbWluZyBmb3IgY2ZnMSwgaW8gYW5kDQo+IG1lbSB2aWV3 cG9ydA0KPiANCj4gVGhpcyBwYXRjaCBjb3JyZWN0IGlBVFUgcHJvZ3JhbW1pbmcgZm9yIGNmZzEs IGlvIGFuZCBtZW0gdmlld3BvcnQuDQo+IEVuYWJsZSBBVFUgb25seSBhZnRlciBjb25maWd1cmlu ZyBpdC4NCj4gDQo+IFNpZ25lZC1vZmYtYnk6IE1vaGl0IEt1bWFyIDxtb2hpdC5rdW1hckBzdC5j b20+DQo+IFNpZ25lZC1vZmYtYnk6IEFqYXkgS2hhbmRlbHdhbCA8YWpheS5raGFuZGVsd2FsQHN0 LmNvbT4NCj4gQ2M6IEppbmdvbyBIYW4gPGpnMS5oYW5Ac2Ftc3VuZy5jb20+DQo+IENjOiBCam9y biBIZWxnYWFzIDxiaGVsZ2Fzc0Bnb29nbGUuY29tPg0KPiBDYzogc3BlYXItZGV2ZWxAbGlzdC5z dC5jb20NCj4gQ2M6IGxpbnV4LXBjaUB2Z2VyLmtlcm5lbC5vcmcNCj4gLS0tDQo+ICBkcml2ZXJz L3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5jIHwgICAgNiArKystLS0NCj4gIDEgZmlsZXMgY2hh bmdlZCwgMyBpbnNlcnRpb25zKCspLCAzIGRlbGV0aW9ucygtKQ0KPiANCj4gZGlmZiAtLWdpdCBh L2RyaXZlcnMvcGNpL2hvc3QvcGNpZS1kZXNpZ253YXJlLmMgYi9kcml2ZXJzL3BjaS9ob3N0L3Bj aWUtDQo+IGRlc2lnbndhcmUuYw0KPiBpbmRleCAzOTE5NjZmLi40NmY0YTE5IDEwMDY0NA0KPiAt LS0gYS9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5jDQo+ICsrKyBiL2RyaXZlcnMv cGNpL2hvc3QvcGNpZS1kZXNpZ253YXJlLmMNCj4gQEAgLTUyMiwxMyArNTIyLDEzIEBAIHN0YXRp YyB2b2lkIGR3X3BjaWVfcHJvZ192aWV3cG9ydF9jZmcxKHN0cnVjdA0KPiBwY2llX3BvcnQgKnBw LCB1MzIgYnVzZGV2KQ0KPiAgCWR3X3BjaWVfd3JpdGVsX3JjKHBwLCBQQ0lFX0FUVV9SRUdJT05f T1VUQk9VTkQgfA0KPiBQQ0lFX0FUVV9SRUdJT05fSU5ERVgxLA0KPiAgCQkJICBQQ0lFX0FUVV9W SUVXUE9SVCk7DQo+ICAJZHdfcGNpZV93cml0ZWxfcmMocHAsIFBDSUVfQVRVX1RZUEVfQ0ZHMSwg UENJRV9BVFVfQ1IxKTsNCj4gLQlkd19wY2llX3dyaXRlbF9yYyhwcCwgUENJRV9BVFVfRU5BQkxF LCBQQ0lFX0FUVV9DUjIpOw0KPiAgCWR3X3BjaWVfd3JpdGVsX3JjKHBwLCBwcC0+Y2ZnMV9iYXNl LCBQQ0lFX0FUVV9MT1dFUl9CQVNFKTsNCj4gIAlkd19wY2llX3dyaXRlbF9yYyhwcCwgKHBwLT5j ZmcxX2Jhc2UgPj4gMzIpLA0KPiBQQ0lFX0FUVV9VUFBFUl9CQVNFKTsNCj4gIAlkd19wY2llX3dy aXRlbF9yYyhwcCwgcHAtPmNmZzFfYmFzZSArIHBwLT5jb25maWcuY2ZnMV9zaXplIC0gMSwNCj4g IAkJCSAgUENJRV9BVFVfTElNSVQpOw0KPiAgCWR3X3BjaWVfd3JpdGVsX3JjKHBwLCBidXNkZXYs IFBDSUVfQVRVX0xPV0VSX1RBUkdFVCk7DQo+ICAJZHdfcGNpZV93cml0ZWxfcmMocHAsIDAsIFBD SUVfQVRVX1VQUEVSX1RBUkdFVCk7DQo+ICsJZHdfcGNpZV93cml0ZWxfcmMocHAsIFBDSUVfQVRV X0VOQUJMRSwgUENJRV9BVFVfQ1IyKTsNCj4gIH0NCj4gDQo+ICBzdGF0aWMgdm9pZCBkd19wY2ll X3Byb2dfdmlld3BvcnRfbWVtX291dGJvdW5kKHN0cnVjdCBwY2llX3BvcnQgKnBwKQ0KPiBAQCAt NTM3LDcgKzUzNyw2IEBAIHN0YXRpYyB2b2lkDQo+IGR3X3BjaWVfcHJvZ192aWV3cG9ydF9tZW1f b3V0Ym91bmQoc3RydWN0IHBjaWVfcG9ydCAqcHApDQo+ICAJZHdfcGNpZV93cml0ZWxfcmMocHAs IFBDSUVfQVRVX1JFR0lPTl9PVVRCT1VORCB8DQo+IFBDSUVfQVRVX1JFR0lPTl9JTkRFWDAsDQo+ ICAJCQkgIFBDSUVfQVRVX1ZJRVdQT1JUKTsNCj4gIAlkd19wY2llX3dyaXRlbF9yYyhwcCwgUENJ RV9BVFVfVFlQRV9NRU0sIFBDSUVfQVRVX0NSMSk7DQo+IC0JZHdfcGNpZV93cml0ZWxfcmMocHAs IFBDSUVfQVRVX0VOQUJMRSwgUENJRV9BVFVfQ1IyKTsNCj4gIAlkd19wY2llX3dyaXRlbF9yYyhw cCwgcHAtPm1lbV9iYXNlLCBQQ0lFX0FUVV9MT1dFUl9CQVNFKTsNCj4gIAlkd19wY2llX3dyaXRl bF9yYyhwcCwgKHBwLT5tZW1fYmFzZSA+PiAzMiksDQo+IFBDSUVfQVRVX1VQUEVSX0JBU0UpOw0K PiAgCWR3X3BjaWVfd3JpdGVsX3JjKHBwLCBwcC0+bWVtX2Jhc2UgKyBwcC0+Y29uZmlnLm1lbV9z aXplIC0gMSwNCj4gQEAgLTU0NSw2ICs1NDQsNyBAQCBzdGF0aWMgdm9pZA0KPiBkd19wY2llX3By b2dfdmlld3BvcnRfbWVtX291dGJvdW5kKHN0cnVjdCBwY2llX3BvcnQgKnBwKQ0KPiAgCWR3X3Bj aWVfd3JpdGVsX3JjKHBwLCBwcC0+Y29uZmlnLm1lbV9idXNfYWRkciwNCj4gUENJRV9BVFVfTE9X RVJfVEFSR0VUKTsNCj4gIAlkd19wY2llX3dyaXRlbF9yYyhwcCwgdXBwZXJfMzJfYml0cyhwcC0+ Y29uZmlnLm1lbV9idXNfYWRkciksDQo+ICAJCQkgIFBDSUVfQVRVX1VQUEVSX1RBUkdFVCk7DQo+ ICsJZHdfcGNpZV93cml0ZWxfcmMocHAsIFBDSUVfQVRVX0VOQUJMRSwgUENJRV9BVFVfQ1IyKTsN Cj4gIH0NCj4gDQo+ICBzdGF0aWMgdm9pZCBkd19wY2llX3Byb2dfdmlld3BvcnRfaW9fb3V0Ym91 bmQoc3RydWN0IHBjaWVfcG9ydCAqcHApIEBADQo+IC01NTMsNyArNTUzLDYgQEAgc3RhdGljIHZv aWQgZHdfcGNpZV9wcm9nX3ZpZXdwb3J0X2lvX291dGJvdW5kKHN0cnVjdA0KPiBwY2llX3BvcnQg KnBwKQ0KPiAgCWR3X3BjaWVfd3JpdGVsX3JjKHBwLCBQQ0lFX0FUVV9SRUdJT05fT1VUQk9VTkQg fA0KPiBQQ0lFX0FUVV9SRUdJT05fSU5ERVgxLA0KPiAgCQkJICBQQ0lFX0FUVV9WSUVXUE9SVCk7 DQo+ICAJZHdfcGNpZV93cml0ZWxfcmMocHAsIFBDSUVfQVRVX1RZUEVfSU8sIFBDSUVfQVRVX0NS MSk7DQo+IC0JZHdfcGNpZV93cml0ZWxfcmMocHAsIFBDSUVfQVRVX0VOQUJMRSwgUENJRV9BVFVf Q1IyKTsNCj4gIAlkd19wY2llX3dyaXRlbF9yYyhwcCwgcHAtPmlvX2Jhc2UsIFBDSUVfQVRVX0xP V0VSX0JBU0UpOw0KPiAgCWR3X3BjaWVfd3JpdGVsX3JjKHBwLCAocHAtPmlvX2Jhc2UgPj4gMzIp LA0KPiBQQ0lFX0FUVV9VUFBFUl9CQVNFKTsNCj4gIAlkd19wY2llX3dyaXRlbF9yYyhwcCwgcHAt PmlvX2Jhc2UgKyBwcC0+Y29uZmlnLmlvX3NpemUgLSAxLCBAQCAtDQo+IDU2MSw2ICs1NjAsNyBA QCBzdGF0aWMgdm9pZCBkd19wY2llX3Byb2dfdmlld3BvcnRfaW9fb3V0Ym91bmQoc3RydWN0DQo+ IHBjaWVfcG9ydCAqcHApDQo+ICAJZHdfcGNpZV93cml0ZWxfcmMocHAsIHBwLT5jb25maWcuaW9f YnVzX2FkZHIsDQo+IFBDSUVfQVRVX0xPV0VSX1RBUkdFVCk7DQo+ICAJZHdfcGNpZV93cml0ZWxf cmMocHAsIHVwcGVyXzMyX2JpdHMocHAtPmNvbmZpZy5pb19idXNfYWRkciksDQo+ICAJCQkgIFBD SUVfQVRVX1VQUEVSX1RBUkdFVCk7DQo+ICsJZHdfcGNpZV93cml0ZWxfcmMocHAsIFBDSUVfQVRV X0VOQUJMRSwgUENJRV9BVFVfQ1IyKTsNCj4gIH0NCj4gDQo+ICBzdGF0aWMgaW50IGR3X3BjaWVf cmRfb3RoZXJfY29uZihzdHJ1Y3QgcGNpZV9wb3J0ICpwcCwgc3RydWN0IHBjaV9idXMgKmJ1cywN Cj4gLS0NCj4gMS43LjAuMQ0KDQo=

Hi,

Does this patch actually fixes device enumeration behind a PCIe-pci bridge or this is more of cleaning up the sequence?

Thanks
Kishon

SGVsbG8gS2lzaG9uLA0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEtp c2hvbiBWaWpheSBBYnJhaGFtIEkgW21haWx0bzpraXNob25AdGkuY29tXQ0KPiBTZW50OiBUaHVy c2RheSwgRmVicnVhcnkgMjAsIDIwMTQgNTowOCBQTQ0KPiBUbzogTW9oaXQgS1VNQVIgRENHOyBq ZzEuaGFuQHNhbXN1bmcuY29tDQo+IENjOiBBamF5IEtIQU5ERUxXQUw7IEJqb3JuIEhlbGdhYXM7 IHNwZWFyLWRldmVsOyBsaW51eC0NCj4gcGNpQHZnZXIua2VybmVsLm9yZw0KPiBTdWJqZWN0OiBS ZTogW1BBVENIIDIvMl0gUENJOmRlc2lnbndhcmU6Rml4IGlBVFUgcHJvZ3JhbW1pbmcgZm9yIGNm ZzEsIGlvDQo+IGFuZCBtZW0gdmlld3BvcnQNCj4gDQo+IEhpLA0KPiANCj4gT24gVGh1cnNkYXkg MjAgRmVicnVhcnkgMjAxNCAxMDo1MiBBTSwgTW9oaXQgS3VtYXIgd3JvdGU6DQo+ID4gVGhpcyBw YXRjaCBjb3JyZWN0IGlBVFUgcHJvZ3JhbW1pbmcgZm9yIGNmZzEsIGlvIGFuZCBtZW0gdmlld3Bv cnQuDQo+ID4gRW5hYmxlIEFUVSBvbmx5IGFmdGVyIGNvbmZpZ3VyaW5nIGl0Lg0KPiANCj4gRG9l cyB0aGlzIHBhdGNoIGFjdHVhbGx5IGZpeGVzIGRldmljZSBlbnVtZXJhdGlvbiBiZWhpbmQgYSBQ Q0llLXBjaSBicmlkZ2Ugb3INCj4gdGhpcyBpcyBtb3JlIG9mIGNsZWFuaW5nIHVwIHRoZSBzZXF1 ZW5jZT8NCj4gDQotIFRoaXMgcGF0Y2ggY29ycmVjdHMgQVRVIHByb2dyYW1taW5nIHNlcXVlbmNl LiBJIGFtIG5vdCBhd2FyZSBvZiBhbnkgc3VjaCBpc3N1ZSB3aXRoDQpjdXJyZW50IGRyaXZlci4g UGxzIHNwZWNpZnkgIHdoaWNoIGJyaWRnZSBkbyB5b3UgdXNlIGluIHlvdXIgc2V0dXAgYW5kIHdo YXQgaXMgdGhlIHByb2JsZW0/DQoNClJlZ2FyZHMNCk1vaGl0DQo=

Hi Mohit,

I tried with card [1], it had a PLX bridge chip. It couldn't read the configuration space of the device connected to the PCIe-PCI bridge.

Thanks
Kishon

[1] -> http://ratetorate.in/products/Wiretech-PCIe%252dto%252dPCI-Bridge-Card.

SGVsbG8gS2lzaG9uLA0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEtp c2hvbiBWaWpheSBBYnJhaGFtIEkgW21haWx0bzpraXNob25AdGkuY29tXQ0KPiBTZW50OiBUaHVy c2RheSwgRmVicnVhcnkgMjAsIDIwMTQgNTo0MyBQTQ0KPiBUbzogTW9oaXQgS1VNQVIgRENHOyBq ZzEuaGFuQHNhbXN1bmcuY29tDQo+IENjOiBBamF5IEtIQU5ERUxXQUw7IEJqb3JuIEhlbGdhYXM7 IHNwZWFyLWRldmVsOyBsaW51eC0NCj4gcGNpQHZnZXIua2VybmVsLm9yZw0KPiBTdWJqZWN0OiBS ZTogW1BBVENIIDIvMl0gUENJOmRlc2lnbndhcmU6Rml4IGlBVFUgcHJvZ3JhbW1pbmcgZm9yIGNm ZzEsIGlvDQo+IGFuZCBtZW0gdmlld3BvcnQNCj4gDQo+IEhpIE1vaGl0LA0KPiANCj4gT24gVGh1 cnNkYXkgMjAgRmVicnVhcnkgMjAxNCAwNToyOCBQTSwgTW9oaXQgS1VNQVIgRENHIHdyb3RlOg0K PiA+IEhlbGxvIEtpc2hvbiwNCj4gPg0KPiA+PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0K PiA+PiBGcm9tOiBLaXNob24gVmlqYXkgQWJyYWhhbSBJIFttYWlsdG86a2lzaG9uQHRpLmNvbV0N Cj4gPj4gU2VudDogVGh1cnNkYXksIEZlYnJ1YXJ5IDIwLCAyMDE0IDU6MDggUE0NCj4gPj4gVG86 IE1vaGl0IEtVTUFSIERDRzsgamcxLmhhbkBzYW1zdW5nLmNvbQ0KPiA+PiBDYzogQWpheSBLSEFO REVMV0FMOyBCam9ybiBIZWxnYWFzOyBzcGVhci1kZXZlbDsgbGludXgtDQo+ID4+IHBjaUB2Z2Vy Lmtlcm5lbC5vcmcNCj4gPj4gU3ViamVjdDogUmU6IFtQQVRDSCAyLzJdIFBDSTpkZXNpZ253YXJl OkZpeCBpQVRVIHByb2dyYW1taW5nIGZvcg0KPiA+PiBjZmcxLCBpbyBhbmQgbWVtIHZpZXdwb3J0 DQo+ID4+DQo+ID4+IEhpLA0KPiA+Pg0KPiA+PiBPbiBUaHVyc2RheSAyMCBGZWJydWFyeSAyMDE0 IDEwOjUyIEFNLCBNb2hpdCBLdW1hciB3cm90ZToNCj4gPj4+IFRoaXMgcGF0Y2ggY29ycmVjdCBp QVRVIHByb2dyYW1taW5nIGZvciBjZmcxLCBpbyBhbmQgbWVtIHZpZXdwb3J0Lg0KPiA+Pj4gRW5h YmxlIEFUVSBvbmx5IGFmdGVyIGNvbmZpZ3VyaW5nIGl0Lg0KPiA+Pg0KPiA+PiBEb2VzIHRoaXMg cGF0Y2ggYWN0dWFsbHkgZml4ZXMgZGV2aWNlIGVudW1lcmF0aW9uIGJlaGluZCBhIFBDSWUtcGNp DQo+ID4+IGJyaWRnZSBvciB0aGlzIGlzIG1vcmUgb2YgY2xlYW5pbmcgdXAgdGhlIHNlcXVlbmNl Pw0KPiA+Pg0KPiA+IC0gVGhpcyBwYXRjaCBjb3JyZWN0cyBBVFUgcHJvZ3JhbW1pbmcgc2VxdWVu Y2UuIEkgYW0gbm90IGF3YXJlIG9mIGFueQ0KPiA+IHN1Y2ggaXNzdWUgd2l0aCBjdXJyZW50IGRy aXZlci4gUGxzIHNwZWNpZnkgIHdoaWNoIGJyaWRnZSBkbyB5b3UgdXNlIGluIHlvdXINCj4gc2V0 dXAgYW5kIHdoYXQgaXMgdGhlIHByb2JsZW0/DQo+IA0KPiBJIHRyaWVkIHdpdGggY2FyZCBbMV0s IGl0IGhhZCBhIFBMWCBicmlkZ2UgY2hpcC4gSXQgY291bGRuJ3QgcmVhZCB0aGUgY29uZmlndXJh dGlvbg0KPiBzcGFjZSBvZiB0aGUgZGV2aWNlIGNvbm5lY3RlZCB0byB0aGUgUENJZS1QQ0kgYnJp ZGdlLg0KPiANCi0gSSBkb27igJl0IGhhdmUgdGhlIG1lbnRpb25lZCBjYXJkIHdpdGggbWUsIGJ1 dCB3ZSBhcmUgc3VjY2Vzc2Z1bGx5IHVzaW5nIExlY3JveSBQVEMgc3dpdGNoDQogYW5kIFNJTDMx MjQtMkNCMzY0IFBDSS1YIGNvbXBhdGlibGUgUkFJRCBjYXJkLg0KDQpNYXkgYmUgSmluZ29vIG9y IG90aGVycyBjYW4gYWxzbyBjb21tZW50IGlmIHRoZXkgYXJlIHVzaW5nIFBDSSBicmlkZ2UgY2Fy ZC4NCg0KVGhhbmtzDQpNb2hpdA0KDQo=

So do you see abort while reading config space of device connected to the PCIe-PCI bridge?

Do you see "received master abort" bit set in your RC's cfg register after you try to read?

Regards
Pratyush

subject line

PCI: designware: Fix comment for setting number of lanes

~Rajeev

SGVsbG8gUmFqZWV2LA0KDQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IFJh amVldiBLVU1BUg0KPiBTZW50OiBUaHVyc2RheSwgRmVicnVhcnkgMjAsIDIwMTQgMTI6MjYgUE0N Cj4gVG86IE1vaGl0IEtVTUFSIERDRw0KPiBDYzogamcxLmhhbkBzYW1zdW5nLmNvbTsgQmpvcm4g SGVsZ2Fhczsgc3BlYXItZGV2ZWw7IGxpbnV4LQ0KPiBwY2lAdmdlci5rZXJuZWwub3JnDQo+IFN1 YmplY3Q6IFJlOiBbUEFUQ0ggMS8yXSBQQ0k6ZGVzaWdud2FyZTpGaXggY29tbWVudCBmb3Igc2V0 dGluZyBudW1iZXIgb2YNCj4gbGFuZXMNCj4gDQo+IHN1YmplY3QgbGluZQ0KPiANCj4gUENJOiBk ZXNpZ253YXJlOiBGaXggY29tbWVudCBmb3Igc2V0dGluZyBudW1iZXIgb2YgbGFuZXMNCj4gDQot IHRoYW5rcywgd2lsbCBwdXQgc3BhY2VzLg0KDQpSZWdhcmRzDQpNb2hpdA0K