ppc4xx: Remove 4xx NAND booting support
Subsystems (3)
PATCH 1/1 ppc4xx: Remove 4xx NAND booting support
As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely.
This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported.
Signed-off-by Stefan Roese <[email protected]>
Cc Wolfgang Denk <[email protected]>
Cc Tirumala Marri <[email protected]>
Cc Matthias Fuchs <[email protected]>
Cc Masahiro Yamada <[email protected]>
Cc Tom Rini <[email protected]>
--- arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c | 20 ---- arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 12 --- arch/powerpc/cpu/ppc4xx/Makefile | 4 - arch/powerpc/cpu/ppc4xx/start.S | 111 +------------------ board/amcc/acadia/memory.c | 13 --- board/amcc/acadia/pll.c | 42 -------- board/amcc/bamboo/bamboo.c | 17 --- board/amcc/bamboo/init.S | 33 ------ board/amcc/canyonlands/canyonlands.c | 4 - board/amcc/canyonlands/init.S | 34 ------ board/amcc/sequoia/init.S | 32 ------ board/amcc/sequoia/sdram.c | 13 +-- board/amcc/sequoia/sequoia.c | 10 +- board/esd/pmc440/init.S | 32 ------ board/esd/pmc440/pmc440.c | 8 -- boards.cfg | 8 -- drivers/mtd/nand/ndfc.c | 13 --- include/configs/PMC440.h | 75 ------------- include/configs/acadia.h | 99 ----------------- include/configs/amcc-common.h | 6 -- include/configs/bamboo.h | 69 ------------ include/configs/canyonlands.h | 82 -------------- include/configs/kilauea.h | 85 --------------- include/configs/redwood.h | 1 - include/configs/sequoia.h | 70 +----------- nand_spl/board/amcc/acadia/Makefile | 88 --------------- nand_spl/board/amcc/acadia/config.mk | 31 ------ nand_spl/board/amcc/acadia/u-boot.lds | 48 --------- nand_spl/board/amcc/bamboo/Makefile | 70 ------------ nand_spl/board/amcc/bamboo/config.mk | 33 ------ nand_spl/board/amcc/bamboo/sdram.c | 76 ------------- nand_spl/board/amcc/bamboo/u-boot.lds | 50 --------- nand_spl/board/amcc/canyonlands/Makefile | 75 ------------- nand_spl/board/amcc/canyonlands/config.mk | 33 ------ nand_spl/board/amcc/canyonlands/ddr2_fixed.c | 130 ----------------------- nand_spl/board/amcc/canyonlands/u-boot.lds | 50 --------- nand_spl/board/amcc/kilauea/Makefile | 77 -------------- nand_spl/board/amcc/kilauea/config.mk | 32 ------ nand_spl/board/amcc/kilauea/u-boot.lds | 48 --------- nand_spl/board/amcc/sequoia/Makefile | 80 -------------- nand_spl/board/amcc/sequoia/config.mk | 33 ------ nand_spl/board/amcc/sequoia/u-boot.lds | 50 --------- 42 files changed, 15 insertions(+), 1882 deletions(-) delete mode 100644 nand_spl/board/amcc/acadia/Makefile delete mode 100644 nand_spl/board/amcc/acadia/config.mk delete mode 100644 nand_spl/board/amcc/acadia/u-boot.lds delete mode 100644 nand_spl/board/amcc/bamboo/Makefile delete mode 100644 nand_spl/board/amcc/bamboo/config.mk delete mode 100644 nand_spl/board/amcc/bamboo/sdram.c delete mode 100644 nand_spl/board/amcc/bamboo/u-boot.lds delete mode 100644 nand_spl/board/amcc/canyonlands/Makefile delete mode 100644 nand_spl/board/amcc/canyonlands/config.mk delete mode 100644 nand_spl/board/amcc/canyonlands/ddr2_fixed.c delete mode 100644 nand_spl/board/amcc/canyonlands/u-boot.lds delete mode 100644 nand_spl/board/amcc/kilauea/Makefile delete mode 100644 nand_spl/board/amcc/kilauea/config.mk delete mode 100644 nand_spl/board/amcc/kilauea/u-boot.lds delete mode 100644 nand_spl/board/amcc/sequoia/Makefile delete mode 100644 nand_spl/board/amcc/sequoia/config.mk delete mode 100644 nand_spl/board/amcc/sequoia/u-boot.lds
arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +0 -20
@@ -49,7 +49,6 @@ "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ } while (0) -#if !defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL )static void update_rdcc (void ) {u32 val;
@@ -72,7 +71,6 @@ static void update_rdcc(void) } } } -#endif #if defined(CONFIG_440 )/*
@@ -101,7 +99,6 @@ void dcbz_area(u32 start_address, u32 num_bytes);#define MULDIV64 (m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) -#if !defined(CONFIG_NAND_SPL )/*-----------------------------------------------------------------------------+ * sdram_memsize *-----------------------------------------------------------------------------*/
@@ -217,7 +214,6 @@ void board_add_ram_info(int use_default) val = (val &SDRAM_MMODE_DCL_MASK ) >>4 ;printf (", CL%d)" , val); } -#endif /* !CONFIG_NAND_SPL */ #if defined(CONFIG_SPD_EEPROM )
@@ -2843,16 +2839,6 @@ static void test(void)*---------------------------------------------------------------------------*/ phys_size_t initdram (int board_type) { -/* -* Only run this SDRAM init code once. For NAND booting -* targets like Kilauea, we call initdram() early from the -* 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot(). -* Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT) -* which calls initdram() again. This time the controller -* mustn't be reconfigured again since we're already running -* from SDRAM. -*/ -#if !defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL )unsigned long val;#if defined(CONFIG_440 )
@@ -2969,12 +2955,10 @@ phys_size_t initdram(int board_type)#endif #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) -#if !defined(CONFIG_NAND_U_BOOT ) && !defined(CONFIG_NAND_SPL )/*------------------------------------------------------------------ | DQS calibration. +-----------------------------------------------------------------*/ DQS_autocalibration (); -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ /*
@@ -3009,13 +2993,10 @@ phys_size_t initdram(int board_type)set_mcsr (get_mcsr ());#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ -#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ -return (CONFIG_SYS_MBYTES_SDRAM <<20 ); }#endif /* CONFIG_SPD_EEPROM */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)#if defined(CONFIG_440 )u32 mfdcr_any (u32 dcr) {
@@ -3062,7 +3043,6 @@ void mtdcr_any(u32 dcr, u32 val) } }#endif /* defined(CONFIG_440) */ -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ inline void ppc4xx_ibm_ddr2_register_dump (void ) {
arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +0 -12
@@ -27,12 +27,6 @@#include "ecc.h" -/* -* Only compile the DDR auto-calibration code for NOR boot and -* not for NAND boot (NAND SPL and NAND U-Boot - NUB) -*/ -#if !defined(CONFIG_NAND_U_BOOT ) && !defined(CONFIG_NAND_SPL ) -#define MAXBXCF 4#define SDRAM_RXBAS_SHIFT_1M 20
@@ -1231,9 +1225,3 @@ u32 DQS_autocalibration(void)return 0 ; } -#else /* defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ -u32 DQS_autocalibration (void ) -{ -return 0 ; -} -#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
arch/powerpc/cpu/ppc4xx/Makefile +0 -4
@@ -14,11 +14,7 @@ obj-y += kgdb.o obj-y += 40x_spd_sdram.o -ifndef CONFIG_NAND_SPL -ifndef CONFIG_NAND_U_BOOT obj-y += 44x_spd_ddr.o -endif -endif obj-$(CONFIG_SDRAM_PPC4xx_IBM_DDR2) += 44x_spd_ddr2.o obj-$(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) += 4xx_ibm_ddr2_autocalib.o obj-y += 4xx_pci.o
arch/powerpc/cpu/ppc4xx/start.S +5 -106
179 lines not on this page · raw message
board/amcc/acadia/memory.c +0 -13
@@ -17,7 +17,6 @@extern void board_pll_init_f (void ); -#if !defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL )static void cram_bcr_write (u32 wr_val) { wr_val <<=2 ;
@@ -41,20 +40,9 @@ static void cram_bcr_write(u32 wr_val)return ; } -#endif phys_size_t initdram (int board_type) { -#if defined(CONFIG_NAND_SPL ) -u32 reg; - -/* don't reinit PLL when booting via I2C bootstrap option */ -mfsdr (SDR0_PINSTP , reg); -if (reg !=0xf0000000 ) -board_pll_init_f (); -#endif - -#if !defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL )int i;u32 val;
@@ -88,7 +76,6 @@ phys_size_t initdram(int board_type)/* Wait a short while, since for NAND booting this is too fast */ for (i=0 ; i<200000 ; i++) ; -#endif return (CONFIG_SYS_MBYTES_RAM <<20 ); }
board/amcc/acadia/pll.c +0 -42
45 lines not on this page · raw message
board/amcc/bamboo/bamboo.c +0 -17
@@ -16,7 +16,6 @@ void ext_bus_cntlr_init(void);void configure_ppc440ep_pins (void );int is_nand_selected (void ); -#if !(defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL ))/************************************************************************* * * Bamboo has one bank onboard sdram (plus DIMM)
@@ -178,7 +177,6 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {0 ,0 }; -#endif #if 0 {/* GPIO Alternate1 Alternate2 Alternate3 */
@@ -440,15 +438,11 @@ int checkboard(void)phys_size_t initdram (int board_type) { -#if !(defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL ))long dram_size; dram_size =spd_sdram ();return dram_size; -#else -return CONFIG_SYS_MBYTES_SDRAM <<20 ; -#endif }/*----------------------------------------------------------------------------+
@@ -1794,23 +1788,12 @@ void configure_ppc440ep_pins(void)if (ppc440ep_core_selection[NAND_FLASH ] ==CORE_SELECTED ) {update_ndfc_ios (gpio_tab); - -#if !(defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL ))mtsdr (SDR0_CUST0 ,SDR0_CUST0_MUX_NDFC_SEL |SDR0_CUST0_NDFC_ENABLE |SDR0_CUST0_NDFC_BW_8_BIT |SDR0_CUST0_NDFC_ARE_MASK |SDR0_CUST0_CHIPSELGAT_EN1 |SDR0_CUST0_CHIPSELGAT_EN2 ); -#else -mtsdr (SDR0_CUST0 ,SDR0_CUST0_MUX_NDFC_SEL | -SDR0_CUST0_NDFC_ENABLE | -SDR0_CUST0_NDFC_BW_8_BIT | -SDR0_CUST0_NDFC_ARE_MASK | -SDR0_CUST0_CHIPSELGAT_EN0 | -SDR0_CUST0_CHIPSELGAT_EN2 ); -#endif -ndfc_selection_in_fpga (); }else
board/amcc/bamboo/init.S +0 -33
@@ -32,12 +32,7 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G) -#else - tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G) - tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG) -#endif /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
@@ -58,31 +53,3 @@ tlbtab: tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG) tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00 at h - ori r5,r5,TLB00 at l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01 at h - ori r5,r5,TLB01 at l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02 at h - ori r5,r5,TLB02 at l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif
board/amcc/canyonlands/canyonlands.c +0 -4
@@ -379,11 +379,7 @@ int board_early_init_r (void)*/ /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ -#if defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL ) -mtebc (PB3CR ,CONFIG_SYS_FLASH_BASE_PHYS_L |0xda000 ); -#else mtebc (PB0CR ,CONFIG_SYS_FLASH_BASE_PHYS_L |0xda000 ); -#endif /* Remove TLB entry of boot EBC mapping */ remove_tlb (CONFIG_SYS_BOOT_BASE_ADDR ,16 <<20 );
board/amcc/canyonlands/init.S +0 -34
@@ -31,13 +31,7 @@ tlbtab: * use the speed up boot process. It is patched after relocation to * enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */ -#else - tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G) - tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG) - tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG) -#endif /* * TLB entries for SDRAM are not needed on this platform.
@@ -95,31 +89,3 @@ tlbtab: #endif tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00 at h - ori r5,r5,TLB00 at l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01 at h - ori r5,r5,TLB01 at l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02 at h - ori r5,r5,TLB02 at l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif
board/amcc/sequoia/init.S +0 -32
@@ -48,11 +48,7 @@ tlbtab: /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) -#else - tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) -#endif #ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
@@ -81,31 +77,3 @@ tlbtab: tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */ - lis r5,TLB00 at h - ori r5,r5,TLB00 at l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01 at h - ori r5,r5,TLB01 at l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02 at h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif
board/amcc/sequoia/sdram.c +2 -11
@@ -26,14 +26,6 @@extern int denali_wait_for_dlllock (void );extern void denali_core_search_data_eye (void ); -#if defined(CONFIG_NAND_SPL ) -/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big -* for the 4k NAND boot image so define bus_frequency to 133MHz here -* which is save for the refresh counter setup. -*/ -#define get_bus_freq (val) 133333333 -#endif -/************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core
@@ -41,8 +33,7 @@ extern void denali_core_search_data_eye(void);************************************************************************/ phys_size_t initdram (int board_type) { -#if !(defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_SYS_RAMBOOT )) || \ - defined(CONFIG_NAND_SPL ) +#if !defined(CONFIG_SYS_RAMBOOT )ulong speed =get_bus_freq (0 );mtsdram (DDR0_02 ,0x00000000 );
@@ -81,7 +72,7 @@ phys_size_t initdram (int board_type)mtsdram (DDR0_02 ,0x00000001 );denali_wait_for_dlllock (); -#endif /* #ifndef CONFIG_NAND_U_BOOT */ +#endif /* #ifndef CONFIG_SYS_RAMBOOT */ #ifdef CONFIG_DDR_DATA_EYE /* -----------------------------------------------------------+
board/amcc/sequoia/sequoia.c +4 -6
@@ -142,8 +142,7 @@ int misc_init_r(void) gd->bd->bi_flashstart =0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset =0 ; -#if defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL ) || \ - defined(CONFIG_SYS_RAMBOOT ) +#if defined(CONFIG_SYS_RAMBOOT )mtdcr (EBC0_CFGADDR ,PB3CR );#else mtdcr (EBC0_CFGADDR ,PB0CR );
@@ -151,8 +150,7 @@ int misc_init_r(void) pbcr =mfdcr (EBC0_CFGDATA ); size_val =ffs (gd->bd->bi_flashsize) -21 ; pbcr = (pbcr &0x0001ffff ) | gd->bd->bi_flashstart | (size_val <<17 ); -#if defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL ) || \ - defined(CONFIG_SYS_RAMBOOT ) +#if defined(CONFIG_SYS_RAMBOOT )mtdcr (EBC0_CFGADDR ,PB3CR );#else mtdcr (EBC0_CFGADDR ,PB0CR );
@@ -360,7 +358,7 @@ void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) }#endif -#if defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_SYS_RAMBOOT ) +#if defined(CONFIG_SYS_RAMBOOT )/* * On NAND-booting sequoia, we need to patch the chips select numbers * in the dtb (CS0 - NAND, CS3 - NOR)
@@ -411,4 +409,4 @@ void ft_board_setup(void *blob, bd_t *bd) return; } } -#endif /* CONFIG_NAND_U_BOOT */ +#endif /* CONFIG_SYS_RAMBOOT */
board/esd/pmc440/init.S +0 -32
@@ -27,11 +27,7 @@ tlbtab: * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the * speed up boot process. It is patched after relocation to enable SA_I */ -#ifndef CONFIG_NAND_SPL tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) -#else - tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) -#endif /* TLB entries for DDR2 SDRAM are generated dynamically */
@@ -71,31 +67,3 @@ tlbtab: /* TODO: what about high IO space */ tlbtab_end - -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) - /* - * For NAND booting the first TLB has to be reconfigured to full size - * and with caching disabled after running from RAM! - */ -#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) -#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) -#define TLB02 TLB2(AC_RWX | SA_IG) - - .globl reconfig_tlb0 -reconfig_tlb0: - sync - isync - addi r4,r0,0x0000 /* TLB entry #0 */ - lis r5,TLB00 at h - ori r5,r5,TLB00 at l - tlbwe r5,r4,0x0000 /* Save it out */ - lis r5,TLB01 at h - ori r5,r5,TLB01 at l - tlbwe r5,r4,0x0001 /* Save it out */ - lis r5,TLB02 at h - ori r5,r5,TLB02@l - tlbwe r5,r4,0x0002 /* Save it out */ - sync - isync - blr -#endif
board/esd/pmc440/pmc440.c +0 -8
@@ -229,19 +229,11 @@ int misc_init_r(void) gd->bd->bi_flashstart =0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset =0 ; -#if defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL ) -mtdcr (EBC0_CFGADDR ,PB2CR ); -#else mtdcr (EBC0_CFGADDR ,PB0CR ); -#endif pbcr =mfdcr (EBC0_CFGDATA ); size_val =ffs (gd->bd->bi_flashsize) -21 ; pbcr = (pbcr &0x0001ffff ) | gd->bd->bi_flashstart | (size_val <<17 ); -#if defined(CONFIG_NAND_U_BOOT ) || defined(CONFIG_NAND_SPL ) -mtdcr (EBC0_CFGADDR ,PB2CR ); -#else mtdcr (EBC0_CFGADDR ,PB0CR ); -#endif mtdcr (EBC0_CFGDATA , pbcr);/*
boards.cfg +0 -8
@@ -1121,22 +1121,14 @@ Active powerpc ppc4xx - amcc - Active powerpc ppc4xx - amcc - taihu - John Otken <[email protected]> Active powerpc ppc4xx - amcc - taishan - Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc - yucca - - -Active powerpc ppc4xx - amcc acadia acadia_nand acadia:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <[email protected]> -Active powerpc ppc4xx - amcc bamboo bamboo_nand bamboo:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <[email protected]> -Active powerpc ppc4xx - amcc canyonlands canyonlands_nand canyonlands:CANYONLANDS,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <[email protected]> -Active powerpc ppc4xx - amcc canyonlands glacier_nand canyonlands:GLACIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <[email protected]> -Active powerpc ppc4xx - amcc kilauea haleakala_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <[email protected]> -Active powerpc ppc4xx - amcc kilauea kilauea_nand kilauea:NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <[email protected]> -Active powerpc ppc4xx - amcc sequoia rainier_nand sequoia:RAINIER,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <[email protected]> -Active powerpc ppc4xx - amcc sequoia sequoia_nand sequoia:SEQUOIA,NAND_U_BOOT,SYS_TEXT_BASE=0x01000000 Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <[email protected]> Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <[email protected]>
drivers/mtd/nand/ndfc.c +0 -13
@@ -104,7 +104,6 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) *p++ =in_be32 ((u32 *)(base +NDFC_DATA )); } -#ifndef CONFIG_NAND_SPL /* * Don't use these speedup functions in NAND boot image, since the image * has to fit into 4kByte.
@@ -148,8 +147,6 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd) } -#endif /* #ifndef CONFIG_NAND_SPL */ -void board_nand_select_device (struct nand_chip *nand,int chip) {/*
@@ -207,21 +204,11 @@ int board_nand_init(struct nand_chip *nand) nand->options |=NAND_BUSWIDTH_16 ;#endif -#ifndef CONFIG_NAND_SPL nand->write_buf = ndfc_write_buf; nand->verify_buf = ndfc_verify_buf; nand->read_byte = ndfc_read_byte; chip++; -#else -/* -* Setup EBC (CS0 only right now) -*/ -mtebc (EBC0_CFG ,CONFIG_SYS_NDFC_EBC0_CFG ); - -mtebc (PB0CR ,CONFIG_SYS_EBC_PB0CR ); -mtebc (PB0AP ,CONFIG_SYS_EBC_PB0AP ); -#endif return 0 ; }
include/configs/PMC440.h +0 -75
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include/configs/acadia.h +0 -99
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include/configs/amcc-common.h +0 -6
@@ -253,10 +253,4 @@ "cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ "upd=run load update\0" \ -#define CONFIG_AMCC_DEF_ENV_NAND_UPD \ - "u-boot-nand=" __stringify(CONFIG_HOSTNAME) "/u-boot-nand.bin\0"\ - "nload=tftp 200000 ${u-boot-nand}\0" \ - "nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \ - "nupd=run nload nupdate\0" -#endif /* __AMCC_COMMON_H */
include/configs/bamboo.h +0 -69
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include/configs/canyonlands.h +0 -82
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include/configs/kilauea.h +0 -85
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include/configs/redwood.h +0 -1
@@ -120,7 +120,6 @@CONFIG_AMCC_DEF_ENV \ CONFIG_AMCC_DEF_ENV_POWERPC \CONFIG_AMCC_DEF_ENV_NOR_UPD \ - CONFIG_AMCC_DEF_ENV_NAND_UPD \"kernel_addr=fc000000\0" \"fdt_addr=fc1e0000\0" \"ramdisk_addr=fc200000\0" \
include/configs/sequoia.h +4 -66
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nand_spl/board/amcc/acadia/Makefile deleted +0 -88
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nand_spl/board/amcc/acadia/config.mk deleted +0 -31
@@ -1,31 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr at denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 405EZ Reference Platform (Acadia) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into internal SRAM in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here. -# -CONFIG_SYS_TEXT_BASE = 0xf8004000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0xf8008000 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif
nand_spl/board/amcc/acadia/u-boot.lds deleted +0 -48
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nand_spl/board/amcc/bamboo/Makefile deleted +0 -70
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nand_spl/board/amcc/bamboo/config.mk deleted +0 -33
@@ -1,33 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr at denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 440EP Reference Platform (Bamboo) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into instruction-cache in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in i-cache here. -# -CONFIG_SYS_TEXT_BASE = 0x00800000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0x00804000 - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif
nand_spl/board/amcc/bamboo/sdram.c deleted +0 -76
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nand_spl/board/amcc/bamboo/u-boot.lds deleted +0 -50
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nand_spl/board/amcc/canyonlands/Makefile deleted +0 -75
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nand_spl/board/amcc/canyonlands/config.mk deleted +0 -33
@@ -1,33 +0,0 @@ -# -# (C) Copyright 2008 -# Stefan Roese, DENX Software Engineering, sr at denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 460EX Reference Platform (Canyonlands) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 460EX platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into internal SRAM in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here. -# -CONFIG_SYS_TEXT_BASE = 0xE3003000 - -# PAD_TO used to generate a 128kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x20000 -PAD_TO = 0xE3023000 - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif
nand_spl/board/amcc/canyonlands/ddr2_fixed.c deleted +0 -130
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nand_spl/board/amcc/canyonlands/u-boot.lds deleted +0 -50
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nand_spl/board/amcc/kilauea/Makefile deleted +0 -77
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nand_spl/board/amcc/kilauea/config.mk deleted +0 -32
@@ -1,32 +0,0 @@ -# -# (C) Copyright 2007 -# Stefan Roese, DENX Software Engineering, sr at denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 405EX Reference Platform (Kilauea) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into SDRAM since we can't access the NAND -# controller at CS0 while running from this location. So we set -# CONFIG_SYS_TEXT_BASE to starting address in SDRAM here. -# -CONFIG_SYS_TEXT_BASE = 0x00800000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0x00804000 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif
nand_spl/board/amcc/kilauea/u-boot.lds deleted +0 -48
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nand_spl/board/amcc/sequoia/Makefile deleted +0 -80
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nand_spl/board/amcc/sequoia/config.mk deleted +0 -33
@@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 -# Stefan Roese, DENX Software Engineering, sr at denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# -# -# AMCC 440EPx Reference Platform (Sequoia) board -# - -# -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff, -# in the last 4kBytes of memory space in cache. -# We will copy this SPL into internal SRAM in start.S. So we set -# CONFIG_SYS_TEXT_BASE to starting address in internal SRAM here. -# -CONFIG_SYS_TEXT_BASE = 0xE0013000 - -# PAD_TO used to generate a 16kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 0x4000 -PAD_TO = 0xE0017000 - -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif - -ifeq ($(dbcr),1) -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000 -endif
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Signature · 1 line
1.8.5.5
PATCH 1/1 ppc4xx: Remove 4xx NAND booting support
Hello Stefan,
Quoted 6 lines · On Tue, 4 Mar 2014 15:34:35 +0100 Stefan Roese <[email protected]> wrote:
As ppc4xx currently only supports the deprecated
nand_splinfrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely.This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported.
Could you add dead boards to doc/README.scrapyard, please?
Best Regards
Masahiro Yamada
PATCH 1/1 ppc4xx: Remove 4xx NAND booting support
In reply to Stefan RoeseHello Stefan,
Quoted 8 lines
Quoted 6 lines
As ppc4xx currently only supports the deprecated
nand_splinfrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely.This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported.
Could you add dead boards to doc/README.scrapyard, please?
Oops - my bad.
I should have noted "normal" boards are still alive.
So you don't have to add entries to doc/README.scrapyard, I think. I retract this request. Sorry.
I built all PowerPC boards and confirmed "normal" boards are not affected by this patch.
Looks fine to me.
Best Regards
Masahiro Yamada
PATCH 1/1 ppc4xx: Remove 4xx NAND booting support
In reply to Stefan RoeseHi Stefan,
Quoted 7 lines · Stefan Roese
As ppc4xx currently only supports the deprecated
nand_splinfrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely.This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported.
Quoted 6 lines
Signed-off-by Stefan Roese <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Tirumala Marri <[email protected]>Cc Matthias Fuchs <[email protected]>Cc Masahiro Yamada <[email protected]>Cc Tom Rini <[email protected]>
I used this chance to test today's U-Boot master with your patch on our PMC440 board. I do not see any problems related to your patch. So you may add
Tested-by Matthias Fuchs <[email protected]>
Matthias
Quoted 7 lines · Stefan Roese
As ppc4xx currently only supports the deprecated
nand_splinfrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely.This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported.
Quoted 7 lines
Signed-off-by Stefan Roese <[email protected]>Cc Wolfgang Denk <[email protected]>Cc Tirumala Marri <[email protected]>Cc Matthias Fuchs <[email protected]>Cc Masahiro Yamada <[email protected]>Cc Tom Rini <[email protected]>Tested-by Matthias Fuchs <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
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