intel_reg_dumper: add more details for DisplayPort MST regs

index 4bc299c..a482b5d 100644
@@ -1685,7 +1685,7 @@ DEBUGSTRING(hsw_debug_sfuse_strap)
 DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl)
 {
 	const char *enable, *port, *mode, *bpc, *vsync, *hsync, *edp_input;
-	const char *width;
+	const char *width, *payload;
 
 	enable = (val & (1<<31)) ? "enabled" : "disabled";
 

@@ -1771,6 +1771,7 @@ DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl)
 		break;
 	}
 
+	payload = (val & (1 << 8)) ? "DP VC enable" : "DP VC disable";
 	switch ((val >> 1) & 7) {
 	case 0:
 		width = "x1";

@@ -1786,8 +1787,110 @@ DEBUGSTRING(hsw_debug_pipe_ddi_func_ctl)
 		break;
 	}
 
-	snprintf(result, len, "%s, %s, %s, %s, %s, %s, %s, %s", enable,
-		 port, mode, bpc, vsync, hsync, edp_input, width);
+	snprintf(result, len, "%s, %s, %s, %s, %s, %s, %s, %s, %s", enable,
+		 port, mode, bpc, vsync, hsync, edp_input, payload, width);
+}
+
+DEBUGSTRING(hsw_debug_dp_tp_ctl)
+{
+	const char *enable, *mode, *force_act, *enh, *autotrain;
+	const char *linktrain;
+	enable = (val & (1<<31)) ? "enabled" : "disabled";
+	mode = (val & (1<<27)) ? "MST" : "SST";
+	force_act = (val & (1<<25)) ? ", Force ACT" : "";
+	enh = (val & (1<<18)) ? ", ENH Framing" : "";
+	autotrain = (val & (1<<15)) ? ", Auto training" : "";
+
+	switch ((val >> 8) & 7) {
+	case 0:
+		linktrain = "TP1";
+		break;
+	case 1:
+		linktrain = "TP2";
+		break;
+	case 2:
+		linktrain = "Idle";
+		break;
+	case 3:
+		linktrain = "Normal";
+		break;
+	case 4:
+		linktrain = "TP3";
+		break;
+	default:
+		linktrain = "Rsvd";
+		break;
+	}
+
+	snprintf(result, len, "%s, %s %s%s%s%s", enable, mode, force_act, enh, autotrain, linktrain);
+}
+
+DEBUGSTRING(hsw_debug_dp_tp_status)
+{
+	const char *idle, *active, *mi, *act, *mode, *nstreams;
+	const char *pm_vc2, *pm_vc1, *pm_vc0;
+	idle = (val & (1<<27)) ? "Idle sent, " : "";
+	active = (val & (1<<26)) ? "Active sent, " : "";
+	mi = (val & (1<<25)) ? "Min Idles sent, " : "";
+	act = (val & (1<<24)) ? "ACT sent, " : "";
+	mode = (val & (1<<23)) ? "MST" : "SST";
+
+	switch ((val >> 16) & 3) {
+	case 0:
+	default:
+		nstreams = "0 streams";
+		break;
+	case 1:
+		nstreams = "1 stream";
+		break;
+	case 2:
+		nstreams = "2 streams";
+		break;
+	case 3:
+		nstreams = "3 streams";
+		break;
+	}
+
+	switch ((val >> 8) & 3)  {
+	case 0:
+	default:
+		pm_vc2 = "VC2-A";
+		break;
+	case 1:
+		pm_vc2 = "VC2-B";
+		break;
+	case 2:
+		pm_vc2 = "VC2-C";
+		break;
+	}
+
+	switch ((val >> 4) & 3)  {
+	case 0:
+	default:
+		pm_vc1 = "VC1-A";
+		break;
+	case 1:
+		pm_vc1 = "VC1-B";
+		break;
+	case 2:
+		pm_vc1 = "VC1-C";
+		break;
+	}
+
+	switch ((val) & 3)  {
+	case 0:
+	default:
+		pm_vc0 = "VC0-A";
+		break;
+	case 1:
+		pm_vc0 = "VC0-B";
+		break;
+	case 2:
+		pm_vc0 = "VC0-C";
+		break;
+	}
+
+	snprintf(result, len, "%s%s%s%s%s %s %s %s %s", idle, active, mi, act, mode, nstreams, pm_vc2, pm_vc1, pm_vc0);
 }
 
 DEBUGSTRING(hsw_debug_wm_pipe)

@@ -2285,17 +2388,17 @@ static struct reg_debug haswell_debug_regs[] = {
 	DEFINEREG2(PIPE_DDI_FUNC_CTL_EDP, hsw_debug_pipe_ddi_func_ctl),
 
 	/* DP transport control */
-	DEFINEREG(DP_TP_CTL_A),
-	DEFINEREG(DP_TP_CTL_B),
-	DEFINEREG(DP_TP_CTL_C),
-	DEFINEREG(DP_TP_CTL_D),
-	DEFINEREG(DP_TP_CTL_E),
+	DEFINEREG2(DP_TP_CTL_A, hsw_debug_dp_tp_ctl),
+	DEFINEREG2(DP_TP_CTL_B, hsw_debug_dp_tp_ctl),
+	DEFINEREG2(DP_TP_CTL_C, hsw_debug_dp_tp_ctl),
+	DEFINEREG2(DP_TP_CTL_D, hsw_debug_dp_tp_ctl),
+	DEFINEREG2(DP_TP_CTL_E, hsw_debug_dp_tp_ctl),
 
 	/* DP status */
-	DEFINEREG(DP_TP_STATUS_B),
-	DEFINEREG(DP_TP_STATUS_C),
-	DEFINEREG(DP_TP_STATUS_D),
-	DEFINEREG(DP_TP_STATUS_E),
+	DEFINEREG2(DP_TP_STATUS_B, hsw_debug_dp_tp_status),
+	DEFINEREG2(DP_TP_STATUS_C, hsw_debug_dp_tp_status),
+	DEFINEREG2(DP_TP_STATUS_D, hsw_debug_dp_tp_status),
+	DEFINEREG2(DP_TP_STATUS_E, hsw_debug_dp_tp_status),
 
 	/* DDI buffer control */
 	DEFINEREG2(DDI_BUF_CTL_A, hsw_debug_ddi_buf_ctl),