pciehp: only wait command complete for real hotplug control

On system with 16 PCI express hotplug slots, customer complain every slot will report "Command not completed in 1000 msec" during initialization.

Intel says that we should only wait command complete only for
Electromechanical Interlock Control Power Controller Control
Power Indicator Control
Attention Indicator Control

For detail please check CF118 on
http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html

We saw same problems on system with AMD/Nvidia chipsets.

Two ways to address the problem:
1. change to only wait when (EIC, PCC, PIC, AIC) bits get changed.
2. or check CMD_COMPLETE and wait before write command. Only wait when CC is set and cmd_busy is true. For chipset from intel will only have CC set for real hotplug control, so we could skip the wait for others.

This patch is using second way.

With that we could save 16 seconds during booting, later with 32 sockets system with 64 pcie hotplug slots we could save 64 seconds.

This patch address spurious "cmd completed" event problem that that Rajat met.

(quoted diff) +0 -3

-v2: use second way that is suggested by Bjorn.
-v3: rebase after
        PCI: pciehp: Acknowledge spurious "cmd completed" event
-v4: add comments according to Bjorn.
     also add URL for Intel doc about the CC set on intel chipset.

Signed-off-by Yinghai Lu <[email protected]>

Tested-by Rajat Jain <[email protected]>

---
 drivers/pci/hotplug/pciehp_hpc.c |   48 ++++++++++++++++++++++++---------------
 1 file changed, 30 insertions(+), 18 deletions(-)

Index: linux-2.6/drivers/pci/hotplug/pciehp_hpc.c
===================================================================

drivers/pci/hotplug/pciehp_hpc.c +30 -18

@@ -155,20 +155,30 @@ static void pcie_write_cmd(struct contro
        u16 slot_status;
        u16 slot_ctrl;
 
+       /*
+        * We basically have two strategies for dealing with Command Complete.
+        * Both are legal according to the PCIe spec:
+        * A: Write command at first and wait for Command Complete is set.
+        * B: Wait at first iff Command Complete and cmd_busy are set,
+        *    that means previous command is not complete yet.
+        *    Then write command.
+        *
+        * Second way also cover "Command not completed in 1000 msec"
+        * Problem on system with chipsets that only set Command Complete
+        * for some "real" hotplug events like:
+        *      Electromechanical Interlock Control
+        *      Power Controller Control
+        *      Power Indicator Control
+        *      Attention Indicator Control
+        * like CF118 in
+        * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
+        */
+
        mutex_lock(&ctrl->ctrl_lock);
 
        pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
-       if (slot_status & PCI_EXP_SLTSTA_CC) {
-               pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
-                                          PCI_EXP_SLTSTA_CC);
-               if (!ctrl->no_cmd_complete) {
-                       /*
-                        * After 1 sec and CMD_COMPLETED still not set, just
-                        * proceed forward to issue the next command according
-                        * to spec. Just print out the error message.
-                        */
-                       ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
-               } else if (!NO_CMD_CMPL(ctrl)) {
+       if (ctrl->no_cmd_complete && slot_status & PCI_EXP_SLTSTA_CC) {
+               if (!NO_CMD_CMPL(ctrl)) {
                        /*
                         * This controller seems to notify of command completed
                         * event even though it supports none of power

@@ -184,16 +194,11 @@ static void pcie_write_cmd(struct contro
        }
 
        pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
-       slot_ctrl &= ~mask;
-       slot_ctrl |= (cmd & mask);
-       ctrl->cmd_busy = 1;
-       smp_mb();
-       pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
-
        /*
         * Wait for command completion.
         */
-       if (!ctrl->no_cmd_complete) {
+       if (!ctrl->no_cmd_complete && (slot_status & PCI_EXP_SLTSTA_CC) &&
+           ctrl->cmd_busy) {
                int poll = 0;
                /*
                 * if hotplug interrupt is not enabled or command

@@ -205,6 +210,13 @@ static void pcie_write_cmd(struct contro
                        poll = 1;
                 pcie_wait_cmd(ctrl, poll);
        }
+
+       slot_ctrl &= ~mask;
+       slot_ctrl |= (cmd & mask);
+       ctrl->cmd_busy = 1;
+       smp_mb();
+       pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
+
        mutex_unlock(&ctrl->ctrl_lock);
 }
 

Hello Yinghai,

Quoted 8 lines · Yinghai Lu

On system with 16 PCI express hotplug slots, customer complain every slot will report "Command not completed in 1000 msec" during initialization.

Intel says that we should only wait command complete only for
Electromechanical Interlock Control Power Controller Control
Power Indicator Control
Attention Indicator Control

The document that you sent is an Intel ERRATA. Thus it would be nice if you can please also mention CF118 in the context of it being an Intel "errata", so that people do not confuse it with being expected / default / standard behavior on all platforms.

Quoted 112 lines

For detail please check CF118 on
http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html

We saw same problems on system with AMD/Nvidia chipsets.

Two ways to address the problem:
1. change to only wait when (EIC, PCC, PIC, AIC) bits get changed.
2. or check CMD_COMPLETE and wait before write command. Only wait when CC is set and cmd_busy is true. For chipset from intel will only have CC set for real hotplug control, so we could skip the wait for others.

This patch is using second way.

With that we could save 16 seconds during booting, later with 32 sockets system with 64 pcie hotplug slots we could save 64 seconds.

This patch address spurious "cmd completed" event problem that that Rajat met.

(quoted diff) +0 -3

-v2: use second way that is suggested by Bjorn.
-v3: rebase after
        PCI: pciehp: Acknowledge spurious "cmd completed" event
-v4: add comments according to Bjorn.
     also add URL for Intel doc about the CC set on intel chipset.

Signed-off-by Yinghai Lu <[email protected]>

Tested-by Rajat Jain <[email protected]>

---
 drivers/pci/hotplug/pciehp_hpc.c |   48 ++++++++++++++++++++++++---------------
 1 file changed, 30 insertions(+), 18 deletions(-)

Index: linux-2.6/drivers/pci/hotplug/pciehp_hpc.c
===================================================================

drivers/pci/hotplug/pciehp_hpc.c +30 -18

@@ -155,20 +155,30 @@ static void pcie_write_cmd(struct contro
        u16 slot_status;
        u16 slot_ctrl;
 
+       /*
+        * We basically have two strategies for dealing with Command Complete.
+        * Both are legal according to the PCIe spec:
+        * A: Write command at first and wait for Command Complete is set.
+        * B: Wait at first iff Command Complete and cmd_busy are set,
+        *    that means previous command is not complete yet.
+        *    Then write command.
+        *
+        * Second way also cover "Command not completed in 1000 msec"
+        * Problem on system with chipsets that only set Command Complete
+        * for some "real" hotplug events like:
+        *      Electromechanical Interlock Control
+        *      Power Controller Control
+        *      Power Indicator Control
+        *      Attention Indicator Control
+        * like CF118 in
+        * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html
+        */
+
        mutex_lock(&ctrl->ctrl_lock);
 
        pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
-       if (slot_status & PCI_EXP_SLTSTA_CC) {
-               pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
-                                          PCI_EXP_SLTSTA_CC);
-               if (!ctrl->no_cmd_complete) {
-                       /*
-                        * After 1 sec and CMD_COMPLETED still not set, just
-                        * proceed forward to issue the next command according
-                        * to spec. Just print out the error message.
-                        */
-                       ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
-               } else if (!NO_CMD_CMPL(ctrl)) {
+       if (ctrl->no_cmd_complete && slot_status & PCI_EXP_SLTSTA_CC) {
+               if (!NO_CMD_CMPL(ctrl)) {
                        /*
                         * This controller seems to notify of command completed
                         * event even though it supports none of power

@@ -184,16 +194,11 @@ static void pcie_write_cmd(struct contro
        }
 
        pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
-       slot_ctrl &= ~mask;
-       slot_ctrl |= (cmd & mask);
-       ctrl->cmd_busy = 1;
-       smp_mb();
-       pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
-
        /*
         * Wait for command completion.
         */
-       if (!ctrl->no_cmd_complete) {
+       if (!ctrl->no_cmd_complete && (slot_status & PCI_EXP_SLTSTA_CC) &&
+           ctrl->cmd_busy) {
                int poll = 0;
                /*
                 * if hotplug interrupt is not enabled or command

@@ -205,6 +210,13 @@ static void pcie_write_cmd(struct contro
                        poll = 1;
                 pcie_wait_cmd(ctrl, poll);
        }
+
+       slot_ctrl &= ~mask;
+       slot_ctrl |= (cmd & mask);
+       ctrl->cmd_busy = 1;
+       smp_mb();
+       pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
+
        mutex_unlock(&ctrl->ctrl_lock);
 }
 

Quoted 2 lines · Yinghai Lu

With that we could save 16 seconds during booting, later with 32 sockets system with 64 pcie hotplug slots we could save 64 seconds.

Doesn't this just move a timeout out of the boot path and into a future hotplug event?

These controllers do not set the "No Command Completed Support" bit, so pciehp expects that they will generate Command Completed events after they process commands.

During initialization, pcie_enable_notification() writes a command to set the DLLSCE, ABPE, PDCE, MRLSCE, HPIE, CCIE bits. The (EIC, PCC, PIC, AIC) bits aren't changed, so per CF118, the controller will not set the Command Completed bit.

Later, when we turn on power to the slot, ctrl->cmd_busy will still be set, so won't we timeout waiting for the Command Completed bit?

(I think there's a bug in your patch (see below) that would explain why you wouldn't see this timeout in testing.)

drivers/pci/hotplug/pciehp_hpc.c static void pcie_write_cmd(struct contro · line 201

Quoted 6 lines

      /*
       * Wait for command completion.
       */

drivers/pci/hotplug/pciehp_hpc.c +2 -1

-     if (!ctrl->no_cmd_complete) {
+     if (!ctrl->no_cmd_complete && (slot_status & PCI_EXP_SLTSTA_CC) &&
+         ctrl->cmd_busy) {

I don't understand this change. Why do you test "slot_status & PCI_EXP_SLTSTA_CC" here? Did you mean to write this:

if (!ctrl->no_cmd_complete && !(slot_status & PCI_EXP_SLTSTA_CC) && ...

instead? I think we want to wait if (1) the controller generates Command Complete events and (2) Slot Status indicates that a command is still in progress.

Quoted 8 lines · Bjorn Helgaas

I don't understand this change. Why do you test "slot_status & PCI_EXP_SLTSTA_CC" here? Did you mean to write this:

if (!ctrl->no_cmd_complete && !(slot_status & PCI_EXP_SLTSTA_CC) && ...

instead? I think we want to wait if (1) the controller generates Command Complete events and (2) Slot Status indicates that a command is still in progress.

Yes. your logic is right for those real hotplug event, that means CC is not set, and isr is not called to clear cmd_busy.

but it will wait for real or non-real cmd right after non-real hotplug cmd.

looks like we need to start one timer for non-real hotplug to clear cmd_busy?

Quoted 15 lines · Yinghai Lu

Quoted 8 lines · Bjorn Helgaas

I don't understand this change. Why do you test "slot_status & PCI_EXP_SLTSTA_CC" here? Did you mean to write this:

if (!ctrl->no_cmd_complete && !(slot_status & PCI_EXP_SLTSTA_CC) && ...

instead? I think we want to wait if (1) the controller generates Command Complete events and (2) Slot Status indicates that a command is still in progress.

Yes. your logic is right for those real hotplug event, that means CC is not set, and isr is not called to clear cmd_busy.

but it will wait for real or non-real cmd right after non-real hotplug cmd.

Quoted 1 line

looks like we need to start one timer for non-real hotplug to clear cmd_busy?

That looks make it too complicated.

I would revert back to first way
change to only wait when (EIC, PCC, PIC, AIC) bits get changed.
and add one flag in ctrl to see if need to apply the rule.

Quoted 7 lines · Bjorn Helgaas

Quoted 2 lines · Yinghai Lu

With that we could save 16 seconds during booting, later with 32 sockets system with 64 pcie hotplug slots we could save 64 seconds.

Doesn't this just move a timeout out of the boot path and into a future hotplug event?

Both. But not affect real Hotplug events (EIC, PCC, PIC, AIC).

Quoted 10 lines

These controllers do not set the "No Command Completed Support" bit, so pciehp expects that they will generate Command Completed events after they process commands.

During initialization, pcie_enable_notification() writes a command to set the DLLSCE, ABPE, PDCE, MRLSCE, HPIE, CCIE bits. The (EIC, PCC, PIC, AIC) bits aren't changed, so per CF118, the controller will not set the Command Completed bit.

Quoted 2 lines

Later, when we turn on power to the slot, ctrl->cmd_busy will still be set, so won't we timeout waiting for the Command Completed bit?

If it is real hotplug events, cmd_busy will be cleared by pcie_isr.

If it is not real hotplug events, cmd_busy is still set, and but CC is not set.

later before we try to write cmd again, but only cmd_busy is set && CC is not set, that means previous write cmd is not real hotplug event. so we should not wait.

Quoted 10 lines

(I think there's a bug in your patch (see below) that would explain why you wouldn't see this timeout in testing.)

drivers/pci/hotplug/pciehp_hpc.c static void pcie_write_cmd(struct contro · line 201

Quoted 6 lines

      /*
       * Wait for command completion.
       */

drivers/pci/hotplug/pciehp_hpc.c +2 -1

-     if (!ctrl->no_cmd_complete) {
+     if (!ctrl->no_cmd_complete && (slot_status & PCI_EXP_SLTSTA_CC) &&
+         ctrl->cmd_busy) {

Quoted 8 lines

I don't understand this change. Why do you test "slot_status & PCI_EXP_SLTSTA_CC" here? Did you mean to write this:

if (!ctrl->no_cmd_complete && !(slot_status & PCI_EXP_SLTSTA_CC) && ...

instead? I think we want to wait if (1) the controller generates Command Complete events and (2) Slot Status indicates that a command is still in progress.

Yes. your logic is right for those real hotplug event, that means CC is not set, and isr is not called to clear cmd_busy.

but it will wait for real or non-real cmd right after non-real hotplug cmd.

looks like we need to start one timer for non-real hotplug to clear cmd_busy?

I think your current patch is incorrect because you wait if the previous command has completed, and you write a new command if the previous one is still in progress. That's backwards.