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PCI: imx6: fix boot hang when link already enabled

PATCH In review Fabio Estevam 2 participants 3 messages Aug 6, 2014 – Aug 7, 2014

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Arm i.MX and Layerscape PCI
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Fabio Estevam

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PATCH 1/1 PCI: imx6: fix boot hang when link already enabled

From: Fabio Estevam <[email protected]>

This fixes a boot hang observed when the bootloader already enabled the PCIe link for it's own use. The fundamental problem is that Freescale forgot to wire up the core reset, so software doesn't have a sane way to get the core into a defined state.

According to the DW PCIe core reference manual configuration of the core may only happen when the LTSSM is disabled, so this is one of the first things we do. Apparently this isn't safe to do when the LTSSM is in any other state than "detect" as we observe an instant machine hang when trying to do so while the link is already up.

As a workaround force LTSSM into detect state right before hitting the disable switch.

Tested on a mx6qsabresd board with PCI driver enabled in the bootloader and also with PCI driver disabled in the bootloader. The kernel boots succesfully on both cases now.

Cc <[email protected]> # 3.16
Signed-off-by Lucas Stach <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
---
 drivers/pci/host/pci-imx6.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
drivers/pci/host/pci-imx6.c +15 -0
index a568efa..2fa6d3a 100644
@@ -49,6 +49,9 @@ struct imx6_pcie {
 
 /* PCIe Port Logic registers (memory-mapped) */
 #define PL_OFFSET 0x700
+#define PCIE_PL_PFLR				(PL_OFFSET + 0x08)
+#define PCIE_PL_PFLR_LINK_STATE_MASK		(0x3f << 16)
+#define PCIE_PL_PFLR_FORCE_LINK			(1 << 15)
 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING	(1 << 29)

@@ -214,7 +217,19 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
 static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
+	u32 val;
+
+	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &val);
 
+	if (val & IMX6Q_GPR12_PCIE_CTL_2) {
+		val = readl(pp->dbi_base + PCIE_PL_PFLR);
+		val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
+		val |= PCIE_PL_PFLR_FORCE_LINK;
+		writel(val, pp->dbi_base + PCIE_PL_PFLR);
+
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				   IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
+	}
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 			IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
Signature · 1 line
1.9.1
#1 lore raw
Quoted 18 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

This fixes a boot hang observed when the bootloader already enabled the PCIe link for it's own use. The fundamental problem is that Freescale forgot to wire up the core reset, so software doesn't have a sane way to get the core into a defined state.

According to the DW PCIe core reference manual configuration of the core may only happen when the LTSSM is disabled, so this is one of the first things we do. Apparently this isn't safe to do when the LTSSM is in any other state than "detect" as we observe an instant machine hang when trying to do so while the link is already up.

As a workaround force LTSSM into detect state right before hitting the disable switch.

Quoted 7 lines

Tested on a mx6qsabresd board with PCI driver enabled in the bootloader and also with PCI driver disabled in the bootloader. The kernel boots succesfully on both cases now.

Cc <[email protected]> # 3.16
Signed-off-by Lucas Stach <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>

I believe Lucas already had a new version of his patch.

http://thread.gmane.org/gmane.linux.kernel.pci/33712/focus=33711

Shawn

Quoted 41 lines
---
 drivers/pci/host/pci-imx6.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
drivers/pci/host/pci-imx6.c +15 -0
index a568efa..2fa6d3a 100644
@@ -49,6 +49,9 @@ struct imx6_pcie {
 
 /* PCIe Port Logic registers (memory-mapped) */
 #define PL_OFFSET 0x700
+#define PCIE_PL_PFLR				(PL_OFFSET + 0x08)
+#define PCIE_PL_PFLR_LINK_STATE_MASK		(0x3f << 16)
+#define PCIE_PL_PFLR_FORCE_LINK			(1 << 15)
 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING	(1 << 29)

@@ -214,7 +217,19 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
 static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
+	u32 val;
+
+	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &val);
 
+	if (val & IMX6Q_GPR12_PCIE_CTL_2) {
+		val = readl(pp->dbi_base + PCIE_PL_PFLR);
+		val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
+		val |= PCIE_PL_PFLR_FORCE_LINK;
+		writel(val, pp->dbi_base + PCIE_PL_PFLR);
+
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				   IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
+	}
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 			IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
Signature · 1 line
1.9.1