drm/i915/bdw: Setup global hardware status page in execlists mode

Write HWS_PGA address even in execlists mode as the global hardware status page is still required. This address was previously uninitialized and HWSP writes would clobber whatever buffer happened to reside at GGTT address 0.

Issue: VIZ-2020

---
 drivers/gpu/drm/i915/intel_lrc.c |    5 +++++
 1 file changed, 5 insertions(+)

index 666cb28..ad36d66 100644
@@ -1678,6 +1678,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
 	uint32_t context_size;
 	struct intel_ringbuffer *ringbuf;
 	int ret;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 
 	WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
 	if (ctx->engine[ring->id].state)

@@ -1750,6 +1751,10 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
 		if (ring->status_page.page_addr == NULL)
 			return -ENOMEM;
 		ring->status_page.obj = ctx_obj;
+
+		I915_WRITE(RING_HWS_PGA(ring->mmio_base),
+				(u32)ring->status_page.gfx_addr);
+		POSTING_READ(RING_HWS_PGA(ring->mmio_base));
 	}
 
 	if (ring->id == RCS && !ctx->rcs_initialized) {

1.7.9.5

-------------------------------------Summary-------------------------------------
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=271/271->270/271
PNV: pass/total=269/271->271/271
ILK: pass/total=271/271->271/271
IVB: pass/total=271/271->271/271
SNB: pass/total=271/271->271/271
HSW: pass/total=271/271->271/271
BDW: pass/total=271/271->271/271 -------------------------------------Detailed-------------------------------------
test_platform: test_suite, test_case, result_with_drm_intel_nightly->result_with_patch_applied
BYT: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, PASS->DMESG_WARN
PNV: Intel_gpu_tools, igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-forked, TIMEOUT->PASS
PNV: Intel_gpu_tools, igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write-forked, TIMEOUT->PASS