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mmc: sdhci: Add HS400 support to SDHCI driver

PATCH Superseded Adrian Hunter 1 participant 5 messages Nov 6, 2014

Subsystems (2)
MMC, SD and SDIO Secure digital host controller interface (SDHCI) driver

v2 of 3 Superseded Latest is v3 →

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Adrian Hunter

author maintainer
#0 lore raw

v2 cover mmc: sdhci: Add HS400 support to SDHCI driver

Hi

Here is version 2 of some patches for SDHCI to support HS400 mode.

Changes in V2:

mmc: sdhci: Clear also HS400 1.2V capability if 1.2V is not supported
Rename MMC_CAPS2_1_2V to MMC_CAPS2_HSX00_1_2V

mmc: sdhci: Add HS400 support to SDHCI driver
Re-base on Ulf's current tree which required moving SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 to the next free quirk2 bit

Adrian Hunter (4):
mmc: sdhci: Remove unused SDHCI_CTRL_HS_SDR200
mmc: sdhci: Fix vqmmc error setting
mmc: sdhci: Clear also HS400 1.2V capability if 1.2V is not supported
mmc: sdhci: Add HS400 support to SDHCI driver

 drivers/mmc/host/sdhci.c  | 28 ++++++++++++++++++++--------
 drivers/mmc/host/sdhci.h  |  4 +++-
 include/linux/mmc/host.h  |  1 +
 include/linux/mmc/sdhci.h |  2 ++
 4 files changed, 26 insertions(+), 9 deletions(-)

Regards
Adrian

author maintainer
#1 lore raw

PATCH v2 1/4 mmc: sdhci: Remove unused SDHCI_CTRL_HS_SDR200

SDHCI_CTRL_HS_SDR200 is unused. Remove it.

Signed-off-by Adrian Hunter <[email protected]>
---
 drivers/mmc/host/sdhci.h | 1 -
 1 file changed, 1 deletion(-)
drivers/mmc/host/sdhci.h +0 -1
index c2ec7fc..79937cf 100644
@@ -161,7 +161,6 @@
 #define   SDHCI_CTRL_UHS_SDR50		0x0002
 #define   SDHCI_CTRL_UHS_SDR104		0x0003
 #define   SDHCI_CTRL_UHS_DDR50		0x0004
-#define   SDHCI_CTRL_HS_SDR200		0x0005 /* reserved value in SDIO spec */
 #define  SDHCI_CTRL_VDD_180		0x0008
 #define  SDHCI_CTRL_DRV_TYPE_MASK	0x0030
 #define   SDHCI_CTRL_DRV_TYPE_B		0x0000
Signature · 1 line
1.9.1
author maintainer
#2 lore raw

PATCH v2 2/4 mmc: sdhci: Fix vqmmc error setting

In reply to Adrian Hunter

supply.vqmmc is used with the IS_ERR macro which means the value must be valid or an error code. NULL is neither, so replace with ERR_PTR(-EINVAL).

Signed-off-by Adrian Hunter <[email protected]>
---
 drivers/mmc/host/sdhci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/mmc/host/sdhci.c +1 -1
index a743d52..c2f4754 100644
@@ -3096,7 +3096,7 @@ int sdhci_add_host(struct sdhci_host *host)
 		if (ret) {
 			pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
 				mmc_hostname(mmc), ret);
-			mmc->supply.vqmmc = NULL;
+			mmc->supply.vqmmc = ERR_PTR(-EINVAL);
 		}
 	}
Signature · 1 line
1.9.1
author maintainer
#3 lore raw

PATCH v2 3/4 mmc: sdhci: Clear also HS400 1.2V capability if 1.2V is not supported

In reply to Adrian Hunter

1.2V HS200 mode capability is cleared if there is not a voltage regulator that supports 1.2V. Do the same for 1.2V HS400 mode.

Signed-off-by Adrian Hunter <[email protected]>
---
 drivers/mmc/host/sdhci.c | 13 +++++++------
 include/linux/mmc/host.h |  1 +
 2 files changed, 8 insertions(+), 6 deletions(-)
drivers/mmc/host/sdhci.c +7 -6
index c2f4754..9d6825d 100644
@@ -3115,16 +3115,17 @@ int sdhci_add_host(struct sdhci_host *host)
 		/* SD3.0: SDR104 is supported so (for eMMC) the caps2
 		 * field can be promoted to support HS200.
 		 */
-		if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) {
+		if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
 			mmc->caps2 |= MMC_CAP2_HS200;
-			if (IS_ERR(mmc->supply.vqmmc) ||
-					!regulator_is_supported_voltage
-					(mmc->supply.vqmmc, 1100000, 1300000))
-				mmc->caps2 &= ~MMC_CAP2_HS200_1_2V_SDR;
-		}
 	} else if (caps[1] & SDHCI_SUPPORT_SDR50)
 		mmc->caps |= MMC_CAP_UHS_SDR50;
 
+	if ((mmc->caps2 & MMC_CAPS2_HSX00_1_2V) &&
+	    (IS_ERR(mmc->supply.vqmmc) ||
+	     !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
+					     1300000)))
+		mmc->caps2 &= ~MMC_CAPS2_HSX00_1_2V;
+
 	if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
 		!(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
 		mmc->caps |= MMC_CAP_UHS_DDR50;
include/linux/mmc/host.h +1 -0
index df0c153..b54eeb7 100644
@@ -289,6 +289,7 @@ struct mmc_host {
 #define MMC_CAP2_HS400_1_2V	(1 << 16)	/* Can support HS400 1.2V */
 #define MMC_CAP2_HS400		(MMC_CAP2_HS400_1_8V | \
 				 MMC_CAP2_HS400_1_2V)
+#define MMC_CAPS2_HSX00_1_2V	(MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
 #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
 
 	mmc_pm_flag_t		pm_caps;	/* supported pm features */
Signature · 1 line
1.9.1
author maintainer
#4 lore raw

PATCH v2 4/4 mmc: sdhci: Add HS400 support to SDHCI driver

In reply to Adrian Hunter

MMC core already has support for HS400. Add HS400 support to SDHCI driver. The SDHC Standard specification does not define HS400 so consequently HS400 support is non-standard. However HS400 is not selected without the host controller setting the corresponding capability flags so host controllers not yet supporting HS400 will not be affected. To support that, a quirk SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 is introduced to enable the use of capabilities register reserved bit-63 to indicate HS400 support.

Because HS400 is non-standard for SDHCI, it is possible that different vendors will do things in different ways. However HS200 support faced the same issue but currently there is only one solution. As such, no attempt has been made to provide for alternate HS400 solutions except for SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400.

Signed-off-by Adrian Hunter <[email protected]>
---
 drivers/mmc/host/sdhci.c  | 13 ++++++++++++-
 drivers/mmc/host/sdhci.h  |  3 +++
 include/linux/mmc/sdhci.h |  2 ++
 3 files changed, 17 insertions(+), 1 deletion(-)
drivers/mmc/host/sdhci.c +12 -1
index 9d6825d..9a035a5 100644
@@ -1148,6 +1148,9 @@ static u16 sdhci_get_preset_value(struct sdhci_host *host)
 	case MMC_TIMING_UHS_DDR50:
 		preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
 		break;
+	case MMC_TIMING_MMC_HS400:
+		preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
+		break;
 	default:
 		pr_warn("%s: Invalid UHS-I mode selected\n",
 			mmc_hostname(host->mmc));

@@ -1475,6 +1478,8 @@ void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
 	else if ((timing == MMC_TIMING_UHS_DDR50) ||
 		 (timing == MMC_TIMING_MMC_DDR52))
 		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+	else if (timing == MMC_TIMING_MMC_HS400)
+		ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
 }
 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);

@@ -1546,7 +1551,8 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
 		u16 clk, ctrl_2;
 
 		/* In case of UHS-I modes, set High Speed Enable */
-		if ((ios->timing == MMC_TIMING_MMC_HS200) ||
+		if ((ios->timing == MMC_TIMING_MMC_HS400) ||
+		    (ios->timing == MMC_TIMING_MMC_HS200) ||
 		    (ios->timing == MMC_TIMING_MMC_DDR52) ||
 		    (ios->timing == MMC_TIMING_UHS_SDR50) ||
 		    (ios->timing == MMC_TIMING_UHS_SDR104) ||

@@ -1893,6 +1899,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
 	 * tuning function has to be executed.
 	 */
 	switch (host->timing) {
+	case MMC_TIMING_MMC_HS400:
 	case MMC_TIMING_MMC_HS200:
 	case MMC_TIMING_UHS_SDR104:
 		break;

@@ -3120,6 +3127,10 @@ int sdhci_add_host(struct sdhci_host *host)
 	} else if (caps[1] & SDHCI_SUPPORT_SDR50)
 		mmc->caps |= MMC_CAP_UHS_SDR50;
 
+	if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
+	    (caps[1] & SDHCI_SUPPORT_HS400))
+		mmc->caps2 |= MMC_CAP2_HS400;
+
 	if ((mmc->caps2 & MMC_CAPS2_HSX00_1_2V) &&
 	    (IS_ERR(mmc->supply.vqmmc) ||
 	     !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
drivers/mmc/host/sdhci.h +3 -0
index 79937cf..ddd31cd 100644
@@ -161,6 +161,7 @@
 #define   SDHCI_CTRL_UHS_SDR50		0x0002
 #define   SDHCI_CTRL_UHS_SDR104		0x0003
 #define   SDHCI_CTRL_UHS_DDR50		0x0004
+#define   SDHCI_CTRL_HS400		0x0005 /* Non-standard */
 #define  SDHCI_CTRL_VDD_180		0x0008
 #define  SDHCI_CTRL_DRV_TYPE_MASK	0x0030
 #define   SDHCI_CTRL_DRV_TYPE_B		0x0000

@@ -203,6 +204,7 @@
 #define  SDHCI_RETUNING_MODE_SHIFT		14
 #define  SDHCI_CLOCK_MUL_MASK	0x00FF0000
 #define  SDHCI_CLOCK_MUL_SHIFT	16
+#define  SDHCI_SUPPORT_HS400	0x80000000 /* Non-standard */
 
 #define SDHCI_CAPABILITIES_1	0x44
 

@@ -235,6 +237,7 @@
 #define SDHCI_PRESET_FOR_SDR50 0x6A
 #define SDHCI_PRESET_FOR_SDR104        0x6C
 #define SDHCI_PRESET_FOR_DDR50 0x6E
+#define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
 #define SDHCI_PRESET_DRV_MASK  0xC000
 #define SDHCI_PRESET_DRV_SHIFT  14
 #define SDHCI_PRESET_CLKGEN_SEL_MASK   0x400
include/linux/mmc/sdhci.h +2 -0
index ae7f357..375af80 100644
@@ -104,6 +104,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA			(1<<9)
 /* need clear transfer mode register before send cmd */
 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD	(1<<10)
+/* Capability register bit-63 indicates HS400 support */
+#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400		(1<<11)
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
Signature · 1 line
1.9.1