x86: Better support of coreboot
v2 cover x86: Better support of coreboot
In theory U-Boot built for coreboot is supposed to run as a payload to be loaded by coreboot on every board that coreboot supports. The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE which are hardcoded in board defconfig and Kconfig files. For better support of coreboot, we want to make these two options configurable so that we can easily change them during 'make menuconfig' so that the generated U-Boot image for coreboot is board configuration aware.
Note this v2 patch series aims to better support coreboot, while v1 patch series just tried to resolve the issues seen on qemu. Several issues are fixed to make coreboot support in U-Boot more robust.
See v1 patch discussion
@ http://lists.denx.de/pipermail/u-boot/2015-January/200140.html
The official qemu U-Boot support will come in the future. This patch series have been tested with coreboot running on qemu and Intel Crown Bay (my own unofficiall simple port, not in coreboot mainline) then loading the U-Boot built with the new mechanism.
Changes in v2:
- Fix the CONFIG_COLLECT_TIMESTAMPS typo in the comment block and commit message
- Spell out TSC, MSR and PIT in the Kconfig help
- New patch to move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
- New patch to hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected
- New patch to make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurable
- New patch to move coreboot specific defines from coreboot.h to Kconfig
- New patch to move CONFIG_SYS_CAR_xxx to Kconfig
- New patch to remove include/configs/coreboot.h
- New patch to make chromebook_link the default board for coreboot
- Leave CROS_EC defines unchanged in coreboot.h
- New patch to configure pci memory regions
- New patch to update REAME.x86 for coreboot support
Bin Meng (12):
x86: coreboot: Set up timer base correctly
x86: Allow a hardcoded TSC frequency provided by Kconfig
x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to
Kconfig
x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected
x86: coreboot: Make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
configurable
x86: coreboot: Move coreboot specific defines from coreboot.h to
Kconfig
x86: Move CONFIG_SYS_CAR_xxx to Kconfig
x86: Remove include/configs/coreboot.h
x86: Make chromebook_link the default board for coreboot
x86: coreboot: Wrap cros_ec initialization
x86: coreboot: Configure pci memory regions
x86: Update REAME.x86 for coreboot support
arch/x86/Kconfig | 32 +++++ arch/x86/cpu/coreboot/Kconfig | 11 ++ arch/x86/cpu/coreboot/pci.c | 30 ++++- arch/x86/cpu/coreboot/timestamp.c | 33 +++--- arch/x86/cpu/ivybridge/Kconfig | 8 ++ arch/x86/dts/Makefile | 3 +- arch/x86/dts/chromebook_link.dts | 220 ++++++++++++++++++++++++++++++++++- arch/x86/dts/link.dts | 219 ---------------------------------- arch/x86/lib/tsc_timer.c | 8 +- board/coreboot/coreboot/Kconfig | 27 ++++- board/coreboot/coreboot/MAINTAINERS | 2 +- board/coreboot/coreboot/coreboot.c | 2 + board/google/chromebook_link/Kconfig | 9 ++ board/intel/crownbay/Kconfig | 1 + configs/coreboot-x86_defconfig | 1 - doc/README.x86 | 35 ++++++ include/configs/chromebook_link.h | 7 +- include/configs/coreboot.h | 75 ------------ include/configs/crownbay.h | 2 - 19 files changed, 401 insertions(+), 324 deletions(-) create mode 100644 arch/x86/cpu/coreboot/Kconfig mode change 120000 => 100644 arch/x86/dts/chromebook_link.dts delete mode 100644 arch/x86/dts/link.dts delete mode 100644 include/configs/coreboot.h
Signature · 1 line
1.8.2.1
PATCH v2 1/12 x86: coreboot: Set up timer base correctly
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value of base_time in coreboot's timestamp table as our timer base, otherwise TSC counter value will be used.
Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS, the value of base_time in the timestamp table is still zero, so we must exclude this case too (this is currently seen on booting coreboot in qemu).
---
Changes in v2:
- Fix the CONFIG_COLLECT_TIMESTAMPS typo in the comment block and commit message
arch/x86/cpu/coreboot/timestamp.c | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-)
arch/x86/cpu/coreboot/timestamp.c +20 -13
@@ -3,18 +3,7 @@* * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; version 2 of the License. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA +* SPDX-License-Identifier: GPL-2.0+ */ #include <common.h>
@@ -38,9 +27,27 @@ static struct timestamp_table *ts_table __attribute__((section(".data")));void timestamp_init (void ) { +#ifdef CONFIG_SYS_X86_TSC_TIMER +uint64_t base_time; +#endif + ts_table = lib_sysinfo.tstamp_table;#ifdef CONFIG_SYS_X86_TSC_TIMER -timer_set_base (ts_table->base_time); +/* +* If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value +* of base_time in coreboot's timestamp table as our timer base, +* otherwise TSC counter value will be used. +* +* Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS, +* the value of base_time in the timestamp table is still zero, so +* we must exclude this case too (this is currently seen on booting +* coreboot in qemu) +*/ +if (ts_table && ts_table->base_time) + base_time = ts_table->base_time; +else + base_time =rdtsc (); +timer_set_base (base_time);#endif timestamp_add_now (TS_U_BOOT_INITTED ); }
Signature · 1 line
1.8.2.1
PATCH v2 1/12 x86: coreboot: Set up timer base correctly
Quoted 9 lines · Bin Meng
If coreboot is built with
CONFIG_COLLECT_TIMESTAMPS, use the value ofbase_timein coreboot's timestamp table as our timer base, otherwise TSC counter value will be used.Sometimes even coreboot is built with
CONFIG_COLLECT_TIMESTAMPS, the value ofbase_timein the timestamp table is still zero, so we must exclude this case too (this is currently seen on booting coreboot in qemu).
Quoted 7 lines
Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- Fix theCONFIG_COLLECT_TIMESTAMPStypo in the comment block and commit message
PATCH v2 2/12 x86: Allow a hardcoded TSC frequency provided by Kconfig
In reply to Bin MengBy default U-Boot automatically calibrates TSC running frequency via MSR and PIT. The calibration may not work on every x86 processor, so a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to allow bypassing the calibration and assign a hardcoded TSC frequency CONFIG_TSC_FREQ_IN_MHZ.
Normally the bypass should be turned on in a simulation environment like qemu.
---
Changes in v2:
- Spell out TSC, MSR and PIT in the Kconfig help
arch/x86/Kconfig | 20 ++++++++++++++++++++ arch/x86/lib/tsc_timer.c | 8 ++++++-- 2 files changed, 26 insertions(+), 2 deletions(-)
arch/x86/Kconfig +20 -0
@@ -317,6 +317,26 @@ config FRAMEBUFFER_VESA_MODE endmenu +config TSC_CALIBRATION_BYPASS + bool "Bypass Time-Stamp Counter (TSC) calibration" + default n + help + By default U-Boot automatically calibrates Time-Stamp Counter (TSC) + running frequency via Model-Specific Register (MSR) and Programmable + Interval Timer (PIT). If the calibration does not work on your board, + select this option and provide a hardcoded TSC running frequency with + CONFIG_TSC_FREQ_IN_MHZ below. + + Normally this option should be turned on in a simulation environment + like qemu. + +config TSC_FREQ_IN_MHZ + int "Time-Stamp Counter (TSC) running frequency in MHz" + depends on TSC_CALIBRATION_BYPASS + default 1000 + help + The running frequency in MHz of Time-Stamp Counter (TSC). + source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/queensbay/Kconfig"
arch/x86/lib/tsc_timer.c +6 -2
@@ -78,7 +78,7 @@ static int match_cpu(u8 family, u8 model)* * Returns the calibration value or 0 if MSR calibration failed. */ -static unsigned long try_msr_calibrate_tsc (void ) +static unsigned long __maybe_unused try_msr_calibrate_tsc (void ) {u32 lo, hi, ratio, freq_id, freq;unsigned long res;
@@ -199,7 +199,7 @@ static inline int pit_expect_msb(unsigned char val, u64 *tscp,#define MAX_QUICK_PIT_MS 50#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) -static unsigned long quick_pit_calibrate (void ) +static unsigned long __maybe_unused quick_pit_calibrate (void ) {int i;u64 tsc, delta;
@@ -306,6 +306,9 @@ unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)if (gd->arch.tsc_mhz)return gd->arch.tsc_mhz; +#ifdef CONFIG_TSC_CALIBRATION_BYPASS + fast_calibrate =CONFIG_TSC_FREQ_IN_MHZ ; +#else fast_calibrate =try_msr_calibrate_tsc ();if (!fast_calibrate) {
@@ -313,6 +316,7 @@ unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)if (!fast_calibrate) panic("TSC frequency is ZERO"); } +#endif gd->arch.tsc_mhz = fast_calibrate;return fast_calibrate;
Signature · 1 line
1.8.2.1
PATCH v2 2/12 x86: Allow a hardcoded TSC frequency provided by Kconfig
Quoted 9 lines · Bin Meng
By default U-Boot automatically calibrates TSC running frequency via MSR and PIT. The calibration may not work on every x86 processor, so a new
KconfigoptionCONFIG_TSC_CALIBRATION_BYPASSis introduced to allow bypassing the calibration and assign a hardcoded TSC frequencyCONFIG_TSC_FREQ_IN_MHZ.Normally the bypass should be turned on in a simulation environment like qemu.
Quoted 6 lines
Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- Spell out TSC, MSR and PIT in theKconfighelp
Quoted 4 lines
arch/x86/Kconfig | 20 ++++++++++++++++++++ arch/x86/lib/tsc_timer.c | 8 ++++++-- 2 files changed, 26 insertions(+), 2 deletions(-)
PATCH v2 3/12 x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
In reply to Bin MengConvert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig options so that we can remove them from board configuration file.
---
Changes in v2:
- New patch to move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
arch/x86/Kconfig | 9 +++++++++ board/google/chromebook_link/Kconfig | 1 + board/intel/crownbay/Kconfig | 1 + include/configs/chromebook_link.h | 2 -- include/configs/crownbay.h | 2 -- 5 files changed, 11 insertions(+), 4 deletions(-)
arch/x86/Kconfig +9 -0
@@ -70,6 +70,15 @@ config SMM_TSEG config SMM_TSEG_SIZE hex +config X86_RESET_VECTOR + bool + default n + +config SYS_X86_START16 + hex + depends on X86_RESET_VECTOR + default 0xfffff800 + config BOARD_ROMSIZE_KB_512 bool config BOARD_ROMSIZE_KB_1024
board/google/chromebook_link/Kconfig +1 -0
@@ -14,6 +14,7 @@ config SYS_CONFIG_NAME config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select X86_RESET_VECTOR select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216
board/intel/crownbay/Kconfig +1 -0
@@ -14,6 +14,7 @@ config SYS_CONFIG_NAME config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select X86_RESET_VECTOR select INTEL_QUEENSBAY select BOARD_ROMSIZE_KB_1024
include/configs/chromebook_link.h +0 -2
@@ -19,11 +19,9 @@#define CONFIG_SYS_CAR_SIZE (128 * 1024)#define CONFIG_SYS_MONITOR_LEN (1 << 20)#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 -#define CONFIG_SYS_X86_START16 0xfffff800#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_X86_RESET_VECTOR #define CONFIG_NR_DRAM_BANKS 8#define CONFIG_X86_MRC_ADDR 0xfffa0000#define CONFIG_CACHE_MRC_SIZE_KB 512
include/configs/crownbay.h +0 -2
@@ -14,10 +14,8 @@#include <configs/x86-common.h> #define CONFIG_SYS_MONITOR_LEN (1 << 20) -#define CONFIG_SYS_X86_START16 0xfffff800#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_X86_RESET_VECTOR #define CONFIG_NR_DRAM_BANKS 1#define CONFIG_X86_SERIAL
Signature · 1 line
1.8.2.1
PATCH v2 3/12 x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
Quoted 11 lines · Bin Meng
Convert
CONFIG_X86_RESET_VECTORandCONFIG_SYS_X86_START16toKconfigoptions so that we can remove them from board configuration file.Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- New patch to moveCONFIG_X86_RESET_VECTORandCONFIG_SYS_X86_START16toKconfig
Quoted 6 lines
arch/x86/Kconfig | 9 +++++++++ board/google/chromebook_link/Kconfig | 1 + board/intel/crownbay/Kconfig | 1 + include/configs/chromebook_link.h | 2 -- include/configs/crownbay.h | 2 -- 5 files changed, 11 insertions(+), 4 deletions(-)
PATCH v2 4/12 x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected
In reply to Bin MengWhen CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip size is meaningless, hence hide it.
---
Changes in v2:
- New patch to hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected
arch/x86/Kconfig | 1 + 1 file changed, 1 insertion(+)
arch/x86/Kconfig +1 -0
@@ -94,6 +94,7 @@ config BOARD_ROMSIZE_KB_16384 choice prompt "ROM chip size" + depends on X86_RESET_VECTOR default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
Signature · 1 line
1.8.2.1
PATCH v2 4/12 x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected
Quoted 27 lines · Bin Meng
When
CONFIG_X86_RESET_VECTORis not selected, specifying the ROM chip size is meaningless, hence hide it.Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- New patch to hide ROM chip size whenCONFIG_X86_RESET_VECTORis not selectedarch/x86/Kconfig | 1 + 1 file changed, 1 insertion(+)arch/x86/Kconfig +1
-1@@ -94,6 +94,7 @@ config BOARD_ROMSIZE_KB_16384 choice prompt "ROM chip size" + depends on X86_RESET_VECTOR default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 --
Quoted 2 lines
1.8.2.1
PATCH v2 5/12 x86: coreboot: Make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurable
In reply to Bin MengIn theory U-Boot built for coreboot is supposed to run as a payload to be loaded by coreboot on every board that coreboot supports. The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE which are hardcoded in board defconfig and Kconfig files. For better support of coreboot, we want to make these two options configurable so that we can easily change them during 'make menuconfig' so that the generated U-Boot image for coreboot is board configuration aware.
---
Changes in v2:
- New patch to make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurable
board/coreboot/coreboot/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+)
board/coreboot/coreboot/Kconfig +13 -0
@@ -9,7 +9,20 @@ config SYS_VENDOR config SYS_SOC default "coreboot" +comment "coreboot specific options" + config SYS_CONFIG_NAME + string "Board configuration file" default "coreboot" + help + This option selects the board configuration file in include/configs/ + directory to be used to build U-Boot for coreboot. + +config DEFAULT_DEVICE_TREE + string "Board Device Tree Source (dts) file" + default "link" + help + This option selects the board Device Tree Source (dts) file in + arch/x86/dts/ directory to be used to build U-Boot for coreboot. endif
Signature · 1 line
1.8.2.1
PATCH v2 5/12 x86: coreboot: Make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurable
Quoted 10 lines · Bin Meng
In theory U-Boot built for coreboot is supposed to run as a payload to be loaded by coreboot on every board that coreboot supports. The U-Boot build process uses
SYS_CONFIG_NAMEandDEFAULT_DEVICE_TREEwhich are hardcoded in board defconfig andKconfigfiles. For better support of coreboot, we want to make these two options configurable so that we can easily change them during 'make menuconfig' so that the generated U-Boot image for coreboot is board configuration aware.Signed-off-by Bin Meng <[email protected]>
Quoted 7 lines
---
Changes in v2:
- New patch to makeSYS_CONFIG_NAMEandDEFAULT_DEVICE_TREEconfigurableboard/coreboot/coreboot/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+)
PATCH v2 6/12 x86: coreboot: Move coreboot specific defines from coreboot.h to Kconfig
In reply to Bin MengThere are many places in the U-Boot source tree which refer to CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT that is currently defined in coreboot.h.
Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch to board configuration file to build U-Boot later.
---
Changes in v2:
- New patch to move coreboot specific defines from coreboot.h to Kconfig
arch/x86/Kconfig | 2 ++ arch/x86/cpu/coreboot/Kconfig | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/x86/cpu/coreboot/Kconfig
arch/x86/Kconfig +2 -0
@@ -347,6 +347,8 @@ config TSC_FREQ_IN_MHZ help The running frequency in MHz of Time-Stamp Counter (TSC). +source "arch/x86/cpu/coreboot/Kconfig" + source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/queensbay/Kconfig"
arch/x86/cpu/coreboot/Kconfig new file +11 -0
@@ -0,0 +1,11 @@ +config SYS_COREBOOT + bool + default y + +config CBMEM_CONSOLE + bool + default y + +config VIDEO_COREBOOT + bool + default y
Signature · 1 line
1.8.2.1
PATCH v2 6/12 x86: coreboot: Move coreboot specific defines from coreboot.h to Kconfig
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng <[email protected]> wrote:
nit: coreboot-specific defines
arch/x86/cpu/coreboot/Kconfig
Quoted 38 lines
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT,CONFIG_CBMEM_CONSOLEandCONFIG_VIDEO_COREBOOTthat is currently defined incoreboot.h.Move them to
arch/x86/cpu/coreboot/Kconfigso that we can switch to board configuration file to build U-Boot later.Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- New patch to move coreboot specific defines fromcoreboot.htoKconfigarch/x86/Kconfig | 2 ++ arch/x86/cpu/coreboot/Kconfig | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/x86/cpu/coreboot/Kconfigarch/x86/Kconfig +2
-0@@ -347,6 +347,8 @@ config TSC_FREQ_IN_MHZ help The running frequency in MHz of Time-Stamp Counter (TSC). +source "arch/x86/cpu/coreboot/Kconfig" + source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/queensbay/Kconfig"arch/x86/cpu/coreboot/Kconfig new file +0
-0@@ -0,0 +1,11 @@
I think you need
if TARGET_COREBOOT
...
endif
around this. We don't wan to use coreboot for chromebook_link, for example.
Quoted 13 lines
arch/x86/cpu/coreboot/Kconfig new file +11
-1+config SYS_COREBOOT + bool + default y + +config CBMEM_CONSOLE + bool + default y + +config VIDEO_COREBOOT + bool + default y --
Quoted 2 lines
1.8.2.1
Also you should remove these options from include/configs/coreboot.h to avoid build errors.
Regards,
Simon
PATCH v2 6/12 x86: coreboot: Move coreboot specific defines from coreboot.h to Kconfig
Hi Simon,
Quoted 5 lines · Simon Glass
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng <[email protected]> wrote:
nit: coreboot-specific defines
OK.
Quoted 41 lines
arch/x86/cpu/coreboot/Kconfig
Quoted 38 lines
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT,CONFIG_CBMEM_CONSOLEandCONFIG_VIDEO_COREBOOTthat is currently defined incoreboot.h.Move them to
arch/x86/cpu/coreboot/Kconfigso that we can switch to board configuration file to build U-Boot later.Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- New patch to move coreboot specific defines fromcoreboot.htoKconfigarch/x86/Kconfig | 2 ++ arch/x86/cpu/coreboot/Kconfig | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/x86/cpu/coreboot/Kconfigarch/x86/Kconfig +2
-0@@ -347,6 +347,8 @@ config TSC_FREQ_IN_MHZ help The running frequency in MHz of Time-Stamp Counter (TSC). +source "arch/x86/cpu/coreboot/Kconfig" + source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/queensbay/Kconfig"arch/x86/cpu/coreboot/Kconfig new file +0
-0@@ -0,0 +1,11 @@I think you need
Quoted 5 lines
if
TARGET_COREBOOT
...
endif
around this. We don't wan to use coreboot forchromebook_link, for example.
Yes, will fix.
Quoted 10 lines
Quoted 10 lines
arch/x86/cpu/coreboot/Kconfig new file +10
-0+config SYS_COREBOOT + bool + default y + +config CBMEM_CONSOLE + bool + default y + +config VIDEO_COREBOOT + bool
Quoted 8 lines
Quoted 5 lines
arch/x86/cpu/coreboot/Kconfig new file +1
-1+ default y --1.8.2.1
Also you should remove these options from
include/configs/coreboot.hto avoid build errors.
The coreboot.h is removed in the follow-up patch in this series.
Regards,
Bin
PATCH v2 6/12 x86: coreboot: Move coreboot specific defines from coreboot.h to Kconfig
Hi Bin,
Quoted 79 lines · Bin Meng
Hi Simon,
Quoted 5 lines · Simon Glass
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng <[email protected]> wrote:
nit: coreboot-specific defines
OK.
Quoted 41 lines
arch/x86/cpu/coreboot/Kconfig
Quoted 38 lines
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT,CONFIG_CBMEM_CONSOLEandCONFIG_VIDEO_COREBOOTthat is currently defined incoreboot.h.Move them to
arch/x86/cpu/coreboot/Kconfigso that we can switch to board configuration file to build U-Boot later.Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- New patch to move coreboot specific defines fromcoreboot.htoKconfigarch/x86/Kconfig | 2 ++ arch/x86/cpu/coreboot/Kconfig | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/x86/cpu/coreboot/Kconfigarch/x86/Kconfig +2
-0@@ -347,6 +347,8 @@ config TSC_FREQ_IN_MHZ help The running frequency in MHz of Time-Stamp Counter (TSC). +source "arch/x86/cpu/coreboot/Kconfig" + source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/queensbay/Kconfig"arch/x86/cpu/coreboot/Kconfig new file +0
-0@@ -0,0 +1,11 @@I think you need
Quoted 5 lines
if
TARGET_COREBOOT
...
endif
around this. We don't wan to use coreboot forchromebook_link, for example.Yes, will fix.
Quoted 10 lines
Quoted 10 lines
arch/x86/cpu/coreboot/Kconfig new file +10
-0+config SYS_COREBOOT + bool + default y + +config CBMEM_CONSOLE + bool + default y + +config VIDEO_COREBOOT + boolQuoted 8 lines
Quoted 5 lines
arch/x86/cpu/coreboot/Kconfig new file +1
-1+ default y --1.8.2.1
Also you should remove these options from
include/configs/coreboot.hto avoid build errors.
Quoted 1 line
The
coreboot.his removed in the follow-up patch in this series.
Yes I see that, but then this patch will break the build - we do try to keep things bisectable, so that you can check out any commit and build it (in extremis it is OK if it doesn't actually work fully though).
Regards,
Simon
PATCH v2 6/12 x86: coreboot: Move coreboot specific defines from coreboot.h to Kconfig
Hi Simon,
Quoted 82 lines · Simon Glass
Hi Bin,
Quoted 79 lines · Bin Meng
Hi Simon,
Quoted 5 lines · Simon Glass
Hi Bin,
On 5 January 2015 at 08:28, Bin Meng <[email protected]> wrote:
nit: coreboot-specific defines
OK.
Quoted 41 lines
arch/x86/cpu/coreboot/Kconfig
Quoted 38 lines
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT,CONFIG_CBMEM_CONSOLEandCONFIG_VIDEO_COREBOOTthat is currently defined incoreboot.h.Move them to
arch/x86/cpu/coreboot/Kconfigso that we can switch to board configuration file to build U-Boot later.Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- New patch to move coreboot specific defines fromcoreboot.htoKconfigarch/x86/Kconfig | 2 ++ arch/x86/cpu/coreboot/Kconfig | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/x86/cpu/coreboot/Kconfigarch/x86/Kconfig +2
-0@@ -347,6 +347,8 @@ config TSC_FREQ_IN_MHZ help The running frequency in MHz of Time-Stamp Counter (TSC). +source "arch/x86/cpu/coreboot/Kconfig" + source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/queensbay/Kconfig"arch/x86/cpu/coreboot/Kconfig new file +0
-0@@ -0,0 +1,11 @@I think you need
Quoted 5 lines
if
TARGET_COREBOOT
...
endif
around this. We don't wan to use coreboot forchromebook_link, for example.Yes, will fix.
Quoted 18 lines
Quoted 13 lines
arch/x86/cpu/coreboot/Kconfig new file +11
-1+config SYS_COREBOOT + bool + default y + +config CBMEM_CONSOLE + bool + default y + +config VIDEO_COREBOOT + bool + default y --Quoted 2 lines
1.8.2.1
Also you should remove these options from
include/configs/coreboot.hto avoid build errors.
Quoted 7 lines
Quoted 1 line
The
coreboot.his removed in the follow-up patch in this series.Yes I see that, but then this patch will break the build - we do try to keep things bisectable, so that you can check out any commit and build it (in extremis it is OK if it doesn't actually work fully though).
Understood, will fix.
Regards,
Bin
PATCH v2 7/12 x86: Move CONFIG_SYS_CAR_xxx to Kconfig
In reply to Bin MengMove CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that we don't need them in the board configuration file thus the same board configuratoin file can be used to build both coreboot version and bare version.
---
Changes in v2:
- New patch to move CONFIG_SYS_CAR_xxx to Kconfig
board/coreboot/coreboot/Kconfig | 12 ++++++++++++ board/google/chromebook_link/Kconfig | 8 ++++++++ include/configs/chromebook_link.h | 4 ++-- 3 files changed, 22 insertions(+), 2 deletions(-)
board/coreboot/coreboot/Kconfig +12 -0
@@ -25,4 +25,16 @@ config DEFAULT_DEVICE_TREE This option selects the board Device Tree Source (dts) file in arch/x86/dts/ directory to be used to build U-Boot for coreboot. +config SYS_CAR_ADDR + hex "Board specific Cache-As-RAM (CAR) address" + default 0x19200000 + help + This option specifies the board specific Cache-As-RAM (CAR) address. + +config SYS_CAR_SIZE + hex "Board specific Cache-As-RAM (CAR) size" + default 0x4000 + help + This option specifies the board specific Cache-As-RAM (CAR) size. + endif
board/google/chromebook_link/Kconfig +8 -0
@@ -30,4 +30,12 @@ config EARLY_POST_CROS_EC bool "Enable early post to Chrome OS EC" default y +config SYS_CAR_ADDR + hex + default 0xff7e0000 + +config SYS_CAR_SIZE + hex + default 0x20000 + endif
include/configs/chromebook_link.h +2 -2
@@ -15,9 +15,9 @@#include <configs/x86-common.h> -#define CONFIG_SYS_CAR_ADDR 0xff7e0000 -#define CONFIG_SYS_CAR_SIZE (128 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO
Signature · 1 line
1.8.2.1
PATCH v2 7/12 x86: Move CONFIG_SYS_CAR_xxx to Kconfig
Quoted 9 lines · Bin Meng
Move
CONFIG_SYS_CAR_ADDRandCONFIG_SYS_CAR_SIZEtoKconfigso that we don't need them in the board configuration file thus the same board configuratoin file can be used to build both coreboot version and bare version.Signed-off-by Bin Meng <[email protected]>---
Quoted 7 lines
Changes in v2:
- New patch to moveCONFIG_SYS_CAR_xxxtoKconfigboard/coreboot/coreboot/Kconfig | 12 ++++++++++++ board/google/chromebook_link/Kconfig | 8 ++++++++ include/configs/chromebook_link.h | 4 ++-- 3 files changed, 22 insertions(+), 2 deletions(-)
PATCH v2 8/12 x86: Remove include/configs/coreboot.h
In reply to Bin MengSince we already swtiched to use the new mechanism for building U-Boot for coreboot, coreboot.h is no longer needed so remove it.
---
Changes in v2:
- New patch to remove include/configs/coreboot.h
board/coreboot/coreboot/MAINTAINERS | 2 +- include/configs/coreboot.h | 75 ------------------------------------- 2 files changed, 1 insertion(+), 76 deletions(-) delete mode 100644 include/configs/coreboot.h
board/coreboot/coreboot/MAINTAINERS +1 -1
@@ -2,5 +2,5 @@ COREBOOT BOARD M: Simon Glass <[email protected]> S: Maintained F: board/coreboot/coreboot/ -F: include/configs/coreboot.h +F: include/configs/chromebook_link.h F: configs/coreboot-x86_defconfig
include/configs/coreboot.h deleted +0 -75
75 lines not on this page · raw message
Signature · 1 line
1.8.2.1
PATCH v2 8/12 x86: Remove include/configs/coreboot.h
Quoted 7 lines · Bin Meng
Since we already swtiched to use the new mechanism for building U-Boot for coreboot,
coreboot.his no longer needed so remove it.Signed-off-by Bin Meng <[email protected]>---
Quoted 7 lines
Changes in v2:
- New patch to removeinclude/configs/coreboot.hboard/coreboot/coreboot/MAINTAINERS | 2 +- include/configs/coreboot.h | 75 ------------------------------------- 2 files changed, 1 insertion(+), 76 deletions(-) delete mode 100644 include/configs/coreboot.h
PATCH v2 9/12 x86: Make chromebook_link the default board for coreboot
In reply to Bin MengChange SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts.
To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.
---
Changes in v2:
- New patch to make chromebook_link the default board for coreboot
arch/x86/cpu/ivybridge/Kconfig | 8 ++ arch/x86/dts/Makefile | 3 +- arch/x86/dts/chromebook_link.dts | 220 +++++++++++++++++++++++++++++++++++++- arch/x86/dts/link.dts | 219 ------------------------------------- board/coreboot/coreboot/Kconfig | 4 +- configs/coreboot-x86_defconfig | 1 - include/configs/chromebook_link.h | 1 - 7 files changed, 230 insertions(+), 226 deletions(-) mode change 120000 => 100644 arch/x86/dts/chromebook_link.dts delete mode 100644 arch/x86/dts/link.dts
arch/x86/cpu/ivybridge/Kconfig +8 -0
@@ -152,6 +152,14 @@ config ENABLE_VMX will be unable to support virtualisation, or it will run very slowly. +config VIDEO_X86 + bool "Enable x86 video driver support" + default y + help + Turn on this option to enable a very simple driver which uses vesa + to discover the video mode and then provides a frame buffer for use + by U-Boot. + endif config CPU_INTEL_SOCKET_RPGA989
arch/x86/dts/Makefile +1 -2
@@ -1,5 +1,4 @@ -dtb-y += link.dtb \ - chromebook_link.dtb \ +dtb-y += chromebook_link.dtb \ crownbay.dtb targets += $(dtb-y)
arch/x86/dts/chromebook_link.dts deleted +0 -1
@@ -1 +0,0 @@ -link.dts
arch/x86/dts/chromebook_link.dts new file +219 -0
219 lines not on this page · raw message
arch/x86/dts/link.dts deleted +0 -219
219 lines not on this page · raw message
board/coreboot/coreboot/Kconfig +2 -2
@@ -13,14 +13,14 @@ comment "coreboot specific options" config SYS_CONFIG_NAME string "Board configuration file" - default "coreboot" + default "chromebook_link" help This option selects the board configuration file in include/configs/ directory to be used to build U-Boot for coreboot. config DEFAULT_DEVICE_TREE string "Board Device Tree Source (dts) file" - default "link" + default "chromebook_link" help This option selects the board Device Tree Source (dts) file in arch/x86/dts/ directory to be used to build U-Boot for coreboot.
configs/coreboot-x86_defconfig +0 -1
@@ -2,4 +2,3 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x01110000" CONFIG_X86=y CONFIG_TARGET_COREBOOT=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="link"
include/configs/chromebook_link.h +0 -1
@@ -39,7 +39,6 @@#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 -#define CONFIG_VIDEO_X86 #define CONFIG_PCI_MEM_BUS 0xe0000000#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
Signature · 1 line
1.8.2.1
PATCH v2 9/12 x86: Make chromebook_link the default board for coreboot
Hi Bin,
Quoted 34 lines · Bin Meng
Change
SYS_CONFIG_NAMEandDEFAULT_DEVICE_TREEtochromebook_linkwhich is currently the only real board officially supported to run U-Boot loaded by coreboot.Note the symbolic link file
chromebook_link.dtsis deleted andlink.dtsis renamed tochromebook_link.dts.To avoid multiple definition of
video_hw_init, theCONFIG_VIDEO_X86define needs to be moved toarch/x86/cpu/ivybridge/Kconfig.Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- New patch to makechromebook_linkthe default board for corebootarch/x86/cpu/ivybridge/Kconfig | 8 ++ arch/x86/dts/Makefile | 3 +- arch/x86/dts/chromebook_link.dts | 220 +++++++++++++++++++++++++++++++++++++- arch/x86/dts/link.dts | 219 ------------------------------------- board/coreboot/coreboot/Kconfig | 4 +- configs/coreboot-x86_defconfig | 1 - include/configs/chromebook_link.h | 1 - 7 files changed, 230 insertions(+), 226 deletions(-) mode change 120000 => 100644 arch/x86/dts/chromebook_link.dts delete mode 100644 arch/x86/dts/link.dtsarch/x86/cpu/ivybridge/Kconfig +0
-0@@ -152,6 +152,14 @@ config ENABLE_VMX will be unable to support virtualisation, or it will run very
arch/x86/cpu/ivybridge/Kconfig config ENABLE_VMX · line 162
Quoted 10 lines
arch/x86/cpu/ivybridge/Kconfig +8
-0slowly. +config VIDEO_X86 + bool "Enable x86 video driver support" + default y + help + Turn on this option to enable a very simple driver which uses vesa + to discover the video mode and then provides a frame buffer for use + by U-Boot. +
I think this should be in drivers/video/Kconfig.
Regards,
Simon
PATCH v2 9/12 x86: Make chromebook_link the default board for coreboot
Hi Simon,
Quoted 39 lines · Simon Glass
Hi Bin,
Quoted 36 lines · Bin Meng
Change
SYS_CONFIG_NAMEandDEFAULT_DEVICE_TREEtochromebook_linkwhich is currently the only real board officially supported to run U-Boot loaded by coreboot.Note the symbolic link file
chromebook_link.dtsis deleted andlink.dtsis renamed tochromebook_link.dts.To avoid multiple definition of
video_hw_init, theCONFIG_VIDEO_X86define needs to be moved toarch/x86/cpu/ivybridge/Kconfig.Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- New patch to makechromebook_linkthe default board for corebootarch/x86/cpu/ivybridge/Kconfig | 8 ++ arch/x86/dts/Makefile | 3 +- arch/x86/dts/chromebook_link.dts | 220 +++++++++++++++++++++++++++++++++++++- arch/x86/dts/link.dts | 219 ------------------------------------- board/coreboot/coreboot/Kconfig | 4 +- configs/coreboot-x86_defconfig | 1 - include/configs/chromebook_link.h | 1 - 7 files changed, 230 insertions(+), 226 deletions(-) mode change 120000 => 100644 arch/x86/dts/chromebook_link.dts delete mode 100644 arch/x86/dts/link.dtsarch/x86/cpu/ivybridge/Kconfig +0
-0@@ -152,6 +152,14 @@ config ENABLE_VMX will be unable to support virtualisation, or it will run very slowly.
Quoted 10 lines
arch/x86/cpu/ivybridge/Kconfig config ENABLE_VMX · line 162
Quoted 8 lines
arch/x86/cpu/ivybridge/Kconfig +8
-0+config VIDEO_X86 + bool "Enable x86 video driver support" + default y + help + Turn on this option to enable a very simple driver which uses vesa + to discover the video mode and then provides a frame buffer for use + by U-Boot. +I think this should be in
drivers/video/Kconfig
OK, will fix.
Regards,
Bin
PATCH v2 10/12 x86: coreboot: Wrap cros_ec initialization
In reply to Bin Mengcros_ec_board_init() should be called only when CONFIG_CROS_EC is enabled.
---
Changes in v2:
- Leave CROS_EC defines unchanged in coreboot.h
board/coreboot/coreboot/coreboot.c | 2 ++ 1 file changed, 2 insertions(+)
board/coreboot/coreboot/coreboot.c +2 -0
@@ -10,8 +10,10 @@int arch_early_init_r (void ) { +#ifdef CONFIG_CROS_EC if (cros_ec_board_init ())return -1 ; +#endif return 0 ; }
Signature · 1 line
1.8.2.1
PATCH v2 10/12 x86: coreboot: Wrap cros_ec initialization
Quoted 5 lines · Bin Meng
cros_ec_board_init()should be called only whenCONFIG_CROS_ECis enabled.Signed-off-by Bin Meng <[email protected]>
Quoted 7 lines
---
Changes in v2:
- LeaveCROS_ECdefines unchanged incoreboot.hboard/coreboot/coreboot/coreboot.c | 2 ++ 1 file changed, 2 insertions(+)
PATCH v2 11/12 x86: coreboot: Configure pci memory regions
In reply to Bin MengConfigure coreboot pci memory regions so that pci device drivers could work correctly.
---
Changes in v2:
- New patch to configure pci memory regions
arch/x86/cpu/coreboot/pci.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-)
arch/x86/cpu/coreboot/pci.c +28 -2
@@ -13,6 +13,8 @@#include <pci.h> #include <asm/pci.h> +DECLARE_GLOBAL_DATA_PTR ; +static void config_pci_bridge (struct pci_controller *hose,pci_dev_t dev,struct pci_config_table *table) {
@@ -35,7 +37,31 @@ void board_pci_setup_hose(struct pci_controller *hose) hose->first_busno =0 ; hose->last_busno =0 ; -pci_set_region (hose->regions +0 ,0x0 ,0x0 ,0xffffffff , +/* PCI memory space */ +pci_set_region (hose->regions +0 , +CONFIG_PCI_MEM_BUS , +CONFIG_PCI_MEM_PHYS , +CONFIG_PCI_MEM_SIZE ,PCI_REGION_MEM ); - hose->region_count =1 ; + +/* PCI IO space */ +pci_set_region (hose->regions +1 , +CONFIG_PCI_IO_BUS , +CONFIG_PCI_IO_PHYS , +CONFIG_PCI_IO_SIZE , +PCI_REGION_IO ); + +pci_set_region (hose->regions +2 , +CONFIG_PCI_PREF_BUS , +CONFIG_PCI_PREF_PHYS , +CONFIG_PCI_PREF_SIZE , +PCI_REGION_PREFETCH ); + +pci_set_region (hose->regions +3 , +0 , +0 , + gd->ram_size, +PCI_REGION_MEM |PCI_REGION_SYS_MEMORY ); + + hose->region_count =4 ; }
Signature · 1 line
1.8.2.1
PATCH v2 11/12 x86: coreboot: Configure pci memory regions
Quoted 5 lines · Bin Meng
Configure coreboot pci memory regions so that pci device drivers could work correctly.
Signed-off-by Bin Meng <[email protected]>
Quoted 7 lines
---
Changes in v2:
- New patch to configure pci memory regionsarch/x86/cpu/coreboot/pci.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-)
At some point much of this code could go into arch/x86/lib/pci_type1.c or similar since ivybridge is common. Let's see how things land first.
Regards,
Simon
PATCH v2 12/12 x86: Update REAME.x86 for coreboot support
In reply to Bin MengUpdate README.x86 to include new build instructions for U-Boot as the coreboot payload and testing considerations with coreboot.
---
Changes in v2:
- New patch to update REAME.x86 for coreboot support
doc/README.x86 | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
doc/README.x86 +35 -0
@@ -32,6 +32,21 @@ on other architectures, like below: $ make coreboot-x86_defconfig $ make all +Note this default configuration will build a U-Boot payload for the Link board. +To build a coreboot payload aginst another board, you can change the build +configuration during the 'make menuconfig' process. + +x86 architecture ---> + ... + (chromebook_link) Board configuration file + (chromebook_link) Board Device Tree Source (dts) file + (0x19200000) Board specific Cache-As-RAM (CAR) address + (0x4000) Board specific Cache-As-RAM (CAR) size + +Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' +to point to a new board. You can also change the Cache-As-RAM (CAR) related +settings here if the default values do not fit your new board. + Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a little bit tricky, as generally it requires several binary blobs which are not shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
@@ -93,6 +108,26 @@ Now you can build U-Boot and obtaim u-boot.rom $ make crownbay_defconfig $ make all +Test with coreboot +------------------ +For testing U-Boot as the coreboot payload, there are things that need be paid +attention to. coreboot supports loading an ELF executable and a 32-bit plain +binary, as well as other supported payloads. With the default configuration, +U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the +generated u-boot-dtb.in needs to be packaged by the cbfstool utility (a tool +provided by coreboot) manually as coreboot's 'make menuconfig' does not provide +this capability yet. The command is as follows: + +# in the coreboot root directory +$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \ + -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015 + +Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the +symbol address of _start (in arch/x86/cpu/start.S). + +If you want to use ELF as the coreboot payload, change U-Boot configuration to +use CONFIG_OF_EMBED. + CPU Microcode ------------- Modern CPU usually requires a special bit stream called microcode [5] to be
Signature · 1 line
1.8.2.1
PATCH v2 12/12 x86: Update REAME.x86 for coreboot support
Hi Bin,
Quoted 5 lines · Bin Meng
Update README.x86 to include new build instructions for U-Boot as the coreboot payload and testing considerations with coreboot.
Signed-off-by Bin Meng <[email protected]>
Quoted 7 lines
---
Changes in v2:
- New patch to update REAME.x86 for coreboot supportdoc/README.x86 | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
Looks good.
What method are you using to boot a kernel? I'm wondering how we document use cases like booting Ubuntu, booting from different boot devices, etc. Mostly this is zImage but we could link to x86-fit-boot.txt also.
There is a syslinux approach used by many ARM boards now - e.g. see rpi.h which includes config_distro_defaults.h. Should we enable this for x86 too?
Regards,
Simon
PATCH v2 12/12 x86: Update REAME.x86 for coreboot support
Hi Simon,
Quoted 13 lines · Simon Glass
Hi Bin,
Quoted 10 lines · Bin Meng
Update README.x86 to include new build instructions for U-Boot as the coreboot payload and testing considerations with coreboot.
Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- New patch to update REAME.x86 for coreboot support
Quoted 6 lines
Quoted 2 lines
doc/README.x86 | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)Looks good.
Acked-by Simon Glass <[email protected]>
Thanks for the fast response as always! Sorry, but I have to respin this patch due to I've found 3 typos (REAME.x86, aginst, u-boot-dtb.in) myself this morning. I must have had my brain cells tired last night :-<
Quoted 4 lines
What method are you using to boot a kernel? I'm wondering how we document use cases like booting Ubuntu, booting from different boot devices, etc. Mostly this is zImage but we could link to x86-fit-boot.txt also.
I am using zboot to boot a kernel bzImage with initramfs and nfs mounted as root. I have not tried to boot any distro out there.
Quoted 3 lines
There is a syslinux approach used by many ARM boards now - e.g. see
rpi.hwhich includesconfig_distro_defaults.h. Should we enable this for x86 too?
I will have a look. If we consider supporting syslinux, how about other bootloaders like grub?
Regards,
Bin
PATCH v2 12/12 x86: Update REAME.x86 for coreboot support
Hi Bin,
Quoted 36 lines · Bin Meng
Hi Simon,
Quoted 13 lines · Simon Glass
Hi Bin,
Quoted 10 lines · Bin Meng
Update README.x86 to include new build instructions for U-Boot as the coreboot payload and testing considerations with coreboot.
Signed-off-by Bin Meng <[email protected]>---
Changes in v2:
- New patch to update REAME.x86 for coreboot supportQuoted 6 lines
Quoted 2 lines
doc/README.x86 | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)Looks good.
Acked-by Simon Glass <[email protected]>Thanks for the fast response as always! Sorry, but I have to respin this patch due to I've found 3 typos (REAME.x86, aginst, u-boot-dtb.in) myself this morning. I must have had my brain cells tired last night :-<
Quoted 4 lines
What method are you using to boot a kernel? I'm wondering how we document use cases like booting Ubuntu, booting from different boot devices, etc. Mostly this is zImage but we could link to x86-fit-boot.txt also.
I am using zboot to boot a kernel bzImage with initramfs and nfs mounted as root. I have not tried to boot any distro out there.
Quoted 6 lines
Quoted 3 lines
There is a syslinux approach used by many ARM boards now - e.g. see
rpi.hwhich includesconfig_distro_defaults.h. Should we enable this for x86 too?I will have a look. If we consider supporting syslinux, how about other bootloaders like grub?
Could do, I'm not sure how to run it, but I suppose it's not that hard.
Regards,
Simon