ACPI / LPSS: Always disable I2C host controllers
PATCH 1/2 ACPI / LPSS: Always disable I2C host controllers
On Baytrail and Braswell the BIOS might leave the I2C host controllers enabled, probably because it uses them for its on purposes. This is fine in normal cases because the I2C driver will disable the hardware when it is probed anyway.
However, in case of suspend to disk it is different story. If the driver happens to be compiled as module the boot kernel never loads the driver thus leaving host controllers enabled upon loading the hibernation image.
The I2C host controller interrupt mask register has default value of 0x8ff, in other words it has most of the interrupts unmasked. When combined with the fact that the host controller is enabled, the driver immediately starts getting interrupts even before its resume hook is called (once IO-APIC is resumed). Since the driver is not prepared for this it will crash the kernel due to NULL pointer derefence because dev->msgs is NULL.
Unfortunately we were not able to get full backtrace to from the console which could be reproduced here.
In order to fix this even when the driver is compiled as module, we disable the I2C host controllers in byt_i2c_setup() before devices are created.
--- drivers/acpi/acpi_lpss.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/acpi/acpi_lpss.c +4 -0
@@ -105,6 +105,8 @@ static void lpss_uart_setup(struct lpss_private_data *pdata) } } +#define LPSS_I2C_ENABLE 0x6c +static void byt_i2c_setup (struct lpss_private_data *pdata) {unsigned int offset;
@@ -117,6 +119,8 @@ static void byt_i2c_setup(struct lpss_private_data *pdata)if (readl (pdata->mmio_base + pdata->dev_desc->prv_offset)) pdata->fixed_clk_rate =133000000 ; + +writel (0 , pdata->mmio_base +LPSS_I2C_ENABLE ); }static struct lpss_device_desc lpt_dev_desc = {
Signature · 1 line
2.1.4
PATCH 2/2 ACPI / LPSS: Deassert resets for SPI host controllers on Braswell
On some Braswell systems BIOS leaves resets for SPI host controllers active. This prevents the SPI driver from transferring messages on wire.
Fix this in similar way that we do for I2C already by deasserting resets for the SPI host controllers.
--- drivers/acpi/acpi_lpss.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-)
drivers/acpi/acpi_lpss.c +15 -4
@@ -105,9 +105,7 @@ static void lpss_uart_setup(struct lpss_private_data *pdata) } } -#define LPSS_I2C_ENABLE 0x6c - -static void byt_i2c_setup (struct lpss_private_data *pdata) +static void lpss_deassert_reset (struct lpss_private_data *pdata) {unsigned int offset;u32 val;
@@ -116,6 +114,13 @@ static void byt_i2c_setup(struct lpss_private_data *pdata) val =readl (pdata->mmio_base + offset); val |=LPSS_RESETS_RESET_APB |LPSS_RESETS_RESET_FUNC ;writel (val, pdata->mmio_base + offset); +} + +#define LPSS_I2C_ENABLE 0x6c + +static void byt_i2c_setup (struct lpss_private_data *pdata) +{ +lpss_deassert_reset (pdata);if (readl (pdata->mmio_base + pdata->dev_desc->prv_offset)) pdata->fixed_clk_rate =133000000 ;
@@ -170,6 +175,12 @@ static struct lpss_device_desc byt_i2c_dev_desc = { .setup = byt_i2c_setup, }; +static struct lpss_device_desc bsw_spi_dev_desc = { + .flags =LPSS_CLK |LPSS_CLK_GATE |LPSS_CLK_DIVIDER |LPSS_SAVE_CTX , + .prv_offset =0x400 , + .setup = lpss_deassert_reset, +}; +#else #define LPSS_ADDR (desc) (0UL)
@@ -202,7 +213,7 @@ static const struct acpi_device_id acpi_lpss_device_ids[] = {/* Braswell LPSS devices */ { "80862288", LPSS_ADDR(byt_pwm_dev_desc) }, { "8086228A", LPSS_ADDR(byt_uart_dev_desc) }, - { "8086228E", LPSS_ADDR(byt_spi_dev_desc) }, + { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) }, { "INT3430", LPSS_ADDR(lpt_dev_desc) },
Signature · 1 line
2.1.4
Re: [PATCH 2/2] ACPI / LPSS: Deassert resets for SPI host controllers on Braswell
Quoted 8 lines · Mika Westerberg
On some Braswell systems BIOS leaves resets for SPI host controllers active. This prevents the SPI driver from transferring messages on wire.
Fix this in similar way that we do for I2C already by deasserting resets for the SPI host controllers.
Reported-by Yang A Fang <[email protected]>Signed-off-by Mika Westerberg <[email protected]>
OK, so these two would need to go into "stable" I suppose?
What "stable" series we need them to go into?
Quoted 56 lines
--- drivers/acpi/acpi_lpss.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-)drivers/acpi/acpi_lpss.c +15
-4@@ -105,9 +105,7 @@ static void lpss_uart_setup(struct lpss_private_data *pdata) } } -#define LPSS_I2C_ENABLE 0x6c - -static void byt_i2c_setup (struct lpss_private_data *pdata) +static void lpss_deassert_reset (struct lpss_private_data *pdata) {unsigned int offset;u32 val;@@ -116,6 +114,13 @@ static void byt_i2c_setup(struct lpss_private_data *pdata) val =readl (pdata->mmio_base + offset); val |=LPSS_RESETS_RESET_APB |LPSS_RESETS_RESET_FUNC ;writel (val, pdata->mmio_base + offset); +} + +#define LPSS_I2C_ENABLE 0x6c + +static void byt_i2c_setup (struct lpss_private_data *pdata) +{ +lpss_deassert_reset (pdata);if (readl (pdata->mmio_base + pdata->dev_desc->prv_offset)) pdata->fixed_clk_rate =133000000 ;@@ -170,6 +175,12 @@ static struct lpss_device_desc byt_i2c_dev_desc = { .setup = byt_i2c_setup, }; +static struct lpss_device_desc bsw_spi_dev_desc = { + .flags =LPSS_CLK |LPSS_CLK_GATE |LPSS_CLK_DIVIDER |LPSS_SAVE_CTX , + .prv_offset =0x400 , + .setup = lpss_deassert_reset, +}; +#else #define LPSS_ADDR (desc) (0UL)@@ -202,7 +213,7 @@ static const struct acpi_device_id acpi_lpss_device_ids[] = {/* Braswell LPSS devices */ { "80862288", LPSS_ADDR(byt_pwm_dev_desc) }, { "8086228A", LPSS_ADDR(byt_uart_dev_desc) }, - { "8086228E", LPSS_ADDR(byt_spi_dev_desc) }, + { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) }, { "INT3430", LPSS_ADDR(lpt_dev_desc) },
Signature · 2 lines
I speak only for myself. Rafael J. Wysocki, Intel Open Source Technology Center.
Re: [PATCH 2/2] ACPI / LPSS: Deassert resets for SPI host controllers on Braswell
Quoted 11 lines · Rafael J. Wysocki
Quoted 8 lines · Mika Westerberg
On some Braswell systems BIOS leaves resets for SPI host controllers active. This prevents the SPI driver from transferring messages on wire.
Fix this in similar way that we do for I2C already by deasserting resets for the SPI host controllers.
Reported-by Yang A Fang <[email protected]>Signed-off-by Mika Westerberg <[email protected]>OK, so these two would need to go into "stable" I suppose?
Yes, if possible.
Quoted 1 line
What "stable" series we need them to go into?
Braswell support was added in v3.17 so I think from v3.17 onwards.
Quoted 2 lines · Mika Westerberg
On Baytrail and Braswell the BIOS might leave the I2C host controllers enabled, probably because it uses them for its on purposes. This is fine in
^^^^^^^^^^^
As pointed out by Graham Whaley, it should say "own purposes".
Rafael, do you want me to resend this patch?
Quoted 7 lines · Mika Westerberg
Quoted 2 lines · Mika Westerberg
On Baytrail and Braswell the BIOS might leave the I2C host controllers enabled, probably because it uses them for its on purposes. This is fine in
^^^^^^^^^^^As pointed out by Graham Whaley, it should say "own purposes".
Rafael, do you want me to resend this patch?
No need if the code changes are correct, I can fix up the changelog. :-)
Signature · 2 lines
I speak only for myself. Rafael J. Wysocki, Intel Open Source Technology Center.