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drm/i915/audio: add codec wakeup override enabled/disable callback

PATCH Superseded [email protected] 5 participants 8 messages Apr 29, 2015 – May 4, 2015

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v3 of 4 Superseded Latest is v4 →

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#0 lore raw

PATCH v3 1/2 drm/i915/audio: add codec wakeup override enabled/disable callback

From: "Lu, Han" <[email protected]>

Add support for enabling codec wakeup override signal to allow re-enumeration of the controller on SKL after resume from low power state.

v3 by Jani: Simplify to only support toggling the appropriate chicken bit.

drivers/gpu/drm/i915/i915_reg.h +3 -0
index 36805b6..435c372 100644
@@ -6881,6 +6881,9 @@ enum skl_disp_power_wells {
 #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
 
+#define HSW_AUD_CHICKENBIT			0x65f10
+#define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
+
 /* HSW Power Wells */
 #define HSW_PWR_WELL_BIOS			0x45400 /* CTL1 */
 #define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */
drivers/gpu/drm/i915/intel_audio.c +27 -0
index f72e93a..ceb2328 100644
@@ -474,6 +474,32 @@ static void i915_audio_component_put_power(struct device *dev)
 	intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
 }
 
+static void i915_audio_component_codec_wake_override(struct device *dev,
+						     bool enable)
+{
+	struct drm_i915_private *dev_priv = dev_to_i915(dev);
+	u32 tmp;
+
+	if (!IS_SKYLAKE(dev_priv))
+		return;
+
+	/*
+	 * Enable/disable generating the codec wake signal, overriding the
+	 * internal logic to generate the codec wake to controller.
+	 */
+	tmp = I915_READ(HSW_AUD_CHICKENBIT);
+	tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
+	I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+	usleep_range(1000, 1500);
+
+	if (enable) {
+		tmp = I915_READ(HSW_AUD_CHICKENBIT);
+		tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
+		I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+		usleep_range(1000, 1500);
+	}
+}
+
 /* Get CDCLK in kHz  */
 static int i915_audio_component_get_cdclk_freq(struct device *dev)
 {
@@ -495,6 +521,7 @@ static const struct i915_audio_component_ops i915_audio_component_ops = {
 	.owner		= THIS_MODULE,
 	.get_power	= i915_audio_component_get_power,
 	.put_power	= i915_audio_component_put_power,
+	.codec_wake_override = i915_audio_component_codec_wake_override,
 	.get_cdclk_freq	= i915_audio_component_get_cdclk_freq,
 };
 
include/drm/i915_component.h +1 -0
index 3e2f22e..c9a8b64 100644
@@ -31,6 +31,7 @@ struct i915_audio_component {
 		struct module *owner;
 		void (*get_power)(struct device *);
 		void (*put_power)(struct device *);
+		void (*codec_wake_override)(struct device *, bool enable);
 		int (*get_cdclk_freq)(struct device *);
 	} *ops;
 };
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#1 lore raw

PATCH v3 2/2 ALSA:hda - reset display codec when power on

From: "Lu, Han" <[email protected]>

In SKL, HDMI/DP codec and PCH HD Audio Controller are in different power wells, so it's necessary to reset display audio codecs when power well on, otherwise display audio codecs will disappear when resume from low power state. Reset steps when power on:

    enable codec wakeup -> azx_init_chip() -> disable codec wakeup

The callback for codec wakeup enable/disable is in drivers/gpu/drm/i915/.

sound/pci/hda/hda_i915.c +21 -0
index 3052a2b..fe4f979a 100644
@@ -33,6 +33,27 @@
 #define AZX_REG_EM4			0x100c
 #define AZX_REG_EM5			0x1010
 
+int hda_set_codec_wakeup(struct hda_intel *hda, bool enable)
+{
+	struct i915_audio_component *acomp = &hda->audio_component;
+
+	if (!acomp->ops)
+		return -ENODEV;
+
+	if (!acomp->ops->codec_wake_override) {
+		dev_warn(&hda->chip.pci->dev,
+			"Invalid codec wake callback\n");
+		return 0;
+	}
+
+	dev_dbg(&hda->chip.pci->dev, "%s codec wakeup\n",
+		enable ? "enable" : "disable");
+
+	acomp->ops->codec_wake_override(acomp->dev, enable);
+
+	return 0;
+}
+
 int hda_display_power(struct hda_intel *hda, bool enable)
 {
 	struct i915_audio_component *acomp = &hda->audio_component;
sound/pci/hda/hda_intel.c +17 -3
index 34040d2..f4ed12d 100644
@@ -491,6 +491,17 @@ static void azx_init_pci(struct azx *chip)
         }
 }
 
+static void hda_intel_init_chip(struct azx *chip, bool full_reset)
+{
+	struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
+
+	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
+		hda_set_codec_wakeup(hda, true);
+	azx_init_chip(chip, full_reset);
+	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
+		hda_set_codec_wakeup(hda, false);
+}
+
 /* calculate runtime delay from LPIB */
 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
 				   unsigned int pos)
@@ -827,7 +838,7 @@ static int azx_resume(struct device *dev)
 		return -EIO;
 	azx_init_pci(chip);
 
-	azx_init_chip(chip, true);
+	hda_intel_init_chip(chip, true);
 
 	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
 	return 0;
@@ -888,13 +899,16 @@ static int azx_runtime_resume(struct device *dev)
 	if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
 		hda_display_power(hda, true);
 		haswell_set_bclk(hda);
+		/* toggle codec wakeup bit for STATESTS read */
+		hda_set_codec_wakeup(hda, true);
+		hda_set_codec_wakeup(hda, false);
 	}
 
 	/* Read STATESTS before controller reset */
 	status = azx_readw(chip, STATESTS);
 
 	azx_init_pci(chip);
-	azx_init_chip(chip, true);
+	hda_intel_init_chip(chip, true);
 
 	bus = chip->bus;
 	if (status && bus) {
@@ -1588,7 +1602,7 @@ static int azx_first_init(struct azx *chip)
 		haswell_set_bclk(hda);
 	}
 
-	azx_init_chip(chip, (probe_only[dev] & 2) == 0);
+	hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
 
 	/* codec detection */
 	if (!chip->codec_mask) {
sound/pci/hda/hda_intel.h +5 -0
index d5231f7..5d2bb07 100644
@@ -48,11 +48,16 @@ struct hda_intel {
 };
 
 #ifdef CONFIG_SND_HDA_I915
+int hda_set_codec_wakeup(struct hda_intel *hda, bool enable);
 int hda_display_power(struct hda_intel *hda, bool enable);
 void haswell_set_bclk(struct hda_intel *hda);
 int hda_i915_init(struct hda_intel *hda);
 int hda_i915_exit(struct hda_intel *hda);
 #else
+static inline int hda_set_codec_wakeup(struct hda_intel *hda, bool enable)
+{
+	return 0;
+}
 static inline int hda_display_power(struct hda_intel *hda, bool enable)
 {
 	return 0;
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Tested-by on v3 2/2
#2 lore raw

Re: [PATCH-V3 2/2] ALSA:hda - reset display codec when power on

Task id: 6287 -------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied

PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                                  316/316              316/316
IVB                                  264/264              264/264

BYT -5 227/227 222/227
BDW 318/318 318/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*BYT igt@gem_dummy_reloc_loop@render FAIL(1)PASS(10) TIMEOUT(1)PASS(1)
*BYT igt@gem_exec_parse@bitmasks FAIL(1)PASS(5) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x
BYT igt@gem_pipe_control_store_loop@fresh-buffer FAIL(1)TIMEOUT(5)PASS(6) TIMEOUT(1)PASS(1)
*BYT igt@gem_tiled_pread FAIL(1)PASS(3) DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:check_crtc_state[i915]]*ERROR*mismatch_in_has_infoframe(expected#,found#)@mismatch in has_infoframe .* found WARNING:at_drivers/gpu/drm/i915/intel_display.c:#check_crtc_state[i915]()@WARNING:.* at .* check_crtc_state+0x
*BYT igt@gem_userptr_blits@forked-unsync-multifd-normal FAIL(1)PASS(2) NO_RESULT(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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#3 lore raw
In reply to [email protected]

At Wed, 29 Apr 2015 17:49:25 +0800,

Quoted 10 lines · [email protected] wrote:

From: "Lu, Han" <[email protected]>

Add support for enabling codec wakeup override signal to allow re-enumeration of the controller on SKL after resume from low power state.

v3 by Jani: Simplify to only support toggling the appropriate chicken bit.

The patch series look OK to me.
But who will merge these?

I can merge these two patches to a branch so that it can be shared between sound and i915 trees. Of course, only when I get ack about the first patch.

thanks,

Takashi

Quoted 75 lines
drivers/gpu/drm/i915/i915_reg.h +3 -0
index 36805b6..435c372 100644
@@ -6881,6 +6881,9 @@ enum skl_disp_power_wells {
 #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
 
+#define HSW_AUD_CHICKENBIT			0x65f10
+#define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
+
 /* HSW Power Wells */
 #define HSW_PWR_WELL_BIOS			0x45400 /* CTL1 */
 #define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */
drivers/gpu/drm/i915/intel_audio.c +27 -0
index f72e93a..ceb2328 100644
@@ -474,6 +474,32 @@ static void i915_audio_component_put_power(struct device *dev)
 	intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO);
 }
 
+static void i915_audio_component_codec_wake_override(struct device *dev,
+						     bool enable)
+{
+	struct drm_i915_private *dev_priv = dev_to_i915(dev);
+	u32 tmp;
+
+	if (!IS_SKYLAKE(dev_priv))
+		return;
+
+	/*
+	 * Enable/disable generating the codec wake signal, overriding the
+	 * internal logic to generate the codec wake to controller.
+	 */
+	tmp = I915_READ(HSW_AUD_CHICKENBIT);
+	tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
+	I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+	usleep_range(1000, 1500);
+
+	if (enable) {
+		tmp = I915_READ(HSW_AUD_CHICKENBIT);
+		tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
+		I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+		usleep_range(1000, 1500);
+	}
+}
+
 /* Get CDCLK in kHz  */
 static int i915_audio_component_get_cdclk_freq(struct device *dev)
 {
@@ -495,6 +521,7 @@ static const struct i915_audio_component_ops i915_audio_component_ops = {
 	.owner		= THIS_MODULE,
 	.get_power	= i915_audio_component_get_power,
 	.put_power	= i915_audio_component_put_power,
+	.codec_wake_override = i915_audio_component_codec_wake_override,
 	.get_cdclk_freq	= i915_audio_component_get_cdclk_freq,
 };
 
include/drm/i915_component.h +1 -0
index 3e2f22e..c9a8b64 100644
@@ -31,6 +31,7 @@ struct i915_audio_component {
 		struct module *owner;
 		void (*get_power)(struct device *);
 		void (*put_power)(struct device *);
+		void (*codec_wake_override)(struct device *, bool enable);
 		int (*get_cdclk_freq)(struct device *);
 	} *ops;
 };
Signature · 1 line
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author
#4 lore raw

Hi Takashi,

Our target is to apply the patches into intel-drm-nightly tree, It will be great if you can help merge the patches into your tree. However I get a negative test result on BYT platform auto test, I'll confirm if it's caused by my patches, so please do not merge now and I'll give you feedback ASAP. Thanks.

Hi Jani,

Is it OK to merge both patches onto Takashi's tree? In case you may would like to merge the patches also, I'm not sure if there will be conflict or something...

BR,
Han Lu

Quoted 98 lines

-----Original Message-----
From: Takashi Iwai [mailto:[email protected]]
Sent: Thursday, April 30, 2015 10:21 PM
To: Lu, Han
Cc: Vetter, Daniel; Nikula, Jani; Yang, Libin; Lin, Mengdong; intel- [email protected]
Subject: Re: [PATCH-V3 1/2] drm/i915/audio: add codec wakeup override enabled/disable callback

At Wed, 29 Apr 2015 17:49:25 +0800,

Quoted 5 lines · [email protected] wrote:

From: "Lu, Han" <[email protected]>

Add support for enabling codec wakeup override signal to allow re-enumeration of the controller on SKL after resume from low power

state.

Quoted 5 lines

v3 by Jani: Simplify to only support toggling the appropriate chicken bit.

The patch series look OK to me.
But who will merge these?

I can merge these two patches to a branch so that it can be shared between sound and i915 trees. Of course, only when I get ack about the first patch.

thanks,

Takashi

drivers/gpu/drm/i915/intel_audio.c static void

Quoted 21 lines
(quoted diff) +0 -0

b/drivers/gpu/drm/i915/i915_reg.h index 36805b6..435c372 100644

drivers/gpu/drm/i915/i915_reg.h +3 -0
@@ -6881,6 +6881,9 @@ enum skl_disp_power_wells {
 #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
 
+#define HSW_AUD_CHICKENBIT			0x65f10
+#define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
+
 /* HSW Power Wells */
 #define HSW_PWR_WELL_BIOS			0x45400 /* CTL1 */
 #define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */
drivers/gpu/drm/i915/intel_audio.c +0 -0
index f72e93a..ceb2328 100644
@@ -474,6 +474,32 @@ static void

i915_audio_component_put_power(struct device *dev)

drivers/gpu/drm/i915/intel_audio.c static void · line 474

Quoted 1 line
drivers/gpu/drm/i915/intel_audio.c +0 -0
 	intel_display_power_put(dev_to_i915(dev),

POWER_DOMAIN_AUDIO); }

drivers/gpu/drm/i915/intel_audio.c static void · line 475

Quoted 2 lines
drivers/gpu/drm/i915/intel_audio.c +1 -0
+static void i915_audio_component_codec_wake_override(struct device

*dev,

drivers/gpu/drm/i915/intel_audio.c static const struct i915_audio_component_ops

Quoted 28 lines
drivers/gpu/drm/i915/intel_audio.c +25 -0
+						     bool enable)
+{
+	struct drm_i915_private *dev_priv = dev_to_i915(dev);
+	u32 tmp;
+
+	if (!IS_SKYLAKE(dev_priv))
+		return;
+
+	/*
+	 * Enable/disable generating the codec wake signal, overriding the
+	 * internal logic to generate the codec wake to controller.
+	 */
+	tmp = I915_READ(HSW_AUD_CHICKENBIT);
+	tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
+	I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+	usleep_range(1000, 1500);
+
+	if (enable) {
+		tmp = I915_READ(HSW_AUD_CHICKENBIT);
+		tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
+		I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+		usleep_range(1000, 1500);
+	}
+}
+
 /* Get CDCLK in kHz  */
 static int i915_audio_component_get_cdclk_freq(struct device *dev)  {
@@ -495,6 +521,7 @@ static const struct i915_audio_component_ops

i915_audio_component_ops = {

drivers/gpu/drm/i915/intel_audio.c static const struct i915_audio_component_ops i915_audio_component_ops = {

Quoted 4 lines
drivers/gpu/drm/i915/intel_audio.c +1 -0
 	.owner		= THIS_MODULE,
 	.get_power	= i915_audio_component_get_power,
 	.put_power	= i915_audio_component_put_power,
+	.codec_wake_override =

i915_audio_component_codec_wake_override,

Quoted 3 lines
drivers/gpu/drm/i915/intel_audio.c +0 -0
 	.get_cdclk_freq	= i915_audio_component_get_cdclk_freq,
 };
 
Quoted 15 lines
Quoted 13 lines
(quoted diff) +0 -0

b/include/drm/i915_component.h index 3e2f22e..c9a8b64 100644

include/drm/i915_component.h +1 -1
@@ -31,6 +31,7 @@ struct i915_audio_component {
 		struct module *owner;
 		void (*get_power)(struct device *);
 		void (*put_power)(struct device *);
+		void (*codec_wake_override)(struct device *, bool enable);
 		int (*get_cdclk_freq)(struct device *);
 	} *ops;
 };
--
Quoted 2 lines

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#5 lore raw
Quoted 7 lines · Han

Hi Takashi,

Our target is to apply the patches into intel-drm-nightly tree, It will be great if you can help merge the patches into your tree. However I get a negative test result on BYT platform auto test, I'll confirm if it's caused by my patches, so please do not merge now and I'll give you feedback ASAP. Thanks.

The automated test failure looks like noise from the test system, can be ignored.

Quoted 3 lines

Is it OK to merge both patches onto Takashi's tree? In case you may would like to merge the patches also, I'm not sure if there will be conflict or something...

I think it's okay to merge through Takashi's tree.

However drm-intel-nightly (a mashup of all our branches and some others) currently doesn't incorporate Takashi's for-next branch because of [1]. We can add it back once that gets resolved.

BR,
Jani.

[1] http://mid.gmane.org/[email protected]

Quoted 117 lines

BR,
Han Lu

Quoted 113 lines

-----Original Message-----
From: Takashi Iwai [mailto:[email protected]]
Sent: Thursday, April 30, 2015 10:21 PM
To: Lu, Han
Cc: Vetter, Daniel; Nikula, Jani; Yang, Libin; Lin, Mengdong; intel- [email protected]
Subject: Re: [PATCH-V3 1/2] drm/i915/audio: add codec wakeup override enabled/disable callback

At Wed, 29 Apr 2015 17:49:25 +0800,

Quoted 5 lines · [email protected] wrote:

From: "Lu, Han" <[email protected]>

Add support for enabling codec wakeup override signal to allow re-enumeration of the controller on SKL after resume from low power

state.

Quoted 5 lines

v3 by Jani: Simplify to only support toggling the appropriate chicken bit.

The patch series look OK to me.
But who will merge these?

I can merge these two patches to a branch so that it can be shared between sound and i915 trees. Of course, only when I get ack about the first patch.

thanks,

Takashi

drivers/gpu/drm/i915/intel_audio.c static void

Quoted 21 lines
(quoted diff) +0 -0

b/drivers/gpu/drm/i915/i915_reg.h index 36805b6..435c372 100644

drivers/gpu/drm/i915/i915_reg.h +3 -0
@@ -6881,6 +6881,9 @@ enum skl_disp_power_wells {
 #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
 
+#define HSW_AUD_CHICKENBIT			0x65f10
+#define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
+
 /* HSW Power Wells */
 #define HSW_PWR_WELL_BIOS			0x45400 /* CTL1 */
 #define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */
drivers/gpu/drm/i915/intel_audio.c +0 -0
index f72e93a..ceb2328 100644
@@ -474,6 +474,32 @@ static void

i915_audio_component_put_power(struct device *dev)

drivers/gpu/drm/i915/intel_audio.c static void · line 474

Quoted 1 line
drivers/gpu/drm/i915/intel_audio.c +0 -0
 	intel_display_power_put(dev_to_i915(dev),

POWER_DOMAIN_AUDIO); }

drivers/gpu/drm/i915/intel_audio.c static void · line 475

Quoted 2 lines
drivers/gpu/drm/i915/intel_audio.c +1 -0
+static void i915_audio_component_codec_wake_override(struct device

*dev,

drivers/gpu/drm/i915/intel_audio.c static const struct i915_audio_component_ops

Quoted 28 lines
drivers/gpu/drm/i915/intel_audio.c +25 -0
+						     bool enable)
+{
+	struct drm_i915_private *dev_priv = dev_to_i915(dev);
+	u32 tmp;
+
+	if (!IS_SKYLAKE(dev_priv))
+		return;
+
+	/*
+	 * Enable/disable generating the codec wake signal, overriding the
+	 * internal logic to generate the codec wake to controller.
+	 */
+	tmp = I915_READ(HSW_AUD_CHICKENBIT);
+	tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
+	I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+	usleep_range(1000, 1500);
+
+	if (enable) {
+		tmp = I915_READ(HSW_AUD_CHICKENBIT);
+		tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
+		I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+		usleep_range(1000, 1500);
+	}
+}
+
 /* Get CDCLK in kHz  */
 static int i915_audio_component_get_cdclk_freq(struct device *dev)  {
@@ -495,6 +521,7 @@ static const struct i915_audio_component_ops

i915_audio_component_ops = {

drivers/gpu/drm/i915/intel_audio.c static const struct i915_audio_component_ops i915_audio_component_ops = {

Quoted 4 lines
drivers/gpu/drm/i915/intel_audio.c +1 -0
 	.owner		= THIS_MODULE,
 	.get_power	= i915_audio_component_get_power,
 	.put_power	= i915_audio_component_put_power,
+	.codec_wake_override =

i915_audio_component_codec_wake_override,

Quoted 18 lines
drivers/gpu/drm/i915/intel_audio.c +0 -0
 	.get_cdclk_freq	= i915_audio_component_get_cdclk_freq,
 };
 
(quoted diff) +0 -0

b/include/drm/i915_component.h index 3e2f22e..c9a8b64 100644

include/drm/i915_component.h +1 -1
@@ -31,6 +31,7 @@ struct i915_audio_component {
 		struct module *owner;
 		void (*get_power)(struct device *);
 		void (*put_power)(struct device *);
+		void (*codec_wake_override)(struct device *, bool enable);
 		int (*get_cdclk_freq)(struct device *);
 	} *ops;
 };
--

1.9.1

Signature · 5 lines
Jani Nikula, Intel Open Source Technology Center
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#6 lore raw

Hi Jani,

Thanks for review.

Hi Takashi,

Should we re-send the patch to ALSA mailing list?

Quoted 33 lines

-----Original Message-----
From: Nikula, Jani
Sent: Monday, May 04, 2015 3:49 PM
To: Lu, Han; Takashi Iwai
Cc: Vetter, Daniel; Yang, Libin; Lin, Mengdong; intel- [email protected]
Subject: RE: [PATCH-V3 1/2] drm/i915/audio: add codec wakeup override enabled/disable callback

Quoted 7 lines · Han

Hi Takashi,

Our target is to apply the patches into intel-drm-nightly tree, It will be great if you can help merge the patches into your tree. However I get a negative test result on BYT platform auto test, I'll confirm if it's caused by my patches, so please do not merge now and I'll give you feedback ASAP. Thanks.

The automated test failure looks like noise from the test system, can be
ignored.

Quoted 3 lines

Is it OK to merge both patches onto Takashi's tree? In case you may would like to merge the patches also, I'm not sure if there will be conflict or something...

I think it's okay to merge through Takashi's tree.

However drm-intel-nightly (a mashup of all our branches and some others)
currently doesn't incorporate Takashi's for-next branch because of [1]. We can add it back once that gets resolved.

Quoted 5 lines

BR,
Jani.

[1] http://mid.gmane.org/[email protected]

The bug has been fixed. Suppose the patch will be merged into for-next soon.

Regards,
Libin
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#7 lore raw
In reply to Jani Nikula

At Mon, 04 May 2015 10:49:15 +0300,

Quoted 17 lines · Jani Nikula
Quoted 7 lines · Han

Hi Takashi,

Our target is to apply the patches into intel-drm-nightly tree, It will be great if you can help merge the patches into your tree. However I get a negative test result on BYT platform auto test, I'll confirm if it's caused by my patches, so please do not merge now and I'll give you feedback ASAP. Thanks.

The automated test failure looks like noise from the test system, can be ignored.

Quoted 3 lines

Is it OK to merge both patches onto Takashi's tree? In case you may would like to merge the patches also, I'm not sure if there will be conflict or something...

Quoted 5 lines

I think it's okay to merge through Takashi's tree.

However drm-intel-nightly (a mashup of all our branches and some others) currently doesn't incorporate Takashi's for-next branch because of [1]. We can add it back once that gets resolved.

OK, now I applied these two patches to for-next branch.

Thanks!

Takashi

Quoted 111 lines

BR,
Jani.

[1] http://mid.gmane.org/[email protected]

Quoted 102 lines

BR,
Han Lu

Quoted 98 lines

-----Original Message-----
From: Takashi Iwai [mailto:[email protected]]
Sent: Thursday, April 30, 2015 10:21 PM
To: Lu, Han
Cc: Vetter, Daniel; Nikula, Jani; Yang, Libin; Lin, Mengdong; intel- [email protected]
Subject: Re: [PATCH-V3 1/2] drm/i915/audio: add codec wakeup override enabled/disable callback

At Wed, 29 Apr 2015 17:49:25 +0800,

Quoted 5 lines · [email protected] wrote:

From: "Lu, Han" <[email protected]>

Add support for enabling codec wakeup override signal to allow re-enumeration of the controller on SKL after resume from low power

state.

Quoted 5 lines

v3 by Jani: Simplify to only support toggling the appropriate chicken bit.

The patch series look OK to me.
But who will merge these?

I can merge these two patches to a branch so that it can be shared between sound and i915 trees. Of course, only when I get ack about the first patch.

thanks,

Takashi

drivers/gpu/drm/i915/intel_audio.c static void

Quoted 21 lines
(quoted diff) +0 -0

b/drivers/gpu/drm/i915/i915_reg.h index 36805b6..435c372 100644

drivers/gpu/drm/i915/i915_reg.h +3 -0
@@ -6881,6 +6881,9 @@ enum skl_disp_power_wells {
 #define   AUDIO_CP_READY(trans)		((1 << 1) << ((trans) * 4))
 #define   AUDIO_ELD_VALID(trans)	((1 << 0) << ((trans) * 4))
 
+#define HSW_AUD_CHICKENBIT			0x65f10
+#define   SKL_AUD_CODEC_WAKE_SIGNAL		(1 << 15)
+
 /* HSW Power Wells */
 #define HSW_PWR_WELL_BIOS			0x45400 /* CTL1 */
 #define HSW_PWR_WELL_DRIVER			0x45404 /* CTL2 */
drivers/gpu/drm/i915/intel_audio.c +0 -0
index f72e93a..ceb2328 100644
@@ -474,6 +474,32 @@ static void

i915_audio_component_put_power(struct device *dev)

drivers/gpu/drm/i915/intel_audio.c static void · line 474

Quoted 1 line
drivers/gpu/drm/i915/intel_audio.c +0 -0
 	intel_display_power_put(dev_to_i915(dev),

POWER_DOMAIN_AUDIO); }

drivers/gpu/drm/i915/intel_audio.c static void · line 475

Quoted 2 lines
drivers/gpu/drm/i915/intel_audio.c +1 -0
+static void i915_audio_component_codec_wake_override(struct device

*dev,

drivers/gpu/drm/i915/intel_audio.c static const struct i915_audio_component_ops

Quoted 28 lines
drivers/gpu/drm/i915/intel_audio.c +25 -0
+						     bool enable)
+{
+	struct drm_i915_private *dev_priv = dev_to_i915(dev);
+	u32 tmp;
+
+	if (!IS_SKYLAKE(dev_priv))
+		return;
+
+	/*
+	 * Enable/disable generating the codec wake signal, overriding the
+	 * internal logic to generate the codec wake to controller.
+	 */
+	tmp = I915_READ(HSW_AUD_CHICKENBIT);
+	tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
+	I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+	usleep_range(1000, 1500);
+
+	if (enable) {
+		tmp = I915_READ(HSW_AUD_CHICKENBIT);
+		tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
+		I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
+		usleep_range(1000, 1500);
+	}
+}
+
 /* Get CDCLK in kHz  */
 static int i915_audio_component_get_cdclk_freq(struct device *dev)  {
@@ -495,6 +521,7 @@ static const struct i915_audio_component_ops

i915_audio_component_ops = {

drivers/gpu/drm/i915/intel_audio.c static const struct i915_audio_component_ops i915_audio_component_ops = {

Quoted 4 lines
drivers/gpu/drm/i915/intel_audio.c +1 -0
 	.owner		= THIS_MODULE,
 	.get_power	= i915_audio_component_get_power,
 	.put_power	= i915_audio_component_put_power,
+	.codec_wake_override =

i915_audio_component_codec_wake_override,

Quoted 3 lines
drivers/gpu/drm/i915/intel_audio.c +0 -0
 	.get_cdclk_freq	= i915_audio_component_get_cdclk_freq,
 };
 
Quoted 19 lines
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
(quoted diff) +0 -0

b/include/drm/i915_component.h index 3e2f22e..c9a8b64 100644

include/drm/i915_component.h +1 -1
@@ -31,6 +31,7 @@ struct i915_audio_component {
 		struct module *owner;
 		void (*get_power)(struct device *);
 		void (*put_power)(struct device *);
+		void (*codec_wake_override)(struct device *, bool enable);
 		int (*get_cdclk_freq)(struct device *);
 	} *ops;
 };
--

1.9.1

Signature · 1 line
Jani Nikula, Intel Open Source Technology Center

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